drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <linux/hrtimer.h>      /* ktime_get_real() */
  60 #include <trace/events/power.h>
  61 #include <linux/sched.h>
  62 #include <linux/notifier.h>
  63 #include <linux/cpu.h>
  64 #include <asm/mwait.h>
  65
  66 #define INTEL_IDLE_VERSION "0.4"
  67 #define PREFIX "intel_idle: "
  68
  69 static struct cpuidle_driver intel_idle_driver = {
  70         .name = "intel_idle",
  71         .owner = THIS_MODULE,
  72 };
  73 /* intel_idle.max_cstate=0 disables driver */
  74 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  75
  76 static unsigned int mwait_substates;
  77
  78 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  79 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  80 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  81
  82 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  83 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  84
  85 static struct cpuidle_state *cpuidle_state_table;
  86
  87 /*
  88  * Set this flag for states where the HW flushes the TLB for us
  89  * and so we don't need cross-calls to keep it consistent.
  90  * If this flag is set, SW flushes the TLB, so even if the
  91  * HW doesn't do the flushing, this flag is safe to use.
  92  */
  93 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
  94
  95 /*
  96  * States are indexed by the cstate number,
  97  * which is also the index into the MWAIT hint array.
  98  * Thus C0 is a dummy.
  99  */
 100 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
 101         { /* MWAIT C0 */ },
 102         { /* MWAIT C1 */
 103                 .name = "NHM-C1",
 104                 .desc = "MWAIT 0x00",
 105                 .driver_data = (void *) 0x00,
 106                 .flags = CPUIDLE_FLAG_TIME_VALID,
 107                 .exit_latency = 3,
 108                 .target_residency = 6,
 109                 .enter = &intel_idle },
 110         { /* MWAIT C2 */
 111                 .name = "NHM-C3",
 112                 .desc = "MWAIT 0x10",
 113                 .driver_data = (void *) 0x10,
 114                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 115                 .exit_latency = 20,
 116                 .target_residency = 80,
 117                 .enter = &intel_idle },
 118         { /* MWAIT C3 */
 119                 .name = "NHM-C6",
 120                 .desc = "MWAIT 0x20",
 121                 .driver_data = (void *) 0x20,
 122                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 123                 .exit_latency = 200,
 124                 .target_residency = 800,
 125                 .enter = &intel_idle },
 126 };
 127
 128 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 129         { /* MWAIT C0 */ },
 130         { /* MWAIT C1 */
 131                 .name = "SNB-C1",
 132                 .desc = "MWAIT 0x00",
 133                 .driver_data = (void *) 0x00,
 134                 .flags = CPUIDLE_FLAG_TIME_VALID,
 135                 .exit_latency = 1,
 136                 .target_residency = 1,
 137                 .enter = &intel_idle },
 138         { /* MWAIT C2 */
 139                 .name = "SNB-C3",
 140                 .desc = "MWAIT 0x10",
 141                 .driver_data = (void *) 0x10,
 142                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 143                 .exit_latency = 80,
 144                 .target_residency = 211,
 145                 .enter = &intel_idle },
 146         { /* MWAIT C3 */
 147                 .name = "SNB-C6",
 148                 .desc = "MWAIT 0x20",
 149                 .driver_data = (void *) 0x20,
 150                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 151                 .exit_latency = 104,
 152                 .target_residency = 345,
 153                 .enter = &intel_idle },
 154         { /* MWAIT C4 */
 155                 .name = "SNB-C7",
 156                 .desc = "MWAIT 0x30",
 157                 .driver_data = (void *) 0x30,
 158                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 159                 .exit_latency = 109,
 160                 .target_residency = 345,
 161                 .enter = &intel_idle },
 162 };
 163
 164 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 165         { /* MWAIT C0 */ },
 166         { /* MWAIT C1 */
 167                 .name = "ATM-C1",
 168                 .desc = "MWAIT 0x00",
 169                 .driver_data = (void *) 0x00,
 170                 .flags = CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 1,
 172                 .target_residency = 4,
 173                 .enter = &intel_idle },
 174         { /* MWAIT C2 */
 175                 .name = "ATM-C2",
 176                 .desc = "MWAIT 0x10",
 177                 .driver_data = (void *) 0x10,
 178                 .flags = CPUIDLE_FLAG_TIME_VALID,
 179                 .exit_latency = 20,
 180                 .target_residency = 80,
 181                 .enter = &intel_idle },
 182         { /* MWAIT C3 */ },
 183         { /* MWAIT C4 */
 184                 .name = "ATM-C4",
 185                 .desc = "MWAIT 0x30",
 186                 .driver_data = (void *) 0x30,
 187                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 188                 .exit_latency = 100,
 189                 .target_residency = 400,
 190                 .enter = &intel_idle },
 191         { /* MWAIT C5 */ },
 192         { /* MWAIT C6 */
 193                 .name = "ATM-C6",
 194                 .desc = "MWAIT 0x52",
 195                 .driver_data = (void *) 0x52,
 196                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 197                 .exit_latency = 140,
 198                 .target_residency = 560,
 199                 .enter = &intel_idle },
 200 };
 201
 202 /**
 203  * intel_idle
 204  * @dev: cpuidle_device
 205  * @state: cpuidle state
 206  *
 207  */
 208 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
 209 {
 210         unsigned long ecx = 1; /* break on interrupt flag */
 211         unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
 212         unsigned int cstate;
 213         ktime_t kt_before, kt_after;
 214         s64 usec_delta;
 215         int cpu = smp_processor_id();
 216
 217         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 218
 219         local_irq_disable();
 220
 221         /*
 222          * leave_mm() to avoid costly and often unnecessary wakeups
 223          * for flushing the user TLB's associated with the active mm.
 224          */
 225         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 226                 leave_mm(cpu);
 227
 228         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 229                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 230
 231         kt_before = ktime_get_real();
 232
 233         stop_critical_timings();
 234         if (!need_resched()) {
 235
 236                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 237                 smp_mb();
 238                 if (!need_resched())
 239                         __mwait(eax, ecx);
 240         }
 241
 242         start_critical_timings();
 243
 244         kt_after = ktime_get_real();
 245         usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
 246
 247         local_irq_enable();
 248
 249         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 250                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 251
 252         return usec_delta;
 253 }
 254
 255 static void __setup_broadcast_timer(void *arg)
 256 {
 257         unsigned long reason = (unsigned long)arg;
 258         int cpu = smp_processor_id();
 259
 260         reason = reason ?
 261                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 262
 263         clockevents_notify(reason, &cpu);
 264 }
 265
 266 static int setup_broadcast_cpuhp_notify(struct notifier_block *n,
 267                 unsigned long action, void *hcpu)
 268 {
 269         int hotcpu = (unsigned long)hcpu;
 270
 271         switch (action & 0xf) {
 272         case CPU_ONLINE:
 273                 smp_call_function_single(hotcpu, __setup_broadcast_timer,
 274                         (void *)true, 1);
 275                 break;
 276         }
 277         return NOTIFY_OK;
 278 }
 279
 280 static struct notifier_block setup_broadcast_notifier = {
 281         .notifier_call = setup_broadcast_cpuhp_notify,
 282 };
 283
 284 /*
 285  * intel_idle_probe()
 286  */
 287 static int intel_idle_probe(void)
 288 {
 289         unsigned int eax, ebx, ecx;
 290
 291         if (max_cstate == 0) {
 292                 pr_debug(PREFIX "disabled\n");
 293                 return -EPERM;
 294         }
 295
 296         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 297                 return -ENODEV;
 298
 299         if (!boot_cpu_has(X86_FEATURE_MWAIT))
 300                 return -ENODEV;
 301
 302         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 303                 return -ENODEV;
 304
 305         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 306
 307         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 308                 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
 309                         return -ENODEV;
 310
 311         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 312
 313
 314         if (boot_cpu_data.x86 != 6)     /* family 6 */
 315                 return -ENODEV;
 316
 317         switch (boot_cpu_data.x86_model) {
 318
 319         case 0x1A:      /* Core i7, Xeon 5500 series */
 320         case 0x1E:      /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
 321         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
 322         case 0x2E:      /* Nehalem-EX Xeon */
 323         case 0x2F:      /* Westmere-EX Xeon */
 324         case 0x25:      /* Westmere */
 325         case 0x2C:      /* Westmere */
 326                 cpuidle_state_table = nehalem_cstates;
 327                 break;
 328
 329         case 0x1C:      /* 28 - Atom Processor */
 330         case 0x26:      /* 38 - Lincroft Atom Processor */
 331                 cpuidle_state_table = atom_cstates;
 332                 break;
 333
 334         case 0x2A:      /* SNB */
 335         case 0x2D:      /* SNB Xeon */
 336                 cpuidle_state_table = snb_cstates;
 337                 break;
 338
 339         default:
 340                 pr_debug(PREFIX "does not run on family %d model %d\n",
 341                         boot_cpu_data.x86, boot_cpu_data.x86_model);
 342                 return -ENODEV;
 343         }
 344
 345         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 346                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 347         else {
 348                 smp_call_function(__setup_broadcast_timer, (void *)true, 1);
 349                 register_cpu_notifier(&setup_broadcast_notifier);
 350         }
 351
 352         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 353                 " model 0x%X\n", boot_cpu_data.x86_model);
 354
 355         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 356                 lapic_timer_reliable_states);
 357         return 0;
 358 }
 359
 360 /*
 361  * intel_idle_cpuidle_devices_uninit()
 362  * unregister, free cpuidle_devices
 363  */
 364 static void intel_idle_cpuidle_devices_uninit(void)
 365 {
 366         int i;
 367         struct cpuidle_device *dev;
 368
 369         for_each_online_cpu(i) {
 370                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 371                 cpuidle_unregister_device(dev);
 372         }
 373
 374         free_percpu(intel_idle_cpuidle_devices);
 375         return;
 376 }
 377 /*
 378  * intel_idle_cpuidle_devices_init()
 379  * allocate, initialize, register cpuidle_devices
 380  */
 381 static int intel_idle_cpuidle_devices_init(void)
 382 {
 383         int i, cstate;
 384         struct cpuidle_device *dev;
 385
 386         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 387         if (intel_idle_cpuidle_devices == NULL)
 388                 return -ENOMEM;
 389
 390         for_each_online_cpu(i) {
 391                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 392
 393                 dev->state_count = 1;
 394
 395                 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 396                         int num_substates;
 397
 398                         if (cstate > max_cstate) {
 399                                 printk(PREFIX "max_cstate %d reached\n",
 400                                         max_cstate);
 401                                 break;
 402                         }
 403
 404                         /* does the state exist in CPUID.MWAIT? */
 405                         num_substates = (mwait_substates >> ((cstate) * 4))
 406                                                 & MWAIT_SUBSTATE_MASK;
 407                         if (num_substates == 0)
 408                                 continue;
 409                         /* is the state not enabled? */
 410                         if (cpuidle_state_table[cstate].enter == NULL) {
 411                                 /* does the driver not know about the state? */
 412                                 if (*cpuidle_state_table[cstate].name == '\0')
 413                                         pr_debug(PREFIX "unaware of model 0x%x"
 414                                                 " MWAIT %d please"
 415                                                 " contact lenb@kernel.org",
 416                                         boot_cpu_data.x86_model, cstate);
 417                                 continue;
 418                         }
 419
 420                         if ((cstate > 2) &&
 421                                 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 422                                 mark_tsc_unstable("TSC halts in idle"
 423                                         " states deeper than C2");
 424
 425                         dev->states[dev->state_count] = /* structure copy */
 426                                 cpuidle_state_table[cstate];
 427
 428                         dev->state_count += 1;
 429                 }
 430
 431                 dev->cpu = i;
 432                 if (cpuidle_register_device(dev)) {
 433                         pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
 434                                  i);
 435                         intel_idle_cpuidle_devices_uninit();
 436                         return -EIO;
 437                 }
 438         }
 439
 440         return 0;
 441 }
 442
 443
 444 static int __init intel_idle_init(void)
 445 {
 446         int retval;
 447
 448         /* Do not load intel_idle at all for now if idle= is passed */
 449         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 450                 return -ENODEV;
 451
 452         retval = intel_idle_probe();
 453         if (retval)
 454                 return retval;
 455
 456         retval = cpuidle_register_driver(&intel_idle_driver);
 457         if (retval) {
 458                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 459                         cpuidle_get_driver()->name);
 460                 return retval;
 461         }
 462
 463         retval = intel_idle_cpuidle_devices_init();
 464         if (retval) {
 465                 cpuidle_unregister_driver(&intel_idle_driver);
 466                 return retval;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static void __exit intel_idle_exit(void)
 473 {
 474         intel_idle_cpuidle_devices_uninit();
 475         cpuidle_unregister_driver(&intel_idle_driver);
 476
 477         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
 478                 smp_call_function(__setup_broadcast_timer, (void *)false, 1);
 479                 unregister_cpu_notifier(&setup_broadcast_notifier);
 480         }
 481
 482         return;
 483 }
 484
 485 module_init(intel_idle_init);
 486 module_exit(intel_idle_exit);
 487
 488 module_param(max_cstate, int, 0444);
 489
 490 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 491 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 492 MODULE_LICENSE("GPL");