drivers/gpu/drm/i915/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/i2c.h>
  28 #include <linux/slab.h>
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc.h"
  32 #include "drm_crtc_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36
  37 static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  38 {
  39         struct drm_device *dev = encoder->dev;
  40         struct drm_i915_private *dev_priv = dev->dev_private;
  41         u32 temp, reg;
  42
  43         if (HAS_PCH_SPLIT(dev))
  44                 reg = PCH_ADPA;
  45         else
  46                 reg = ADPA;
  47
  48         temp = I915_READ(reg);
  49         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  50         temp &= ~ADPA_DAC_ENABLE;
  51
  52         switch(mode) {
  53         case DRM_MODE_DPMS_ON:
  54                 temp |= ADPA_DAC_ENABLE;
  55                 break;
  56         case DRM_MODE_DPMS_STANDBY:
  57                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  58                 break;
  59         case DRM_MODE_DPMS_SUSPEND:
  60                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  61                 break;
  62         case DRM_MODE_DPMS_OFF:
  63                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  64                 break;
  65         }
  66
  67         I915_WRITE(reg, temp);
  68 }
  69
  70 static int intel_crt_mode_valid(struct drm_connector *connector,
  71                                 struct drm_display_mode *mode)
  72 {
  73         struct drm_device *dev = connector->dev;
  74
  75         int max_clock = 0;
  76         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  77                 return MODE_NO_DBLESCAN;
  78
  79         if (mode->clock < 25000)
  80                 return MODE_CLOCK_LOW;
  81
  82         if (!IS_I9XX(dev))
  83                 max_clock = 350000;
  84         else
  85                 max_clock = 400000;
  86         if (mode->clock > max_clock)
  87                 return MODE_CLOCK_HIGH;
  88
  89         return MODE_OK;
  90 }
  91
  92 static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  93                                  struct drm_display_mode *mode,
  94                                  struct drm_display_mode *adjusted_mode)
  95 {
  96         return true;
  97 }
  98
  99 static void intel_crt_mode_set(struct drm_encoder *encoder,
 100                                struct drm_display_mode *mode,
 101                                struct drm_display_mode *adjusted_mode)
 102 {
 103
 104         struct drm_device *dev = encoder->dev;
 105         struct drm_crtc *crtc = encoder->crtc;
 106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 107         struct drm_i915_private *dev_priv = dev->dev_private;
 108         int dpll_md_reg;
 109         u32 adpa, dpll_md;
 110         u32 adpa_reg;
 111
 112         if (intel_crtc->pipe == 0)
 113                 dpll_md_reg = DPLL_A_MD;
 114         else
 115                 dpll_md_reg = DPLL_B_MD;
 116
 117         if (HAS_PCH_SPLIT(dev))
 118                 adpa_reg = PCH_ADPA;
 119         else
 120                 adpa_reg = ADPA;
 121
 122         /*
 123          * Disable separate mode multiplier used when cloning SDVO to CRT
 124          * XXX this needs to be adjusted when we really are cloning
 125          */
 126         if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
 127                 dpll_md = I915_READ(dpll_md_reg);
 128                 I915_WRITE(dpll_md_reg,
 129                            dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
 130         }
 131
 132         adpa = 0;
 133         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 134                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 135         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 136                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 137
 138         if (intel_crtc->pipe == 0) {
 139                 adpa |= ADPA_PIPE_A_SELECT;
 140                 if (!HAS_PCH_SPLIT(dev))
 141                         I915_WRITE(BCLRPAT_A, 0);
 142         } else {
 143                 adpa |= ADPA_PIPE_B_SELECT;
 144                 if (!HAS_PCH_SPLIT(dev))
 145                         I915_WRITE(BCLRPAT_B, 0);
 146         }
 147
 148         I915_WRITE(adpa_reg, adpa);
 149 }
 150
 151 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 152 {
 153         struct drm_device *dev = connector->dev;
 154         struct drm_i915_private *dev_priv = dev->dev_private;
 155         u32 adpa;
 156         bool ret;
 157
 158         adpa = I915_READ(PCH_ADPA);
 159
 160         adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 161         /* disable HPD first */
 162         I915_WRITE(PCH_ADPA, adpa);
 163         (void)I915_READ(PCH_ADPA);
 164
 165         adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
 166                         ADPA_CRT_HOTPLUG_WARMUP_10MS |
 167                         ADPA_CRT_HOTPLUG_SAMPLE_4S |
 168                         ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
 169                         ADPA_CRT_HOTPLUG_VOLREF_325MV |
 170                         ADPA_CRT_HOTPLUG_ENABLE |
 171                         ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
 172
 173         DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
 174         I915_WRITE(PCH_ADPA, adpa);
 175
 176         while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0)
 177                 ;
 178
 179         /* Check the status to see if both blue and green are on now */
 180         adpa = I915_READ(PCH_ADPA);
 181         adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
 182         if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
 183                 (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
 184                 ret = true;
 185         else
 186                 ret = false;
 187
 188         return ret;
 189 }
 190
 191 /**
 192  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
 193  *
 194  * Not for i915G/i915GM
 195  *
 196  * \return true if CRT is connected.
 197  * \return false if CRT is disconnected.
 198  */
 199 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 200 {
 201         struct drm_device *dev = connector->dev;
 202         struct drm_i915_private *dev_priv = dev->dev_private;
 203         u32 hotplug_en;
 204         int i, tries = 0;
 205
 206         if (HAS_PCH_SPLIT(dev))
 207                 return intel_ironlake_crt_detect_hotplug(connector);
 208
 209         /*
 210          * On 4 series desktop, CRT detect sequence need to be done twice
 211          * to get a reliable result.
 212          */
 213
 214         if (IS_G4X(dev) && !IS_GM45(dev))
 215                 tries = 2;
 216         else
 217                 tries = 1;
 218         hotplug_en = I915_READ(PORT_HOTPLUG_EN);
 219         hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
 220         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 221
 222         if (IS_G4X(dev))
 223                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
 224
 225         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
 226
 227         for (i = 0; i < tries ; i++) {
 228                 unsigned long timeout;
 229                 /* turn on the FORCE_DETECT */
 230                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
 231                 timeout = jiffies + msecs_to_jiffies(1000);
 232                 /* wait for FORCE_DETECT to go off */
 233                 do {
 234                         if (!(I915_READ(PORT_HOTPLUG_EN) &
 235                                         CRT_HOTPLUG_FORCE_DETECT))
 236                                 break;
 237                         msleep(1);
 238                 } while (time_after(timeout, jiffies));
 239         }
 240
 241         if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
 242             CRT_HOTPLUG_MONITOR_NONE)
 243                 return true;
 244
 245         return false;
 246 }
 247
 248 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 249 {
 250         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 251
 252         /* CRT should always be at 0, but check anyway */
 253         if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
 254                 return false;
 255
 256         return intel_ddc_probe(intel_encoder);
 257 }
 258
 259 static enum drm_connector_status
 260 intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
 261 {
 262         struct drm_encoder *encoder = &intel_encoder->enc;
 263         struct drm_device *dev = encoder->dev;
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 266         uint32_t pipe = intel_crtc->pipe;
 267         uint32_t save_bclrpat;
 268         uint32_t save_vtotal;
 269         uint32_t vtotal, vactive;
 270         uint32_t vsample;
 271         uint32_t vblank, vblank_start, vblank_end;
 272         uint32_t dsl;
 273         uint32_t bclrpat_reg;
 274         uint32_t vtotal_reg;
 275         uint32_t vblank_reg;
 276         uint32_t vsync_reg;
 277         uint32_t pipeconf_reg;
 278         uint32_t pipe_dsl_reg;
 279         uint8_t st00;
 280         enum drm_connector_status status;
 281
 282         if (pipe == 0) {
 283                 bclrpat_reg = BCLRPAT_A;
 284                 vtotal_reg = VTOTAL_A;
 285                 vblank_reg = VBLANK_A;
 286                 vsync_reg = VSYNC_A;
 287                 pipeconf_reg = PIPEACONF;
 288                 pipe_dsl_reg = PIPEADSL;
 289         } else {
 290                 bclrpat_reg = BCLRPAT_B;
 291                 vtotal_reg = VTOTAL_B;
 292                 vblank_reg = VBLANK_B;
 293                 vsync_reg = VSYNC_B;
 294                 pipeconf_reg = PIPEBCONF;
 295                 pipe_dsl_reg = PIPEBDSL;
 296         }
 297
 298         save_bclrpat = I915_READ(bclrpat_reg);
 299         save_vtotal = I915_READ(vtotal_reg);
 300         vblank = I915_READ(vblank_reg);
 301
 302         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
 303         vactive = (save_vtotal & 0x7ff) + 1;
 304
 305         vblank_start = (vblank & 0xfff) + 1;
 306         vblank_end = ((vblank >> 16) & 0xfff) + 1;
 307
 308         /* Set the border color to purple. */
 309         I915_WRITE(bclrpat_reg, 0x500050);
 310
 311         if (IS_I9XX(dev)) {
 312                 uint32_t pipeconf = I915_READ(pipeconf_reg);
 313                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
 314                 /* Wait for next Vblank to substitue
 315                  * border color for Color info */
 316                 intel_wait_for_vblank(dev);
 317                 st00 = I915_READ8(VGA_MSR_WRITE);
 318                 status = ((st00 & (1 << 4)) != 0) ?
 319                         connector_status_connected :
 320                         connector_status_disconnected;
 321
 322                 I915_WRITE(pipeconf_reg, pipeconf);
 323         } else {
 324                 bool restore_vblank = false;
 325                 int count, detect;
 326
 327                 /*
 328                 * If there isn't any border, add some.
 329                 * Yes, this will flicker
 330                 */
 331                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 332                         uint32_t vsync = I915_READ(vsync_reg);
 333                         uint32_t vsync_start = (vsync & 0xffff) + 1;
 334
 335                         vblank_start = vsync_start;
 336                         I915_WRITE(vblank_reg,
 337                                    (vblank_start - 1) |
 338                                    ((vblank_end - 1) << 16));
 339                         restore_vblank = true;
 340                 }
 341                 /* sample in the vertical border, selecting the larger one */
 342                 if (vblank_start - vactive >= vtotal - vblank_end)
 343                         vsample = (vblank_start + vactive) >> 1;
 344                 else
 345                         vsample = (vtotal + vblank_end) >> 1;
 346
 347                 /*
 348                  * Wait for the border to be displayed
 349                  */
 350                 while (I915_READ(pipe_dsl_reg) >= vactive)
 351                         ;
 352                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
 353                         ;
 354                 /*
 355                  * Watch ST00 for an entire scanline
 356                  */
 357                 detect = 0;
 358                 count = 0;
 359                 do {
 360                         count++;
 361                         /* Read the ST00 VGA status register */
 362                         st00 = I915_READ8(VGA_MSR_WRITE);
 363                         if (st00 & (1 << 4))
 364                                 detect++;
 365                 } while ((I915_READ(pipe_dsl_reg) == dsl));
 366
 367                 /* restore vblank if necessary */
 368                 if (restore_vblank)
 369                         I915_WRITE(vblank_reg, vblank);
 370                 /*
 371                  * If more than 3/4 of the scanline detected a monitor,
 372                  * then it is assumed to be present. This works even on i830,
 373                  * where there isn't any way to force the border color across
 374                  * the screen
 375                  */
 376                 status = detect * 4 > count * 3 ?
 377                          connector_status_connected :
 378                          connector_status_disconnected;
 379         }
 380
 381         /* Restore previous settings */
 382         I915_WRITE(bclrpat_reg, save_bclrpat);
 383
 384         return status;
 385 }
 386
 387 static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
 388 {
 389         struct drm_device *dev = connector->dev;
 390         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 391         struct drm_encoder *encoder = &intel_encoder->enc;
 392         struct drm_crtc *crtc;
 393         int dpms_mode;
 394         enum drm_connector_status status;
 395
 396         if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
 397                 if (intel_crt_detect_hotplug(connector))
 398                         return connector_status_connected;
 399                 else
 400                         return connector_status_disconnected;
 401         }
 402
 403         if (intel_crt_detect_ddc(connector))
 404                 return connector_status_connected;
 405
 406         /* for pre-945g platforms use load detect */
 407         if (encoder->crtc && encoder->crtc->enabled) {
 408                 status = intel_crt_load_detect(encoder->crtc, intel_encoder);
 409         } else {
 410                 crtc = intel_get_load_detect_pipe(intel_encoder,
 411                                                   NULL, &dpms_mode);
 412                 if (crtc) {
 413                         status = intel_crt_load_detect(crtc, intel_encoder);
 414                         intel_release_load_detect_pipe(intel_encoder, dpms_mode);
 415                 } else
 416                         status = connector_status_unknown;
 417         }
 418
 419         return status;
 420 }
 421
 422 static void intel_crt_destroy(struct drm_connector *connector)
 423 {
 424         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 425
 426         intel_i2c_destroy(intel_encoder->ddc_bus);
 427         drm_sysfs_connector_remove(connector);
 428         drm_connector_cleanup(connector);
 429         kfree(connector);
 430 }
 431
 432 static int intel_crt_get_modes(struct drm_connector *connector)
 433 {
 434         int ret;
 435         struct intel_encoder *intel_encoder = to_intel_encoder(connector);
 436         struct i2c_adapter *ddcbus;
 437         struct drm_device *dev = connector->dev;
 438
 439
 440         ret = intel_ddc_get_modes(intel_encoder);
 441         if (ret || !IS_G4X(dev))
 442                 goto end;
 443
 444         ddcbus = intel_encoder->ddc_bus;
 445         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 446         intel_encoder->ddc_bus =
 447                 intel_i2c_create(connector->dev, GPIOD, "CRTDDC_D");
 448
 449         if (!intel_encoder->ddc_bus) {
 450                 intel_encoder->ddc_bus = ddcbus;
 451                 dev_printk(KERN_ERR, &connector->dev->pdev->dev,
 452                            "DDC bus registration failed for CRTDDC_D.\n");
 453                 goto end;
 454         }
 455         /* Try to get modes by GPIOD port */
 456         ret = intel_ddc_get_modes(intel_encoder);
 457         intel_i2c_destroy(ddcbus);
 458
 459 end:
 460         return ret;
 461
 462 }
 463
 464 static int intel_crt_set_property(struct drm_connector *connector,
 465                                   struct drm_property *property,
 466                                   uint64_t value)
 467 {
 468         return 0;
 469 }
 470
 471 /*
 472  * Routines for controlling stuff on the analog port
 473  */
 474
 475 static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
 476         .dpms = intel_crt_dpms,
 477         .mode_fixup = intel_crt_mode_fixup,
 478         .prepare = intel_encoder_prepare,
 479         .commit = intel_encoder_commit,
 480         .mode_set = intel_crt_mode_set,
 481 };
 482
 483 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 484         .dpms = drm_helper_connector_dpms,
 485         .detect = intel_crt_detect,
 486         .fill_modes = drm_helper_probe_single_connector_modes,
 487         .destroy = intel_crt_destroy,
 488         .set_property = intel_crt_set_property,
 489 };
 490
 491 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 492         .mode_valid = intel_crt_mode_valid,
 493         .get_modes = intel_crt_get_modes,
 494         .best_encoder = intel_best_encoder,
 495 };
 496
 497 static void intel_crt_enc_destroy(struct drm_encoder *encoder)
 498 {
 499         drm_encoder_cleanup(encoder);
 500 }
 501
 502 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 503         .destroy = intel_crt_enc_destroy,
 504 };
 505
 506 void intel_crt_init(struct drm_device *dev)
 507 {
 508         struct drm_connector *connector;
 509         struct intel_encoder *intel_encoder;
 510         struct drm_i915_private *dev_priv = dev->dev_private;
 511         u32 i2c_reg;
 512
 513         intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
 514         if (!intel_encoder)
 515                 return;
 516
 517         connector = &intel_encoder->base;
 518         drm_connector_init(dev, &intel_encoder->base,
 519                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
 520
 521         drm_encoder_init(dev, &intel_encoder->enc, &intel_crt_enc_funcs,
 522                          DRM_MODE_ENCODER_DAC);
 523
 524         drm_mode_connector_attach_encoder(&intel_encoder->base,
 525                                           &intel_encoder->enc);
 526
 527         /* Set up the DDC bus. */
 528         if (HAS_PCH_SPLIT(dev))
 529                 i2c_reg = PCH_GPIOA;
 530         else {
 531                 i2c_reg = GPIOA;
 532                 /* Use VBT information for CRT DDC if available */
 533                 if (dev_priv->crt_ddc_bus != 0)
 534                         i2c_reg = dev_priv->crt_ddc_bus;
 535         }
 536         intel_encoder->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
 537         if (!intel_encoder->ddc_bus) {
 538                 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
 539                            "failed.\n");
 540                 return;
 541         }
 542
 543         intel_encoder->type = INTEL_OUTPUT_ANALOG;
 544         intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
 545                                    (1 << INTEL_ANALOG_CLONE_BIT) |
 546                                    (1 << INTEL_SDVO_LVDS_CLONE_BIT);
 547         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
 548         connector->interlace_allowed = 0;
 549         connector->doublescan_allowed = 0;
 550
 551         drm_encoder_helper_add(&intel_encoder->enc, &intel_crt_helper_funcs);
 552         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
 553
 554         drm_sysfs_connector_add(connector);
 555
 556         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
 557 }