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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / intel_display.c
blobc7502b6b16009205b9ba0eb27e7158c75035e578
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
41
42 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
43 static void intel_update_watermarks(struct drm_device *dev);
44 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
45
46 typedef struct {
47 /* given values */
48 int n;
49 int m1, m2;
50 int p1, p2;
51 /* derived values */
52 int dot;
53 int vco;
54 int m;
55 int p;
56 } intel_clock_t;
57
58 typedef struct {
59 int min, max;
60 } intel_range_t;
61
62 typedef struct {
63 int dot_limit;
64 int p2_slow, p2_fast;
65 } intel_p2_t;
66
67 #define INTEL_P2_NUM 2
68 typedef struct intel_limit intel_limit_t;
69 struct intel_limit {
70 intel_range_t dot, vco, n, m, m1, m2, p, p1;
71 intel_p2_t p2;
72 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
73 int, int, intel_clock_t *);
74 };
75
76 #define I8XX_DOT_MIN 25000
77 #define I8XX_DOT_MAX 350000
78 #define I8XX_VCO_MIN 930000
79 #define I8XX_VCO_MAX 1400000
80 #define I8XX_N_MIN 3
81 #define I8XX_N_MAX 16
82 #define I8XX_M_MIN 96
83 #define I8XX_M_MAX 140
84 #define I8XX_M1_MIN 18
85 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MIN 6
87 #define I8XX_M2_MAX 16
88 #define I8XX_P_MIN 4
89 #define I8XX_P_MAX 128
90 #define I8XX_P1_MIN 2
91 #define I8XX_P1_MAX 33
92 #define I8XX_P1_LVDS_MIN 1
93 #define I8XX_P1_LVDS_MAX 6
94 #define I8XX_P2_SLOW 4
95 #define I8XX_P2_FAST 2
96 #define I8XX_P2_LVDS_SLOW 14
97 #define I8XX_P2_LVDS_FAST 7
98 #define I8XX_P2_SLOW_LIMIT 165000
99
100 #define I9XX_DOT_MIN 20000
101 #define I9XX_DOT_MAX 400000
102 #define I9XX_VCO_MIN 1400000
103 #define I9XX_VCO_MAX 2800000
104 #define PINEVIEW_VCO_MIN 1700000
105 #define PINEVIEW_VCO_MAX 3500000
106 #define I9XX_N_MIN 1
107 #define I9XX_N_MAX 6
108 /* Pineview's Ncounter is a ring counter */
109 #define PINEVIEW_N_MIN 3
110 #define PINEVIEW_N_MAX 6
111 #define I9XX_M_MIN 70
112 #define I9XX_M_MAX 120
113 #define PINEVIEW_M_MIN 2
114 #define PINEVIEW_M_MAX 256
115 #define I9XX_M1_MIN 10
116 #define I9XX_M1_MAX 22
117 #define I9XX_M2_MIN 5
118 #define I9XX_M2_MAX 9
119 /* Pineview M1 is reserved, and must be 0 */
120 #define PINEVIEW_M1_MIN 0
121 #define PINEVIEW_M1_MAX 0
122 #define PINEVIEW_M2_MIN 0
123 #define PINEVIEW_M2_MAX 254
124 #define I9XX_P_SDVO_DAC_MIN 5
125 #define I9XX_P_SDVO_DAC_MAX 80
126 #define I9XX_P_LVDS_MIN 7
127 #define I9XX_P_LVDS_MAX 98
128 #define PINEVIEW_P_LVDS_MIN 7
129 #define PINEVIEW_P_LVDS_MAX 112
130 #define I9XX_P1_MIN 1
131 #define I9XX_P1_MAX 8
132 #define I9XX_P2_SDVO_DAC_SLOW 10
133 #define I9XX_P2_SDVO_DAC_FAST 5
134 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
135 #define I9XX_P2_LVDS_SLOW 14
136 #define I9XX_P2_LVDS_FAST 7
137 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138
139 /*The parameter is for SDVO on G4x platform*/
140 #define G4X_DOT_SDVO_MIN 25000
141 #define G4X_DOT_SDVO_MAX 270000
142 #define G4X_VCO_MIN 1750000
143 #define G4X_VCO_MAX 3500000
144 #define G4X_N_SDVO_MIN 1
145 #define G4X_N_SDVO_MAX 4
146 #define G4X_M_SDVO_MIN 104
147 #define G4X_M_SDVO_MAX 138
148 #define G4X_M1_SDVO_MIN 17
149 #define G4X_M1_SDVO_MAX 23
150 #define G4X_M2_SDVO_MIN 5
151 #define G4X_M2_SDVO_MAX 11
152 #define G4X_P_SDVO_MIN 10
153 #define G4X_P_SDVO_MAX 30
154 #define G4X_P1_SDVO_MIN 1
155 #define G4X_P1_SDVO_MAX 3
156 #define G4X_P2_SDVO_SLOW 10
157 #define G4X_P2_SDVO_FAST 10
158 #define G4X_P2_SDVO_LIMIT 270000
159
160 /*The parameter is for HDMI_DAC on G4x platform*/
161 #define G4X_DOT_HDMI_DAC_MIN 22000
162 #define G4X_DOT_HDMI_DAC_MAX 400000
163 #define G4X_N_HDMI_DAC_MIN 1
164 #define G4X_N_HDMI_DAC_MAX 4
165 #define G4X_M_HDMI_DAC_MIN 104
166 #define G4X_M_HDMI_DAC_MAX 138
167 #define G4X_M1_HDMI_DAC_MIN 16
168 #define G4X_M1_HDMI_DAC_MAX 23
169 #define G4X_M2_HDMI_DAC_MIN 5
170 #define G4X_M2_HDMI_DAC_MAX 11
171 #define G4X_P_HDMI_DAC_MIN 5
172 #define G4X_P_HDMI_DAC_MAX 80
173 #define G4X_P1_HDMI_DAC_MIN 1
174 #define G4X_P1_HDMI_DAC_MAX 8
175 #define G4X_P2_HDMI_DAC_SLOW 10
176 #define G4X_P2_HDMI_DAC_FAST 5
177 #define G4X_P2_HDMI_DAC_LIMIT 165000
178
179 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
181 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
183 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
185 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
187 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
189 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
191 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
193 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197
198 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
200 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
201 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
202 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
203 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
204 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
206 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
208 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
209 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
210 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
212 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
213 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
215 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216
217 /*The parameter is for DISPLAY PORT on G4x platform*/
218 #define G4X_DOT_DISPLAY_PORT_MIN 161670
219 #define G4X_DOT_DISPLAY_PORT_MAX 227000
220 #define G4X_N_DISPLAY_PORT_MIN 1
221 #define G4X_N_DISPLAY_PORT_MAX 2
222 #define G4X_M_DISPLAY_PORT_MIN 97
223 #define G4X_M_DISPLAY_PORT_MAX 108
224 #define G4X_M1_DISPLAY_PORT_MIN 0x10
225 #define G4X_M1_DISPLAY_PORT_MAX 0x12
226 #define G4X_M2_DISPLAY_PORT_MIN 0x05
227 #define G4X_M2_DISPLAY_PORT_MAX 0x06
228 #define G4X_P_DISPLAY_PORT_MIN 10
229 #define G4X_P_DISPLAY_PORT_MAX 20
230 #define G4X_P1_DISPLAY_PORT_MIN 1
231 #define G4X_P1_DISPLAY_PORT_MAX 2
232 #define G4X_P2_DISPLAY_PORT_SLOW 10
233 #define G4X_P2_DISPLAY_PORT_FAST 10
234 #define G4X_P2_DISPLAY_PORT_LIMIT 0
235
236 /* Ironlake / Sandybridge */
237 /* as we calculate clock using (register_value + 2) for
238 N/M1/M2, so here the range value for them is (actual_value-2).
239 */
240 #define IRONLAKE_DOT_MIN 25000
241 #define IRONLAKE_DOT_MAX 350000
242 #define IRONLAKE_VCO_MIN 1760000
243 #define IRONLAKE_VCO_MAX 3510000
244 #define IRONLAKE_M1_MIN 12
245 #define IRONLAKE_M1_MAX 22
246 #define IRONLAKE_M2_MIN 5
247 #define IRONLAKE_M2_MAX 9
248 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
249
250 /* We have parameter ranges for different type of outputs. */
251
252 /* DAC & HDMI Refclk 120Mhz */
253 #define IRONLAKE_DAC_N_MIN 1
254 #define IRONLAKE_DAC_N_MAX 5
255 #define IRONLAKE_DAC_M_MIN 79
256 #define IRONLAKE_DAC_M_MAX 127
257 #define IRONLAKE_DAC_P_MIN 5
258 #define IRONLAKE_DAC_P_MAX 80
259 #define IRONLAKE_DAC_P1_MIN 1
260 #define IRONLAKE_DAC_P1_MAX 8
261 #define IRONLAKE_DAC_P2_SLOW 10
262 #define IRONLAKE_DAC_P2_FAST 5
263
264 /* LVDS single-channel 120Mhz refclk */
265 #define IRONLAKE_LVDS_S_N_MIN 1
266 #define IRONLAKE_LVDS_S_N_MAX 3
267 #define IRONLAKE_LVDS_S_M_MIN 79
268 #define IRONLAKE_LVDS_S_M_MAX 118
269 #define IRONLAKE_LVDS_S_P_MIN 28
270 #define IRONLAKE_LVDS_S_P_MAX 112
271 #define IRONLAKE_LVDS_S_P1_MIN 2
272 #define IRONLAKE_LVDS_S_P1_MAX 8
273 #define IRONLAKE_LVDS_S_P2_SLOW 14
274 #define IRONLAKE_LVDS_S_P2_FAST 14
275
276 /* LVDS dual-channel 120Mhz refclk */
277 #define IRONLAKE_LVDS_D_N_MIN 1
278 #define IRONLAKE_LVDS_D_N_MAX 3
279 #define IRONLAKE_LVDS_D_M_MIN 79
280 #define IRONLAKE_LVDS_D_M_MAX 127
281 #define IRONLAKE_LVDS_D_P_MIN 14
282 #define IRONLAKE_LVDS_D_P_MAX 56
283 #define IRONLAKE_LVDS_D_P1_MIN 2
284 #define IRONLAKE_LVDS_D_P1_MAX 8
285 #define IRONLAKE_LVDS_D_P2_SLOW 7
286 #define IRONLAKE_LVDS_D_P2_FAST 7
287
288 /* LVDS single-channel 100Mhz refclk */
289 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
290 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
291 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
292 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
293 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
294 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
295 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
296 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
297 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
298 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
299
300 /* LVDS dual-channel 100Mhz refclk */
301 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
302 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
303 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
304 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
305 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
306 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
307 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
308 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
309 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
310 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
311
312 /* DisplayPort */
313 #define IRONLAKE_DP_N_MIN 1
314 #define IRONLAKE_DP_N_MAX 2
315 #define IRONLAKE_DP_M_MIN 81
316 #define IRONLAKE_DP_M_MAX 90
317 #define IRONLAKE_DP_P_MIN 10
318 #define IRONLAKE_DP_P_MAX 20
319 #define IRONLAKE_DP_P2_FAST 10
320 #define IRONLAKE_DP_P2_SLOW 10
321 #define IRONLAKE_DP_P2_LIMIT 0
322 #define IRONLAKE_DP_P1_MIN 1
323 #define IRONLAKE_DP_P1_MAX 2
324
325 static bool
326 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
327 int target, int refclk, intel_clock_t *best_clock);
328 static bool
329 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
330 int target, int refclk, intel_clock_t *best_clock);
331
332 static bool
333 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
334 int target, int refclk, intel_clock_t *best_clock);
335 static bool
336 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
337 int target, int refclk, intel_clock_t *best_clock);
338
339 static const intel_limit_t intel_limits_i8xx_dvo = {
340 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
341 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
342 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
343 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
344 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
345 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
346 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
347 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
348 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
349 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
350 .find_pll = intel_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_i8xx_lvds = {
354 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
355 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
356 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
357 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
358 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
359 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
360 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
361 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
362 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
363 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
364 .find_pll = intel_find_best_PLL,
365 };
366
367 static const intel_limit_t intel_limits_i9xx_sdvo = {
368 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
369 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
370 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
371 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
372 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
373 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
374 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
375 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
376 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
377 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
378 .find_pll = intel_find_best_PLL,
379 };
380
381 static const intel_limit_t intel_limits_i9xx_lvds = {
382 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
383 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
384 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
385 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
386 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
387 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
388 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
389 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
390 /* The single-channel range is 25-112Mhz, and dual-channel
391 * is 80-224Mhz. Prefer single channel as much as possible.
392 */
393 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
394 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
395 .find_pll = intel_find_best_PLL,
396 };
397
398 /* below parameter and function is for G4X Chipset Family*/
399 static const intel_limit_t intel_limits_g4x_sdvo = {
400 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
401 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
402 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
403 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
404 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
405 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
406 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
407 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
408 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
409 .p2_slow = G4X_P2_SDVO_SLOW,
410 .p2_fast = G4X_P2_SDVO_FAST
411 },
412 .find_pll = intel_g4x_find_best_PLL,
413 };
414
415 static const intel_limit_t intel_limits_g4x_hdmi = {
416 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
419 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
420 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
421 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
422 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
423 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
424 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
425 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
426 .p2_fast = G4X_P2_HDMI_DAC_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
432 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
433 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
434 .vco = { .min = G4X_VCO_MIN,
435 .max = G4X_VCO_MAX },
436 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
437 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
438 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
439 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
440 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
441 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
442 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
443 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
444 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
445 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
446 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
447 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
448 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
449 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
450 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
451 },
452 .find_pll = intel_g4x_find_best_PLL,
453 };
454
455 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
456 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
457 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
458 .vco = { .min = G4X_VCO_MIN,
459 .max = G4X_VCO_MAX },
460 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
461 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
462 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
463 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
464 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
465 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
466 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
467 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
468 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
469 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
470 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
471 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
472 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
473 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
474 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
475 },
476 .find_pll = intel_g4x_find_best_PLL,
477 };
478
479 static const intel_limit_t intel_limits_g4x_display_port = {
480 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
481 .max = G4X_DOT_DISPLAY_PORT_MAX },
482 .vco = { .min = G4X_VCO_MIN,
483 .max = G4X_VCO_MAX},
484 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
485 .max = G4X_N_DISPLAY_PORT_MAX },
486 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
487 .max = G4X_M_DISPLAY_PORT_MAX },
488 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
489 .max = G4X_M1_DISPLAY_PORT_MAX },
490 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
491 .max = G4X_M2_DISPLAY_PORT_MAX },
492 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
493 .max = G4X_P_DISPLAY_PORT_MAX },
494 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
495 .max = G4X_P1_DISPLAY_PORT_MAX},
496 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
497 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
498 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
499 .find_pll = intel_find_pll_g4x_dp,
500 };
501
502 static const intel_limit_t intel_limits_pineview_sdvo = {
503 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
504 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
505 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
506 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
507 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
508 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
509 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
510 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
511 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
512 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
513 .find_pll = intel_find_best_PLL,
514 };
515
516 static const intel_limit_t intel_limits_pineview_lvds = {
517 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
518 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
519 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
520 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
521 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
522 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
523 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
524 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
525 /* Pineview only supports single-channel mode. */
526 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
527 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
528 .find_pll = intel_find_best_PLL,
529 };
530
531 static const intel_limit_t intel_limits_ironlake_dac = {
532 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
533 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
534 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
535 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
536 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
537 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
538 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
539 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
540 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
541 .p2_slow = IRONLAKE_DAC_P2_SLOW,
542 .p2_fast = IRONLAKE_DAC_P2_FAST },
543 .find_pll = intel_g4x_find_best_PLL,
544 };
545
546 static const intel_limit_t intel_limits_ironlake_single_lvds = {
547 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
548 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
549 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
550 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
551 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
552 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
553 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
554 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
555 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
556 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
557 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
558 .find_pll = intel_g4x_find_best_PLL,
559 };
560
561 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
562 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
563 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
564 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
565 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
566 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
567 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
568 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
569 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
570 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
571 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
572 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
573 .find_pll = intel_g4x_find_best_PLL,
574 };
575
576 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
577 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
578 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
579 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
580 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
581 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
582 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
583 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
584 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
585 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
586 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
587 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
588 .find_pll = intel_g4x_find_best_PLL,
589 };
590
591 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
592 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
593 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
594 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
595 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
596 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
597 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
598 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
599 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
600 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
601 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
602 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
603 .find_pll = intel_g4x_find_best_PLL,
604 };
605
606 static const intel_limit_t intel_limits_ironlake_display_port = {
607 .dot = { .min = IRONLAKE_DOT_MIN,
608 .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN,
610 .max = IRONLAKE_VCO_MAX},
611 .n = { .min = IRONLAKE_DP_N_MIN,
612 .max = IRONLAKE_DP_N_MAX },
613 .m = { .min = IRONLAKE_DP_M_MIN,
614 .max = IRONLAKE_DP_M_MAX },
615 .m1 = { .min = IRONLAKE_M1_MIN,
616 .max = IRONLAKE_M1_MAX },
617 .m2 = { .min = IRONLAKE_M2_MIN,
618 .max = IRONLAKE_M2_MAX },
619 .p = { .min = IRONLAKE_DP_P_MIN,
620 .max = IRONLAKE_DP_P_MAX },
621 .p1 = { .min = IRONLAKE_DP_P1_MIN,
622 .max = IRONLAKE_DP_P1_MAX},
623 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
624 .p2_slow = IRONLAKE_DP_P2_SLOW,
625 .p2_fast = IRONLAKE_DP_P2_FAST },
626 .find_pll = intel_find_pll_ironlake_dp,
627 };
628
629 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
630 {
631 struct drm_device *dev = crtc->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 const intel_limit_t *limit;
634 int refclk = 120;
635
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
637 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
638 refclk = 100;
639
640 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
641 LVDS_CLKB_POWER_UP) {
642 /* LVDS dual channel */
643 if (refclk == 100)
644 limit = &intel_limits_ironlake_dual_lvds_100m;
645 else
646 limit = &intel_limits_ironlake_dual_lvds;
647 } else {
648 if (refclk == 100)
649 limit = &intel_limits_ironlake_single_lvds_100m;
650 else
651 limit = &intel_limits_ironlake_single_lvds;
652 }
653 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
654 HAS_eDP)
655 limit = &intel_limits_ironlake_display_port;
656 else
657 limit = &intel_limits_ironlake_dac;
658
659 return limit;
660 }
661
662 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
663 {
664 struct drm_device *dev = crtc->dev;
665 struct drm_i915_private *dev_priv = dev->dev_private;
666 const intel_limit_t *limit;
667
668 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
669 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
670 LVDS_CLKB_POWER_UP)
671 /* LVDS with dual channel */
672 limit = &intel_limits_g4x_dual_channel_lvds;
673 else
674 /* LVDS with dual channel */
675 limit = &intel_limits_g4x_single_channel_lvds;
676 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
677 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
678 limit = &intel_limits_g4x_hdmi;
679 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
680 limit = &intel_limits_g4x_sdvo;
681 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
682 limit = &intel_limits_g4x_display_port;
683 } else /* The option is for other outputs */
684 limit = &intel_limits_i9xx_sdvo;
685
686 return limit;
687 }
688
689 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
690 {
691 struct drm_device *dev = crtc->dev;
692 const intel_limit_t *limit;
693
694 if (HAS_PCH_SPLIT(dev))
695 limit = intel_ironlake_limit(crtc);
696 else if (IS_G4X(dev)) {
697 limit = intel_g4x_limit(crtc);
698 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
699 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
700 limit = &intel_limits_i9xx_lvds;
701 else
702 limit = &intel_limits_i9xx_sdvo;
703 } else if (IS_PINEVIEW(dev)) {
704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
705 limit = &intel_limits_pineview_lvds;
706 else
707 limit = &intel_limits_pineview_sdvo;
708 } else {
709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
710 limit = &intel_limits_i8xx_lvds;
711 else
712 limit = &intel_limits_i8xx_dvo;
713 }
714 return limit;
715 }
716
717 /* m1 is reserved as 0 in Pineview, n is a ring counter */
718 static void pineview_clock(int refclk, intel_clock_t *clock)
719 {
720 clock->m = clock->m2 + 2;
721 clock->p = clock->p1 * clock->p2;
722 clock->vco = refclk * clock->m / clock->n;
723 clock->dot = clock->vco / clock->p;
724 }
725
726 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
727 {
728 if (IS_PINEVIEW(dev)) {
729 pineview_clock(refclk, clock);
730 return;
731 }
732 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
733 clock->p = clock->p1 * clock->p2;
734 clock->vco = refclk * clock->m / (clock->n + 2);
735 clock->dot = clock->vco / clock->p;
736 }
737
738 /**
739 * Returns whether any output on the specified pipe is of the specified type
740 */
741 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742 {
743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_connector *l_entry;
746
747 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
748 if (l_entry->encoder &&
749 l_entry->encoder->crtc == crtc) {
750 struct intel_encoder *intel_encoder = to_intel_encoder(l_entry);
751 if (intel_encoder->type == type)
752 return true;
753 }
754 }
755 return false;
756 }
757
758 static struct drm_connector *
759 intel_pipe_get_connector (struct drm_crtc *crtc)
760 {
761 struct drm_device *dev = crtc->dev;
762 struct drm_mode_config *mode_config = &dev->mode_config;
763 struct drm_connector *l_entry, *ret = NULL;
764
765 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
766 if (l_entry->encoder &&
767 l_entry->encoder->crtc == crtc) {
768 ret = l_entry;
769 break;
770 }
771 }
772 return ret;
773 }
774
775 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
776 /**
777 * Returns whether the given set of divisors are valid for a given refclk with
778 * the given connectors.
779 */
780
781 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
782 {
783 const intel_limit_t *limit = intel_limit (crtc);
784 struct drm_device *dev = crtc->dev;
785
786 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
787 INTELPllInvalid ("p1 out of range\n");
788 if (clock->p < limit->p.min || limit->p.max < clock->p)
789 INTELPllInvalid ("p out of range\n");
790 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
791 INTELPllInvalid ("m2 out of range\n");
792 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
793 INTELPllInvalid ("m1 out of range\n");
794 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
795 INTELPllInvalid ("m1 <= m2\n");
796 if (clock->m < limit->m.min || limit->m.max < clock->m)
797 INTELPllInvalid ("m out of range\n");
798 if (clock->n < limit->n.min || limit->n.max < clock->n)
799 INTELPllInvalid ("n out of range\n");
800 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
801 INTELPllInvalid ("vco out of range\n");
802 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
803 * connector, etc., rather than just a single range.
804 */
805 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
806 INTELPllInvalid ("dot out of range\n");
807
808 return true;
809 }
810
811 static bool
812 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
813 int target, int refclk, intel_clock_t *best_clock)
814
815 {
816 struct drm_device *dev = crtc->dev;
817 struct drm_i915_private *dev_priv = dev->dev_private;
818 intel_clock_t clock;
819 int err = target;
820
821 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
822 (I915_READ(LVDS)) != 0) {
823 /*
824 * For LVDS, if the panel is on, just rely on its current
825 * settings for dual-channel. We haven't figured out how to
826 * reliably set up different single/dual channel state, if we
827 * even can.
828 */
829 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
830 LVDS_CLKB_POWER_UP)
831 clock.p2 = limit->p2.p2_fast;
832 else
833 clock.p2 = limit->p2.p2_slow;
834 } else {
835 if (target < limit->p2.dot_limit)
836 clock.p2 = limit->p2.p2_slow;
837 else
838 clock.p2 = limit->p2.p2_fast;
839 }
840
841 memset (best_clock, 0, sizeof (*best_clock));
842
843 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
844 clock.m1++) {
845 for (clock.m2 = limit->m2.min;
846 clock.m2 <= limit->m2.max; clock.m2++) {
847 /* m1 is always 0 in Pineview */
848 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
849 break;
850 for (clock.n = limit->n.min;
851 clock.n <= limit->n.max; clock.n++) {
852 for (clock.p1 = limit->p1.min;
853 clock.p1 <= limit->p1.max; clock.p1++) {
854 int this_err;
855
856 intel_clock(dev, refclk, &clock);
857
858 if (!intel_PLL_is_valid(crtc, &clock))
859 continue;
860
861 this_err = abs(clock.dot - target);
862 if (this_err < err) {
863 *best_clock = clock;
864 err = this_err;
865 }
866 }
867 }
868 }
869 }
870
871 return (err != target);
872 }
873
874 static bool
875 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
876 int target, int refclk, intel_clock_t *best_clock)
877 {
878 struct drm_device *dev = crtc->dev;
879 struct drm_i915_private *dev_priv = dev->dev_private;
880 intel_clock_t clock;
881 int max_n;
882 bool found;
883 /* approximately equals target * 0.00488 */
884 int err_most = (target >> 8) + (target >> 10);
885 found = false;
886
887 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
888 int lvds_reg;
889
890 if (HAS_PCH_SPLIT(dev))
891 lvds_reg = PCH_LVDS;
892 else
893 lvds_reg = LVDS;
894 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
895 LVDS_CLKB_POWER_UP)
896 clock.p2 = limit->p2.p2_fast;
897 else
898 clock.p2 = limit->p2.p2_slow;
899 } else {
900 if (target < limit->p2.dot_limit)
901 clock.p2 = limit->p2.p2_slow;
902 else
903 clock.p2 = limit->p2.p2_fast;
904 }
905
906 memset(best_clock, 0, sizeof(*best_clock));
907 max_n = limit->n.max;
908 /* based on hardware requriment prefer smaller n to precision */
909 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
910 /* based on hardware requirment prefere larger m1,m2 */
911 for (clock.m1 = limit->m1.max;
912 clock.m1 >= limit->m1.min; clock.m1--) {
913 for (clock.m2 = limit->m2.max;
914 clock.m2 >= limit->m2.min; clock.m2--) {
915 for (clock.p1 = limit->p1.max;
916 clock.p1 >= limit->p1.min; clock.p1--) {
917 int this_err;
918
919 intel_clock(dev, refclk, &clock);
920 if (!intel_PLL_is_valid(crtc, &clock))
921 continue;
922 this_err = abs(clock.dot - target) ;
923 if (this_err < err_most) {
924 *best_clock = clock;
925 err_most = this_err;
926 max_n = clock.n;
927 found = true;
928 }
929 }
930 }
931 }
932 }
933 return found;
934 }
935
936 static bool
937 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
938 int target, int refclk, intel_clock_t *best_clock)
939 {
940 struct drm_device *dev = crtc->dev;
941 intel_clock_t clock;
942
943 /* return directly when it is eDP */
944 if (HAS_eDP)
945 return true;
946
947 if (target < 200000) {
948 clock.n = 1;
949 clock.p1 = 2;
950 clock.p2 = 10;
951 clock.m1 = 12;
952 clock.m2 = 9;
953 } else {
954 clock.n = 2;
955 clock.p1 = 1;
956 clock.p2 = 10;
957 clock.m1 = 14;
958 clock.m2 = 8;
959 }
960 intel_clock(dev, refclk, &clock);
961 memcpy(best_clock, &clock, sizeof(intel_clock_t));
962 return true;
963 }
964
965 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
966 static bool
967 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
968 int target, int refclk, intel_clock_t *best_clock)
969 {
970 intel_clock_t clock;
971 if (target < 200000) {
972 clock.p1 = 2;
973 clock.p2 = 10;
974 clock.n = 2;
975 clock.m1 = 23;
976 clock.m2 = 8;
977 } else {
978 clock.p1 = 1;
979 clock.p2 = 10;
980 clock.n = 1;
981 clock.m1 = 14;
982 clock.m2 = 2;
983 }
984 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
985 clock.p = (clock.p1 * clock.p2);
986 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
987 clock.vco = 0;
988 memcpy(best_clock, &clock, sizeof(intel_clock_t));
989 return true;
990 }
991
992 void
993 intel_wait_for_vblank(struct drm_device *dev)
994 {
995 /* Wait for 20ms, i.e. one cycle at 50hz. */
996 msleep(20);
997 }
998
999 /* Parameters have changed, update FBC info */
1000 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1001 {
1002 struct drm_device *dev = crtc->dev;
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 struct drm_framebuffer *fb = crtc->fb;
1005 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1006 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008 int plane, i;
1009 u32 fbc_ctl, fbc_ctl2;
1010
1011 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1012
1013 if (fb->pitch < dev_priv->cfb_pitch)
1014 dev_priv->cfb_pitch = fb->pitch;
1015
1016 /* FBC_CTL wants 64B units */
1017 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1018 dev_priv->cfb_fence = obj_priv->fence_reg;
1019 dev_priv->cfb_plane = intel_crtc->plane;
1020 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1021
1022 /* Clear old tags */
1023 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1024 I915_WRITE(FBC_TAG + (i * 4), 0);
1025
1026 /* Set it up... */
1027 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1028 if (obj_priv->tiling_mode != I915_TILING_NONE)
1029 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1030 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1031 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1032
1033 /* enable it... */
1034 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1035 if (IS_I945GM(dev))
1036 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1037 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1038 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1039 if (obj_priv->tiling_mode != I915_TILING_NONE)
1040 fbc_ctl |= dev_priv->cfb_fence;
1041 I915_WRITE(FBC_CONTROL, fbc_ctl);
1042
1043 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1044 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1045 }
1046
1047 void i8xx_disable_fbc(struct drm_device *dev)
1048 {
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 u32 fbc_ctl;
1051
1052 if (!I915_HAS_FBC(dev))
1053 return;
1054
1055 /* Disable compression */
1056 fbc_ctl = I915_READ(FBC_CONTROL);
1057 fbc_ctl &= ~FBC_CTL_EN;
1058 I915_WRITE(FBC_CONTROL, fbc_ctl);
1059
1060 /* Wait for compressing bit to clear */
1061 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1062 ; /* nothing */
1063
1064 intel_wait_for_vblank(dev);
1065
1066 DRM_DEBUG_KMS("disabled FBC\n");
1067 }
1068
1069 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1070 {
1071 struct drm_device *dev = crtc->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073
1074 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1075 }
1076
1077 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1078 {
1079 struct drm_device *dev = crtc->dev;
1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 struct drm_framebuffer *fb = crtc->fb;
1082 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1083 struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1085 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1086 DPFC_CTL_PLANEB);
1087 unsigned long stall_watermark = 200;
1088 u32 dpfc_ctl;
1089
1090 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1091 dev_priv->cfb_fence = obj_priv->fence_reg;
1092 dev_priv->cfb_plane = intel_crtc->plane;
1093
1094 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1095 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1096 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1097 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1098 } else {
1099 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1100 }
1101
1102 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1103 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1104 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1105 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1106 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1107
1108 /* enable it... */
1109 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1110
1111 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1112 }
1113
1114 void g4x_disable_fbc(struct drm_device *dev)
1115 {
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1117 u32 dpfc_ctl;
1118
1119 /* Disable compression */
1120 dpfc_ctl = I915_READ(DPFC_CONTROL);
1121 dpfc_ctl &= ~DPFC_CTL_EN;
1122 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1123 intel_wait_for_vblank(dev);
1124
1125 DRM_DEBUG_KMS("disabled FBC\n");
1126 }
1127
1128 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1129 {
1130 struct drm_device *dev = crtc->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1132
1133 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1134 }
1135
1136 /**
1137 * intel_update_fbc - enable/disable FBC as needed
1138 * @crtc: CRTC to point the compressor at
1139 * @mode: mode in use
1140 *
1141 * Set up the framebuffer compression hardware at mode set time. We
1142 * enable it if possible:
1143 * - plane A only (on pre-965)
1144 * - no pixel mulitply/line duplication
1145 * - no alpha buffer discard
1146 * - no dual wide
1147 * - framebuffer <= 2048 in width, 1536 in height
1148 *
1149 * We can't assume that any compression will take place (worst case),
1150 * so the compressed buffer has to be the same size as the uncompressed
1151 * one. It also must reside (along with the line length buffer) in
1152 * stolen memory.
1153 *
1154 * We need to enable/disable FBC on a global basis.
1155 */
1156 static void intel_update_fbc(struct drm_crtc *crtc,
1157 struct drm_display_mode *mode)
1158 {
1159 struct drm_device *dev = crtc->dev;
1160 struct drm_i915_private *dev_priv = dev->dev_private;
1161 struct drm_framebuffer *fb = crtc->fb;
1162 struct intel_framebuffer *intel_fb;
1163 struct drm_i915_gem_object *obj_priv;
1164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1165 int plane = intel_crtc->plane;
1166
1167 if (!i915_powersave)
1168 return;
1169
1170 if (!dev_priv->display.fbc_enabled ||
1171 !dev_priv->display.enable_fbc ||
1172 !dev_priv->display.disable_fbc)
1173 return;
1174
1175 if (!crtc->fb)
1176 return;
1177
1178 intel_fb = to_intel_framebuffer(fb);
1179 obj_priv = to_intel_bo(intel_fb->obj);
1180
1181 /*
1182 * If FBC is already on, we just have to verify that we can
1183 * keep it that way...
1184 * Need to disable if:
1185 * - changing FBC params (stride, fence, mode)
1186 * - new fb is too large to fit in compressed buffer
1187 * - going to an unsupported config (interlace, pixel multiply, etc.)
1188 */
1189 if (intel_fb->obj->size > dev_priv->cfb_size) {
1190 DRM_DEBUG_KMS("framebuffer too large, disabling "
1191 "compression\n");
1192 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1193 goto out_disable;
1194 }
1195 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1196 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1197 DRM_DEBUG_KMS("mode incompatible with compression, "
1198 "disabling\n");
1199 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1200 goto out_disable;
1201 }
1202 if ((mode->hdisplay > 2048) ||
1203 (mode->vdisplay > 1536)) {
1204 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1205 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1206 goto out_disable;
1207 }
1208 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1209 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1210 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1211 goto out_disable;
1212 }
1213 if (obj_priv->tiling_mode != I915_TILING_X) {
1214 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1215 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1216 goto out_disable;
1217 }
1218
1219 if (dev_priv->display.fbc_enabled(crtc)) {
1220 /* We can re-enable it in this case, but need to update pitch */
1221 if (fb->pitch > dev_priv->cfb_pitch)
1222 dev_priv->display.disable_fbc(dev);
1223 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1224 dev_priv->display.disable_fbc(dev);
1225 if (plane != dev_priv->cfb_plane)
1226 dev_priv->display.disable_fbc(dev);
1227 }
1228
1229 if (!dev_priv->display.fbc_enabled(crtc)) {
1230 /* Now try to turn it back on if possible */
1231 dev_priv->display.enable_fbc(crtc, 500);
1232 }
1233
1234 return;
1235
1236 out_disable:
1237 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1238 /* Multiple disables should be harmless */
1239 if (dev_priv->display.fbc_enabled(crtc))
1240 dev_priv->display.disable_fbc(dev);
1241 }
1242
1243 static int
1244 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1245 {
1246 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1247 u32 alignment;
1248 int ret;
1249
1250 switch (obj_priv->tiling_mode) {
1251 case I915_TILING_NONE:
1252 alignment = 64 * 1024;
1253 break;
1254 case I915_TILING_X:
1255 /* pin() will align the object as required by fence */
1256 alignment = 0;
1257 break;
1258 case I915_TILING_Y:
1259 /* FIXME: Is this true? */
1260 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1261 return -EINVAL;
1262 default:
1263 BUG();
1264 }
1265
1266 ret = i915_gem_object_pin(obj, alignment);
1267 if (ret != 0)
1268 return ret;
1269
1270 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1271 * fence, whereas 965+ only requires a fence if using
1272 * framebuffer compression. For simplicity, we always install
1273 * a fence as the cost is not that onerous.
1274 */
1275 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1276 obj_priv->tiling_mode != I915_TILING_NONE) {
1277 ret = i915_gem_object_get_fence_reg(obj);
1278 if (ret != 0) {
1279 i915_gem_object_unpin(obj);
1280 return ret;
1281 }
1282 }
1283
1284 return 0;
1285 }
1286
1287 static int
1288 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1289 struct drm_framebuffer *old_fb)
1290 {
1291 struct drm_device *dev = crtc->dev;
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293 struct drm_i915_master_private *master_priv;
1294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1295 struct intel_framebuffer *intel_fb;
1296 struct drm_i915_gem_object *obj_priv;
1297 struct drm_gem_object *obj;
1298 int pipe = intel_crtc->pipe;
1299 int plane = intel_crtc->plane;
1300 unsigned long Start, Offset;
1301 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1302 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1303 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1304 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1305 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1306 u32 dspcntr;
1307 int ret;
1308
1309 /* no fb bound */
1310 if (!crtc->fb) {
1311 DRM_DEBUG_KMS("No FB bound\n");
1312 return 0;
1313 }
1314
1315 switch (plane) {
1316 case 0:
1317 case 1:
1318 break;
1319 default:
1320 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1321 return -EINVAL;
1322 }
1323
1324 intel_fb = to_intel_framebuffer(crtc->fb);
1325 obj = intel_fb->obj;
1326 obj_priv = to_intel_bo(obj);
1327
1328 mutex_lock(&dev->struct_mutex);
1329 ret = intel_pin_and_fence_fb_obj(dev, obj);
1330 if (ret != 0) {
1331 mutex_unlock(&dev->struct_mutex);
1332 return ret;
1333 }
1334
1335 ret = i915_gem_object_set_to_display_plane(obj);
1336 if (ret != 0) {
1337 i915_gem_object_unpin(obj);
1338 mutex_unlock(&dev->struct_mutex);
1339 return ret;
1340 }
1341
1342 dspcntr = I915_READ(dspcntr_reg);
1343 /* Mask out pixel format bits in case we change it */
1344 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1345 switch (crtc->fb->bits_per_pixel) {
1346 case 8:
1347 dspcntr |= DISPPLANE_8BPP;
1348 break;
1349 case 16:
1350 if (crtc->fb->depth == 15)
1351 dspcntr |= DISPPLANE_15_16BPP;
1352 else
1353 dspcntr |= DISPPLANE_16BPP;
1354 break;
1355 case 24:
1356 case 32:
1357 if (crtc->fb->depth == 30)
1358 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1359 else
1360 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1361 break;
1362 default:
1363 DRM_ERROR("Unknown color depth\n");
1364 i915_gem_object_unpin(obj);
1365 mutex_unlock(&dev->struct_mutex);
1366 return -EINVAL;
1367 }
1368 if (IS_I965G(dev)) {
1369 if (obj_priv->tiling_mode != I915_TILING_NONE)
1370 dspcntr |= DISPPLANE_TILED;
1371 else
1372 dspcntr &= ~DISPPLANE_TILED;
1373 }
1374
1375 if (HAS_PCH_SPLIT(dev))
1376 /* must disable */
1377 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1378
1379 I915_WRITE(dspcntr_reg, dspcntr);
1380
1381 Start = obj_priv->gtt_offset;
1382 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1383
1384 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1385 I915_WRITE(dspstride, crtc->fb->pitch);
1386 if (IS_I965G(dev)) {
1387 I915_WRITE(dspbase, Offset);
1388 I915_READ(dspbase);
1389 I915_WRITE(dspsurf, Start);
1390 I915_READ(dspsurf);
1391 I915_WRITE(dsptileoff, (y << 16) | x);
1392 } else {
1393 I915_WRITE(dspbase, Start + Offset);
1394 I915_READ(dspbase);
1395 }
1396
1397 if ((IS_I965G(dev) || plane == 0))
1398 intel_update_fbc(crtc, &crtc->mode);
1399
1400 intel_wait_for_vblank(dev);
1401
1402 if (old_fb) {
1403 intel_fb = to_intel_framebuffer(old_fb);
1404 obj_priv = to_intel_bo(intel_fb->obj);
1405 i915_gem_object_unpin(intel_fb->obj);
1406 }
1407 intel_increase_pllclock(crtc, true);
1408
1409 mutex_unlock(&dev->struct_mutex);
1410
1411 if (!dev->primary->master)
1412 return 0;
1413
1414 master_priv = dev->primary->master->driver_priv;
1415 if (!master_priv->sarea_priv)
1416 return 0;
1417
1418 if (pipe) {
1419 master_priv->sarea_priv->pipeB_x = x;
1420 master_priv->sarea_priv->pipeB_y = y;
1421 } else {
1422 master_priv->sarea_priv->pipeA_x = x;
1423 master_priv->sarea_priv->pipeA_y = y;
1424 }
1425
1426 return 0;
1427 }
1428
1429 /* Disable the VGA plane that we never use */
1430 static void i915_disable_vga (struct drm_device *dev)
1431 {
1432 struct drm_i915_private *dev_priv = dev->dev_private;
1433 u8 sr1;
1434 u32 vga_reg;
1435
1436 if (HAS_PCH_SPLIT(dev))
1437 vga_reg = CPU_VGACNTRL;
1438 else
1439 vga_reg = VGACNTRL;
1440
1441 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1442 return;
1443
1444 I915_WRITE8(VGA_SR_INDEX, 1);
1445 sr1 = I915_READ8(VGA_SR_DATA);
1446 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1447 udelay(100);
1448
1449 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1450 }
1451
1452 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1453 {
1454 struct drm_device *dev = crtc->dev;
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1456 u32 dpa_ctl;
1457
1458 DRM_DEBUG_KMS("\n");
1459 dpa_ctl = I915_READ(DP_A);
1460 dpa_ctl &= ~DP_PLL_ENABLE;
1461 I915_WRITE(DP_A, dpa_ctl);
1462 }
1463
1464 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1465 {
1466 struct drm_device *dev = crtc->dev;
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1468 u32 dpa_ctl;
1469
1470 dpa_ctl = I915_READ(DP_A);
1471 dpa_ctl |= DP_PLL_ENABLE;
1472 I915_WRITE(DP_A, dpa_ctl);
1473 udelay(200);
1474 }
1475
1476
1477 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1478 {
1479 struct drm_device *dev = crtc->dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 dpa_ctl;
1482
1483 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1484 dpa_ctl = I915_READ(DP_A);
1485 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1486
1487 if (clock < 200000) {
1488 u32 temp;
1489 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1490 /* workaround for 160Mhz:
1491 1) program 0x4600c bits 15:0 = 0x8124
1492 2) program 0x46010 bit 0 = 1
1493 3) program 0x46034 bit 24 = 1
1494 4) program 0x64000 bit 14 = 1
1495 */
1496 temp = I915_READ(0x4600c);
1497 temp &= 0xffff0000;
1498 I915_WRITE(0x4600c, temp | 0x8124);
1499
1500 temp = I915_READ(0x46010);
1501 I915_WRITE(0x46010, temp | 1);
1502
1503 temp = I915_READ(0x46034);
1504 I915_WRITE(0x46034, temp | (1 << 24));
1505 } else {
1506 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1507 }
1508 I915_WRITE(DP_A, dpa_ctl);
1509
1510 udelay(500);
1511 }
1512
1513 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1514 {
1515 struct drm_device *dev = crtc->dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1518 int pipe = intel_crtc->pipe;
1519 int plane = intel_crtc->plane;
1520 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1521 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1522 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1523 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1524 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1525 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1526 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1527 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1528 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1529 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1530 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1531 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1532 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1533 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1534 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1535 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1536 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1537 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1538 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1539 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1540 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1541 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1542 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1543 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1544 u32 temp;
1545 int tries = 5, j, n;
1546 u32 pipe_bpc;
1547
1548 temp = I915_READ(pipeconf_reg);
1549 pipe_bpc = temp & PIPE_BPC_MASK;
1550
1551 /* XXX: When our outputs are all unaware of DPMS modes other than off
1552 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1553 */
1554 switch (mode) {
1555 case DRM_MODE_DPMS_ON:
1556 case DRM_MODE_DPMS_STANDBY:
1557 case DRM_MODE_DPMS_SUSPEND:
1558 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1559
1560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1561 temp = I915_READ(PCH_LVDS);
1562 if ((temp & LVDS_PORT_EN) == 0) {
1563 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1564 POSTING_READ(PCH_LVDS);
1565 }
1566 }
1567
1568 if (HAS_eDP) {
1569 /* enable eDP PLL */
1570 ironlake_enable_pll_edp(crtc);
1571 } else {
1572 /* enable PCH DPLL */
1573 temp = I915_READ(pch_dpll_reg);
1574 if ((temp & DPLL_VCO_ENABLE) == 0) {
1575 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1576 I915_READ(pch_dpll_reg);
1577 }
1578
1579 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1580 temp = I915_READ(fdi_rx_reg);
1581 /*
1582 * make the BPC in FDI Rx be consistent with that in
1583 * pipeconf reg.
1584 */
1585 temp &= ~(0x7 << 16);
1586 temp |= (pipe_bpc << 11);
1587 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1588 FDI_SEL_PCDCLK |
1589 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1590 I915_READ(fdi_rx_reg);
1591 udelay(200);
1592
1593 /* Enable CPU FDI TX PLL, always on for Ironlake */
1594 temp = I915_READ(fdi_tx_reg);
1595 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1596 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1597 I915_READ(fdi_tx_reg);
1598 udelay(100);
1599 }
1600 }
1601
1602 /* Enable panel fitting for LVDS */
1603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1604 temp = I915_READ(pf_ctl_reg);
1605 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1606
1607 /* currently full aspect */
1608 I915_WRITE(pf_win_pos, 0);
1609
1610 I915_WRITE(pf_win_size,
1611 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1612 (dev_priv->panel_fixed_mode->vdisplay));
1613 }
1614
1615 /* Enable CPU pipe */
1616 temp = I915_READ(pipeconf_reg);
1617 if ((temp & PIPEACONF_ENABLE) == 0) {
1618 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1619 I915_READ(pipeconf_reg);
1620 udelay(100);
1621 }
1622
1623 /* configure and enable CPU plane */
1624 temp = I915_READ(dspcntr_reg);
1625 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1626 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1627 /* Flush the plane changes */
1628 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1629 }
1630
1631 if (!HAS_eDP) {
1632 /* enable CPU FDI TX and PCH FDI RX */
1633 temp = I915_READ(fdi_tx_reg);
1634 temp |= FDI_TX_ENABLE;
1635 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1636 temp &= ~FDI_LINK_TRAIN_NONE;
1637 temp |= FDI_LINK_TRAIN_PATTERN_1;
1638 I915_WRITE(fdi_tx_reg, temp);
1639 I915_READ(fdi_tx_reg);
1640
1641 temp = I915_READ(fdi_rx_reg);
1642 temp &= ~FDI_LINK_TRAIN_NONE;
1643 temp |= FDI_LINK_TRAIN_PATTERN_1;
1644 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645 I915_READ(fdi_rx_reg);
1646
1647 udelay(150);
1648
1649 /* Train FDI. */
1650 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1651 for train result */
1652 temp = I915_READ(fdi_rx_imr_reg);
1653 temp &= ~FDI_RX_SYMBOL_LOCK;
1654 temp &= ~FDI_RX_BIT_LOCK;
1655 I915_WRITE(fdi_rx_imr_reg, temp);
1656 I915_READ(fdi_rx_imr_reg);
1657 udelay(150);
1658
1659 temp = I915_READ(fdi_rx_iir_reg);
1660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1661
1662 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1663 for (j = 0; j < tries; j++) {
1664 temp = I915_READ(fdi_rx_iir_reg);
1665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1666 temp);
1667 if (temp & FDI_RX_BIT_LOCK)
1668 break;
1669 udelay(200);
1670 }
1671 if (j != tries)
1672 I915_WRITE(fdi_rx_iir_reg,
1673 temp | FDI_RX_BIT_LOCK);
1674 else
1675 DRM_DEBUG_KMS("train 1 fail\n");
1676 } else {
1677 I915_WRITE(fdi_rx_iir_reg,
1678 temp | FDI_RX_BIT_LOCK);
1679 DRM_DEBUG_KMS("train 1 ok 2!\n");
1680 }
1681 temp = I915_READ(fdi_tx_reg);
1682 temp &= ~FDI_LINK_TRAIN_NONE;
1683 temp |= FDI_LINK_TRAIN_PATTERN_2;
1684 I915_WRITE(fdi_tx_reg, temp);
1685
1686 temp = I915_READ(fdi_rx_reg);
1687 temp &= ~FDI_LINK_TRAIN_NONE;
1688 temp |= FDI_LINK_TRAIN_PATTERN_2;
1689 I915_WRITE(fdi_rx_reg, temp);
1690
1691 udelay(150);
1692
1693 temp = I915_READ(fdi_rx_iir_reg);
1694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1695
1696 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1697 for (j = 0; j < tries; j++) {
1698 temp = I915_READ(fdi_rx_iir_reg);
1699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1700 temp);
1701 if (temp & FDI_RX_SYMBOL_LOCK)
1702 break;
1703 udelay(200);
1704 }
1705 if (j != tries) {
1706 I915_WRITE(fdi_rx_iir_reg,
1707 temp | FDI_RX_SYMBOL_LOCK);
1708 DRM_DEBUG_KMS("train 2 ok 1!\n");
1709 } else
1710 DRM_DEBUG_KMS("train 2 fail\n");
1711 } else {
1712 I915_WRITE(fdi_rx_iir_reg,
1713 temp | FDI_RX_SYMBOL_LOCK);
1714 DRM_DEBUG_KMS("train 2 ok 2!\n");
1715 }
1716 DRM_DEBUG_KMS("train done\n");
1717
1718 /* set transcoder timing */
1719 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1720 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1721 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1722
1723 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1724 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1725 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1726
1727 /* enable PCH transcoder */
1728 temp = I915_READ(transconf_reg);
1729 /*
1730 * make the BPC in transcoder be consistent with
1731 * that in pipeconf reg.
1732 */
1733 temp &= ~PIPE_BPC_MASK;
1734 temp |= pipe_bpc;
1735 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1736 I915_READ(transconf_reg);
1737
1738 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1739 ;
1740
1741 /* enable normal */
1742
1743 temp = I915_READ(fdi_tx_reg);
1744 temp &= ~FDI_LINK_TRAIN_NONE;
1745 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1746 FDI_TX_ENHANCE_FRAME_ENABLE);
1747 I915_READ(fdi_tx_reg);
1748
1749 temp = I915_READ(fdi_rx_reg);
1750 temp &= ~FDI_LINK_TRAIN_NONE;
1751 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1752 FDI_RX_ENHANCE_FRAME_ENABLE);
1753 I915_READ(fdi_rx_reg);
1754
1755 /* wait one idle pattern time */
1756 udelay(100);
1757
1758 }
1759
1760 intel_crtc_load_lut(crtc);
1761
1762 break;
1763 case DRM_MODE_DPMS_OFF:
1764 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1765
1766 drm_vblank_off(dev, pipe);
1767 /* Disable display plane */
1768 temp = I915_READ(dspcntr_reg);
1769 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1770 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1771 /* Flush the plane changes */
1772 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1773 I915_READ(dspbase_reg);
1774 }
1775
1776 i915_disable_vga(dev);
1777
1778 /* disable cpu pipe, disable after all planes disabled */
1779 temp = I915_READ(pipeconf_reg);
1780 if ((temp & PIPEACONF_ENABLE) != 0) {
1781 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1782 I915_READ(pipeconf_reg);
1783 n = 0;
1784 /* wait for cpu pipe off, pipe state */
1785 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1786 n++;
1787 if (n < 60) {
1788 udelay(500);
1789 continue;
1790 } else {
1791 DRM_DEBUG_KMS("pipe %d off delay\n",
1792 pipe);
1793 break;
1794 }
1795 }
1796 } else
1797 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1798
1799 udelay(100);
1800
1801 /* Disable PF */
1802 temp = I915_READ(pf_ctl_reg);
1803 if ((temp & PF_ENABLE) != 0) {
1804 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1805 I915_READ(pf_ctl_reg);
1806 }
1807 I915_WRITE(pf_win_size, 0);
1808
1809 /* disable CPU FDI tx and PCH FDI rx */
1810 temp = I915_READ(fdi_tx_reg);
1811 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1812 I915_READ(fdi_tx_reg);
1813
1814 temp = I915_READ(fdi_rx_reg);
1815 /* BPC in FDI rx is consistent with that in pipeconf */
1816 temp &= ~(0x07 << 16);
1817 temp |= (pipe_bpc << 11);
1818 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1819 I915_READ(fdi_rx_reg);
1820
1821 udelay(100);
1822
1823 /* still set train pattern 1 */
1824 temp = I915_READ(fdi_tx_reg);
1825 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_1;
1827 I915_WRITE(fdi_tx_reg, temp);
1828
1829 temp = I915_READ(fdi_rx_reg);
1830 temp &= ~FDI_LINK_TRAIN_NONE;
1831 temp |= FDI_LINK_TRAIN_PATTERN_1;
1832 I915_WRITE(fdi_rx_reg, temp);
1833
1834 udelay(100);
1835
1836 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1837 temp = I915_READ(PCH_LVDS);
1838 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1839 I915_READ(PCH_LVDS);
1840 udelay(100);
1841 }
1842
1843 /* disable PCH transcoder */
1844 temp = I915_READ(transconf_reg);
1845 if ((temp & TRANS_ENABLE) != 0) {
1846 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1847 I915_READ(transconf_reg);
1848 n = 0;
1849 /* wait for PCH transcoder off, transcoder state */
1850 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1851 n++;
1852 if (n < 60) {
1853 udelay(500);
1854 continue;
1855 } else {
1856 DRM_DEBUG_KMS("transcoder %d off "
1857 "delay\n", pipe);
1858 break;
1859 }
1860 }
1861 }
1862 temp = I915_READ(transconf_reg);
1863 /* BPC in transcoder is consistent with that in pipeconf */
1864 temp &= ~PIPE_BPC_MASK;
1865 temp |= pipe_bpc;
1866 I915_WRITE(transconf_reg, temp);
1867 I915_READ(transconf_reg);
1868 udelay(100);
1869
1870 /* disable PCH DPLL */
1871 temp = I915_READ(pch_dpll_reg);
1872 if ((temp & DPLL_VCO_ENABLE) != 0) {
1873 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1874 I915_READ(pch_dpll_reg);
1875 }
1876
1877 if (HAS_eDP) {
1878 ironlake_disable_pll_edp(crtc);
1879 }
1880
1881 temp = I915_READ(fdi_rx_reg);
1882 temp &= ~FDI_SEL_PCDCLK;
1883 I915_WRITE(fdi_rx_reg, temp);
1884 I915_READ(fdi_rx_reg);
1885
1886 temp = I915_READ(fdi_rx_reg);
1887 temp &= ~FDI_RX_PLL_ENABLE;
1888 I915_WRITE(fdi_rx_reg, temp);
1889 I915_READ(fdi_rx_reg);
1890
1891 /* Disable CPU FDI TX PLL */
1892 temp = I915_READ(fdi_tx_reg);
1893 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1894 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1895 I915_READ(fdi_tx_reg);
1896 udelay(100);
1897 }
1898
1899 /* Wait for the clocks to turn off. */
1900 udelay(100);
1901 break;
1902 }
1903 }
1904
1905 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1906 {
1907 struct intel_overlay *overlay;
1908 int ret;
1909
1910 if (!enable && intel_crtc->overlay) {
1911 overlay = intel_crtc->overlay;
1912 mutex_lock(&overlay->dev->struct_mutex);
1913 for (;;) {
1914 ret = intel_overlay_switch_off(overlay);
1915 if (ret == 0)
1916 break;
1917
1918 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1919 if (ret != 0) {
1920 /* overlay doesn't react anymore. Usually
1921 * results in a black screen and an unkillable
1922 * X server. */
1923 BUG();
1924 overlay->hw_wedged = HW_WEDGED;
1925 break;
1926 }
1927 }
1928 mutex_unlock(&overlay->dev->struct_mutex);
1929 }
1930 /* Let userspace switch the overlay on again. In most cases userspace
1931 * has to recompute where to put it anyway. */
1932
1933 return;
1934 }
1935
1936 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1937 {
1938 struct drm_device *dev = crtc->dev;
1939 struct drm_i915_private *dev_priv = dev->dev_private;
1940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1941 int pipe = intel_crtc->pipe;
1942 int plane = intel_crtc->plane;
1943 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1944 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1945 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1946 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1947 u32 temp;
1948
1949 /* XXX: When our outputs are all unaware of DPMS modes other than off
1950 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1951 */
1952 switch (mode) {
1953 case DRM_MODE_DPMS_ON:
1954 case DRM_MODE_DPMS_STANDBY:
1955 case DRM_MODE_DPMS_SUSPEND:
1956 intel_update_watermarks(dev);
1957
1958 /* Enable the DPLL */
1959 temp = I915_READ(dpll_reg);
1960 if ((temp & DPLL_VCO_ENABLE) == 0) {
1961 I915_WRITE(dpll_reg, temp);
1962 I915_READ(dpll_reg);
1963 /* Wait for the clocks to stabilize. */
1964 udelay(150);
1965 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1966 I915_READ(dpll_reg);
1967 /* Wait for the clocks to stabilize. */
1968 udelay(150);
1969 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1970 I915_READ(dpll_reg);
1971 /* Wait for the clocks to stabilize. */
1972 udelay(150);
1973 }
1974
1975 /* Enable the pipe */
1976 temp = I915_READ(pipeconf_reg);
1977 if ((temp & PIPEACONF_ENABLE) == 0)
1978 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1979
1980 /* Enable the plane */
1981 temp = I915_READ(dspcntr_reg);
1982 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1983 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1984 /* Flush the plane changes */
1985 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1986 }
1987
1988 intel_crtc_load_lut(crtc);
1989
1990 if ((IS_I965G(dev) || plane == 0))
1991 intel_update_fbc(crtc, &crtc->mode);
1992
1993 /* Give the overlay scaler a chance to enable if it's on this pipe */
1994 intel_crtc_dpms_overlay(intel_crtc, true);
1995 break;
1996 case DRM_MODE_DPMS_OFF:
1997 intel_update_watermarks(dev);
1998
1999 /* Give the overlay scaler a chance to disable if it's on this pipe */
2000 intel_crtc_dpms_overlay(intel_crtc, false);
2001 drm_vblank_off(dev, pipe);
2002
2003 if (dev_priv->cfb_plane == plane &&
2004 dev_priv->display.disable_fbc)
2005 dev_priv->display.disable_fbc(dev);
2006
2007 /* Disable the VGA plane that we never use */
2008 i915_disable_vga(dev);
2009
2010 /* Disable display plane */
2011 temp = I915_READ(dspcntr_reg);
2012 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2013 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2014 /* Flush the plane changes */
2015 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2016 I915_READ(dspbase_reg);
2017 }
2018
2019 if (!IS_I9XX(dev)) {
2020 /* Wait for vblank for the disable to take effect */
2021 intel_wait_for_vblank(dev);
2022 }
2023
2024 /* Next, disable display pipes */
2025 temp = I915_READ(pipeconf_reg);
2026 if ((temp & PIPEACONF_ENABLE) != 0) {
2027 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2028 I915_READ(pipeconf_reg);
2029 }
2030
2031 /* Wait for vblank for the disable to take effect. */
2032 intel_wait_for_vblank(dev);
2033
2034 temp = I915_READ(dpll_reg);
2035 if ((temp & DPLL_VCO_ENABLE) != 0) {
2036 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2037 I915_READ(dpll_reg);
2038 }
2039
2040 /* Wait for the clocks to turn off. */
2041 udelay(150);
2042 break;
2043 }
2044 }
2045
2046 /**
2047 * Sets the power management mode of the pipe and plane.
2048 *
2049 * This code should probably grow support for turning the cursor off and back
2050 * on appropriately at the same time as we're turning the pipe off/on.
2051 */
2052 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2053 {
2054 struct drm_device *dev = crtc->dev;
2055 struct drm_i915_private *dev_priv = dev->dev_private;
2056 struct drm_i915_master_private *master_priv;
2057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2058 int pipe = intel_crtc->pipe;
2059 bool enabled;
2060
2061 dev_priv->display.dpms(crtc, mode);
2062
2063 intel_crtc->dpms_mode = mode;
2064
2065 if (!dev->primary->master)
2066 return;
2067
2068 master_priv = dev->primary->master->driver_priv;
2069 if (!master_priv->sarea_priv)
2070 return;
2071
2072 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2073
2074 switch (pipe) {
2075 case 0:
2076 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2077 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2078 break;
2079 case 1:
2080 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2081 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2082 break;
2083 default:
2084 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2085 break;
2086 }
2087 }
2088
2089 static void intel_crtc_prepare (struct drm_crtc *crtc)
2090 {
2091 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2092 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2093 }
2094
2095 static void intel_crtc_commit (struct drm_crtc *crtc)
2096 {
2097 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2098 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2099 }
2100
2101 void intel_encoder_prepare (struct drm_encoder *encoder)
2102 {
2103 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2104 /* lvds has its own version of prepare see intel_lvds_prepare */
2105 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2106 }
2107
2108 void intel_encoder_commit (struct drm_encoder *encoder)
2109 {
2110 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2111 /* lvds has its own version of commit see intel_lvds_commit */
2112 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2113 }
2114
2115 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2116 struct drm_display_mode *mode,
2117 struct drm_display_mode *adjusted_mode)
2118 {
2119 struct drm_device *dev = crtc->dev;
2120 if (HAS_PCH_SPLIT(dev)) {
2121 /* FDI link clock is fixed at 2.7G */
2122 if (mode->clock * 3 > 27000 * 4)
2123 return MODE_CLOCK_HIGH;
2124 }
2125 return true;
2126 }
2127
2128 static int i945_get_display_clock_speed(struct drm_device *dev)
2129 {
2130 return 400000;
2131 }
2132
2133 static int i915_get_display_clock_speed(struct drm_device *dev)
2134 {
2135 return 333000;
2136 }
2137
2138 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2139 {
2140 return 200000;
2141 }
2142
2143 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2144 {
2145 u16 gcfgc = 0;
2146
2147 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2148
2149 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2150 return 133000;
2151 else {
2152 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2153 case GC_DISPLAY_CLOCK_333_MHZ:
2154 return 333000;
2155 default:
2156 case GC_DISPLAY_CLOCK_190_200_MHZ:
2157 return 190000;
2158 }
2159 }
2160 }
2161
2162 static int i865_get_display_clock_speed(struct drm_device *dev)
2163 {
2164 return 266000;
2165 }
2166
2167 static int i855_get_display_clock_speed(struct drm_device *dev)
2168 {
2169 u16 hpllcc = 0;
2170 /* Assume that the hardware is in the high speed state. This
2171 * should be the default.
2172 */
2173 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2174 case GC_CLOCK_133_200:
2175 case GC_CLOCK_100_200:
2176 return 200000;
2177 case GC_CLOCK_166_250:
2178 return 250000;
2179 case GC_CLOCK_100_133:
2180 return 133000;
2181 }
2182
2183 /* Shouldn't happen */
2184 return 0;
2185 }
2186
2187 static int i830_get_display_clock_speed(struct drm_device *dev)
2188 {
2189 return 133000;
2190 }
2191
2192 /**
2193 * Return the pipe currently connected to the panel fitter,
2194 * or -1 if the panel fitter is not present or not in use
2195 */
2196 int intel_panel_fitter_pipe (struct drm_device *dev)
2197 {
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 u32 pfit_control;
2200
2201 /* i830 doesn't have a panel fitter */
2202 if (IS_I830(dev))
2203 return -1;
2204
2205 pfit_control = I915_READ(PFIT_CONTROL);
2206
2207 /* See if the panel fitter is in use */
2208 if ((pfit_control & PFIT_ENABLE) == 0)
2209 return -1;
2210
2211 /* 965 can place panel fitter on either pipe */
2212 if (IS_I965G(dev))
2213 return (pfit_control >> 29) & 0x3;
2214
2215 /* older chips can only use pipe 1 */
2216 return 1;
2217 }
2218
2219 struct fdi_m_n {
2220 u32 tu;
2221 u32 gmch_m;
2222 u32 gmch_n;
2223 u32 link_m;
2224 u32 link_n;
2225 };
2226
2227 static void
2228 fdi_reduce_ratio(u32 *num, u32 *den)
2229 {
2230 while (*num > 0xffffff || *den > 0xffffff) {
2231 *num >>= 1;
2232 *den >>= 1;
2233 }
2234 }
2235
2236 #define DATA_N 0x800000
2237 #define LINK_N 0x80000
2238
2239 static void
2240 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2241 int link_clock, struct fdi_m_n *m_n)
2242 {
2243 u64 temp;
2244
2245 m_n->tu = 64; /* default size */
2246
2247 temp = (u64) DATA_N * pixel_clock;
2248 temp = div_u64(temp, link_clock);
2249 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2250 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2251 m_n->gmch_n = DATA_N;
2252 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2253
2254 temp = (u64) LINK_N * pixel_clock;
2255 m_n->link_m = div_u64(temp, link_clock);
2256 m_n->link_n = LINK_N;
2257 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2258 }
2259
2260
2261 struct intel_watermark_params {
2262 unsigned long fifo_size;
2263 unsigned long max_wm;
2264 unsigned long default_wm;
2265 unsigned long guard_size;
2266 unsigned long cacheline_size;
2267 };
2268
2269 /* Pineview has different values for various configs */
2270 static struct intel_watermark_params pineview_display_wm = {
2271 PINEVIEW_DISPLAY_FIFO,
2272 PINEVIEW_MAX_WM,
2273 PINEVIEW_DFT_WM,
2274 PINEVIEW_GUARD_WM,
2275 PINEVIEW_FIFO_LINE_SIZE
2276 };
2277 static struct intel_watermark_params pineview_display_hplloff_wm = {
2278 PINEVIEW_DISPLAY_FIFO,
2279 PINEVIEW_MAX_WM,
2280 PINEVIEW_DFT_HPLLOFF_WM,
2281 PINEVIEW_GUARD_WM,
2282 PINEVIEW_FIFO_LINE_SIZE
2283 };
2284 static struct intel_watermark_params pineview_cursor_wm = {
2285 PINEVIEW_CURSOR_FIFO,
2286 PINEVIEW_CURSOR_MAX_WM,
2287 PINEVIEW_CURSOR_DFT_WM,
2288 PINEVIEW_CURSOR_GUARD_WM,
2289 PINEVIEW_FIFO_LINE_SIZE,
2290 };
2291 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2292 PINEVIEW_CURSOR_FIFO,
2293 PINEVIEW_CURSOR_MAX_WM,
2294 PINEVIEW_CURSOR_DFT_WM,
2295 PINEVIEW_CURSOR_GUARD_WM,
2296 PINEVIEW_FIFO_LINE_SIZE
2297 };
2298 static struct intel_watermark_params g4x_wm_info = {
2299 G4X_FIFO_SIZE,
2300 G4X_MAX_WM,
2301 G4X_MAX_WM,
2302 2,
2303 G4X_FIFO_LINE_SIZE,
2304 };
2305 static struct intel_watermark_params i945_wm_info = {
2306 I945_FIFO_SIZE,
2307 I915_MAX_WM,
2308 1,
2309 2,
2310 I915_FIFO_LINE_SIZE
2311 };
2312 static struct intel_watermark_params i915_wm_info = {
2313 I915_FIFO_SIZE,
2314 I915_MAX_WM,
2315 1,
2316 2,
2317 I915_FIFO_LINE_SIZE
2318 };
2319 static struct intel_watermark_params i855_wm_info = {
2320 I855GM_FIFO_SIZE,
2321 I915_MAX_WM,
2322 1,
2323 2,
2324 I830_FIFO_LINE_SIZE
2325 };
2326 static struct intel_watermark_params i830_wm_info = {
2327 I830_FIFO_SIZE,
2328 I915_MAX_WM,
2329 1,
2330 2,
2331 I830_FIFO_LINE_SIZE
2332 };
2333
2334 /**
2335 * intel_calculate_wm - calculate watermark level
2336 * @clock_in_khz: pixel clock
2337 * @wm: chip FIFO params
2338 * @pixel_size: display pixel size
2339 * @latency_ns: memory latency for the platform
2340 *
2341 * Calculate the watermark level (the level at which the display plane will
2342 * start fetching from memory again). Each chip has a different display
2343 * FIFO size and allocation, so the caller needs to figure that out and pass
2344 * in the correct intel_watermark_params structure.
2345 *
2346 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2347 * on the pixel size. When it reaches the watermark level, it'll start
2348 * fetching FIFO line sized based chunks from memory until the FIFO fills
2349 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2350 * will occur, and a display engine hang could result.
2351 */
2352 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2353 struct intel_watermark_params *wm,
2354 int pixel_size,
2355 unsigned long latency_ns)
2356 {
2357 long entries_required, wm_size;
2358
2359 /*
2360 * Note: we need to make sure we don't overflow for various clock &
2361 * latency values.
2362 * clocks go from a few thousand to several hundred thousand.
2363 * latency is usually a few thousand
2364 */
2365 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2366 1000;
2367 entries_required /= wm->cacheline_size;
2368
2369 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2370
2371 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2372
2373 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2374
2375 /* Don't promote wm_size to unsigned... */
2376 if (wm_size > (long)wm->max_wm)
2377 wm_size = wm->max_wm;
2378 if (wm_size <= 0)
2379 wm_size = wm->default_wm;
2380 return wm_size;
2381 }
2382
2383 struct cxsr_latency {
2384 int is_desktop;
2385 unsigned long fsb_freq;
2386 unsigned long mem_freq;
2387 unsigned long display_sr;
2388 unsigned long display_hpll_disable;
2389 unsigned long cursor_sr;
2390 unsigned long cursor_hpll_disable;
2391 };
2392
2393 static struct cxsr_latency cxsr_latency_table[] = {
2394 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2395 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2396 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2397
2398 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2399 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2400 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2401
2402 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2403 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2404 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2405
2406 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2407 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2408 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2409
2410 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2411 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2412 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2413
2414 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2415 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2416 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2417 };
2418
2419 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2420 int mem)
2421 {
2422 int i;
2423 struct cxsr_latency *latency;
2424
2425 if (fsb == 0 || mem == 0)
2426 return NULL;
2427
2428 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2429 latency = &cxsr_latency_table[i];
2430 if (is_desktop == latency->is_desktop &&
2431 fsb == latency->fsb_freq && mem == latency->mem_freq)
2432 return latency;
2433 }
2434
2435 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2436
2437 return NULL;
2438 }
2439
2440 static void pineview_disable_cxsr(struct drm_device *dev)
2441 {
2442 struct drm_i915_private *dev_priv = dev->dev_private;
2443 u32 reg;
2444
2445 /* deactivate cxsr */
2446 reg = I915_READ(DSPFW3);
2447 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2448 I915_WRITE(DSPFW3, reg);
2449 DRM_INFO("Big FIFO is disabled\n");
2450 }
2451
2452 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2453 int pixel_size)
2454 {
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 u32 reg;
2457 unsigned long wm;
2458 struct cxsr_latency *latency;
2459
2460 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2461 dev_priv->mem_freq);
2462 if (!latency) {
2463 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2464 pineview_disable_cxsr(dev);
2465 return;
2466 }
2467
2468 /* Display SR */
2469 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2470 latency->display_sr);
2471 reg = I915_READ(DSPFW1);
2472 reg &= 0x7fffff;
2473 reg |= wm << 23;
2474 I915_WRITE(DSPFW1, reg);
2475 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2476
2477 /* cursor SR */
2478 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2479 latency->cursor_sr);
2480 reg = I915_READ(DSPFW3);
2481 reg &= ~(0x3f << 24);
2482 reg |= (wm & 0x3f) << 24;
2483 I915_WRITE(DSPFW3, reg);
2484
2485 /* Display HPLL off SR */
2486 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2487 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2488 reg = I915_READ(DSPFW3);
2489 reg &= 0xfffffe00;
2490 reg |= wm & 0x1ff;
2491 I915_WRITE(DSPFW3, reg);
2492
2493 /* cursor HPLL off SR */
2494 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2495 latency->cursor_hpll_disable);
2496 reg = I915_READ(DSPFW3);
2497 reg &= ~(0x3f << 16);
2498 reg |= (wm & 0x3f) << 16;
2499 I915_WRITE(DSPFW3, reg);
2500 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2501
2502 /* activate cxsr */
2503 reg = I915_READ(DSPFW3);
2504 reg |= PINEVIEW_SELF_REFRESH_EN;
2505 I915_WRITE(DSPFW3, reg);
2506
2507 DRM_INFO("Big FIFO is enabled\n");
2508
2509 return;
2510 }
2511
2512 /*
2513 * Latency for FIFO fetches is dependent on several factors:
2514 * - memory configuration (speed, channels)
2515 * - chipset
2516 * - current MCH state
2517 * It can be fairly high in some situations, so here we assume a fairly
2518 * pessimal value. It's a tradeoff between extra memory fetches (if we
2519 * set this value too high, the FIFO will fetch frequently to stay full)
2520 * and power consumption (set it too low to save power and we might see
2521 * FIFO underruns and display "flicker").
2522 *
2523 * A value of 5us seems to be a good balance; safe for very low end
2524 * platforms but not overly aggressive on lower latency configs.
2525 */
2526 static const int latency_ns = 5000;
2527
2528 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2529 {
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 uint32_t dsparb = I915_READ(DSPARB);
2532 int size;
2533
2534 if (plane == 0)
2535 size = dsparb & 0x7f;
2536 else
2537 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2538 (dsparb & 0x7f);
2539
2540 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2541 plane ? "B" : "A", size);
2542
2543 return size;
2544 }
2545
2546 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2547 {
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 uint32_t dsparb = I915_READ(DSPARB);
2550 int size;
2551
2552 if (plane == 0)
2553 size = dsparb & 0x1ff;
2554 else
2555 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2556 (dsparb & 0x1ff);
2557 size >>= 1; /* Convert to cachelines */
2558
2559 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2560 plane ? "B" : "A", size);
2561
2562 return size;
2563 }
2564
2565 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2566 {
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 uint32_t dsparb = I915_READ(DSPARB);
2569 int size;
2570
2571 size = dsparb & 0x7f;
2572 size >>= 2; /* Convert to cachelines */
2573
2574 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2575 plane ? "B" : "A",
2576 size);
2577
2578 return size;
2579 }
2580
2581 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2582 {
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 uint32_t dsparb = I915_READ(DSPARB);
2585 int size;
2586
2587 size = dsparb & 0x7f;
2588 size >>= 1; /* Convert to cachelines */
2589
2590 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2591 plane ? "B" : "A", size);
2592
2593 return size;
2594 }
2595
2596 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2597 int planeb_clock, int sr_hdisplay, int pixel_size)
2598 {
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 int total_size, cacheline_size;
2601 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2602 struct intel_watermark_params planea_params, planeb_params;
2603 unsigned long line_time_us;
2604 int sr_clock, sr_entries = 0, entries_required;
2605
2606 /* Create copies of the base settings for each pipe */
2607 planea_params = planeb_params = g4x_wm_info;
2608
2609 /* Grab a couple of global values before we overwrite them */
2610 total_size = planea_params.fifo_size;
2611 cacheline_size = planea_params.cacheline_size;
2612
2613 /*
2614 * Note: we need to make sure we don't overflow for various clock &
2615 * latency values.
2616 * clocks go from a few thousand to several hundred thousand.
2617 * latency is usually a few thousand
2618 */
2619 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2620 1000;
2621 entries_required /= G4X_FIFO_LINE_SIZE;
2622 planea_wm = entries_required + planea_params.guard_size;
2623
2624 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2625 1000;
2626 entries_required /= G4X_FIFO_LINE_SIZE;
2627 planeb_wm = entries_required + planeb_params.guard_size;
2628
2629 cursora_wm = cursorb_wm = 16;
2630 cursor_sr = 32;
2631
2632 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2633
2634 /* Calc sr entries for one plane configs */
2635 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2636 /* self-refresh has much higher latency */
2637 static const int sr_latency_ns = 12000;
2638
2639 sr_clock = planea_clock ? planea_clock : planeb_clock;
2640 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2641
2642 /* Use ns/us then divide to preserve precision */
2643 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2644 pixel_size * sr_hdisplay) / 1000;
2645 sr_entries = roundup(sr_entries / cacheline_size, 1);
2646 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2647 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2648 } else {
2649 /* Turn off self refresh if both pipes are enabled */
2650 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2651 & ~FW_BLC_SELF_EN);
2652 }
2653
2654 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2655 planea_wm, planeb_wm, sr_entries);
2656
2657 planea_wm &= 0x3f;
2658 planeb_wm &= 0x3f;
2659
2660 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2661 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2662 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2663 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2664 (cursora_wm << DSPFW_CURSORA_SHIFT));
2665 /* HPLL off in SR has some issues on G4x... disable it */
2666 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2667 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2668 }
2669
2670 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2671 int planeb_clock, int sr_hdisplay, int pixel_size)
2672 {
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 unsigned long line_time_us;
2675 int sr_clock, sr_entries, srwm = 1;
2676
2677 /* Calc sr entries for one plane configs */
2678 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2679 /* self-refresh has much higher latency */
2680 static const int sr_latency_ns = 12000;
2681
2682 sr_clock = planea_clock ? planea_clock : planeb_clock;
2683 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2684
2685 /* Use ns/us then divide to preserve precision */
2686 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2687 pixel_size * sr_hdisplay) / 1000;
2688 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2689 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2690 srwm = I945_FIFO_SIZE - sr_entries;
2691 if (srwm < 0)
2692 srwm = 1;
2693 srwm &= 0x3f;
2694 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2695 } else {
2696 /* Turn off self refresh if both pipes are enabled */
2697 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2698 & ~FW_BLC_SELF_EN);
2699 }
2700
2701 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2702 srwm);
2703
2704 /* 965 has limitations... */
2705 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2706 (8 << 0));
2707 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2708 }
2709
2710 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2711 int planeb_clock, int sr_hdisplay, int pixel_size)
2712 {
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 uint32_t fwater_lo;
2715 uint32_t fwater_hi;
2716 int total_size, cacheline_size, cwm, srwm = 1;
2717 int planea_wm, planeb_wm;
2718 struct intel_watermark_params planea_params, planeb_params;
2719 unsigned long line_time_us;
2720 int sr_clock, sr_entries = 0;
2721
2722 /* Create copies of the base settings for each pipe */
2723 if (IS_I965GM(dev) || IS_I945GM(dev))
2724 planea_params = planeb_params = i945_wm_info;
2725 else if (IS_I9XX(dev))
2726 planea_params = planeb_params = i915_wm_info;
2727 else
2728 planea_params = planeb_params = i855_wm_info;
2729
2730 /* Grab a couple of global values before we overwrite them */
2731 total_size = planea_params.fifo_size;
2732 cacheline_size = planea_params.cacheline_size;
2733
2734 /* Update per-plane FIFO sizes */
2735 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2736 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2737
2738 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2739 pixel_size, latency_ns);
2740 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2741 pixel_size, latency_ns);
2742 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2743
2744 /*
2745 * Overlay gets an aggressive default since video jitter is bad.
2746 */
2747 cwm = 2;
2748
2749 /* Calc sr entries for one plane configs */
2750 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2751 (!planea_clock || !planeb_clock)) {
2752 /* self-refresh has much higher latency */
2753 static const int sr_latency_ns = 6000;
2754
2755 sr_clock = planea_clock ? planea_clock : planeb_clock;
2756 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2757
2758 /* Use ns/us then divide to preserve precision */
2759 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2760 pixel_size * sr_hdisplay) / 1000;
2761 sr_entries = roundup(sr_entries / cacheline_size, 1);
2762 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2763 srwm = total_size - sr_entries;
2764 if (srwm < 0)
2765 srwm = 1;
2766
2767 if (IS_I945G(dev) || IS_I945GM(dev))
2768 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2769 else if (IS_I915GM(dev)) {
2770 /* 915M has a smaller SRWM field */
2771 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2772 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2773 }
2774 } else {
2775 /* Turn off self refresh if both pipes are enabled */
2776 if (IS_I945G(dev) || IS_I945GM(dev)) {
2777 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2778 & ~FW_BLC_SELF_EN);
2779 } else if (IS_I915GM(dev)) {
2780 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2781 }
2782 }
2783
2784 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2785 planea_wm, planeb_wm, cwm, srwm);
2786
2787 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2788 fwater_hi = (cwm & 0x1f);
2789
2790 /* Set request length to 8 cachelines per fetch */
2791 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2792 fwater_hi = fwater_hi | (1 << 8);
2793
2794 I915_WRITE(FW_BLC, fwater_lo);
2795 I915_WRITE(FW_BLC2, fwater_hi);
2796 }
2797
2798 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2799 int unused2, int pixel_size)
2800 {
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2803 int planea_wm;
2804
2805 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2806
2807 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2808 pixel_size, latency_ns);
2809 fwater_lo |= (3<<8) | planea_wm;
2810
2811 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2812
2813 I915_WRITE(FW_BLC, fwater_lo);
2814 }
2815
2816 /**
2817 * intel_update_watermarks - update FIFO watermark values based on current modes
2818 *
2819 * Calculate watermark values for the various WM regs based on current mode
2820 * and plane configuration.
2821 *
2822 * There are several cases to deal with here:
2823 * - normal (i.e. non-self-refresh)
2824 * - self-refresh (SR) mode
2825 * - lines are large relative to FIFO size (buffer can hold up to 2)
2826 * - lines are small relative to FIFO size (buffer can hold more than 2
2827 * lines), so need to account for TLB latency
2828 *
2829 * The normal calculation is:
2830 * watermark = dotclock * bytes per pixel * latency
2831 * where latency is platform & configuration dependent (we assume pessimal
2832 * values here).
2833 *
2834 * The SR calculation is:
2835 * watermark = (trunc(latency/line time)+1) * surface width *
2836 * bytes per pixel
2837 * where
2838 * line time = htotal / dotclock
2839 * and latency is assumed to be high, as above.
2840 *
2841 * The final value programmed to the register should always be rounded up,
2842 * and include an extra 2 entries to account for clock crossings.
2843 *
2844 * We don't use the sprite, so we can ignore that. And on Crestline we have
2845 * to set the non-SR watermarks to 8.
2846 */
2847 static void intel_update_watermarks(struct drm_device *dev)
2848 {
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct drm_crtc *crtc;
2851 struct intel_crtc *intel_crtc;
2852 int sr_hdisplay = 0;
2853 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2854 int enabled = 0, pixel_size = 0;
2855
2856 if (!dev_priv->display.update_wm)
2857 return;
2858
2859 /* Get the clock config from both planes */
2860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2861 intel_crtc = to_intel_crtc(crtc);
2862 if (crtc->enabled) {
2863 enabled++;
2864 if (intel_crtc->plane == 0) {
2865 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2866 intel_crtc->pipe, crtc->mode.clock);
2867 planea_clock = crtc->mode.clock;
2868 } else {
2869 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2870 intel_crtc->pipe, crtc->mode.clock);
2871 planeb_clock = crtc->mode.clock;
2872 }
2873 sr_hdisplay = crtc->mode.hdisplay;
2874 sr_clock = crtc->mode.clock;
2875 if (crtc->fb)
2876 pixel_size = crtc->fb->bits_per_pixel / 8;
2877 else
2878 pixel_size = 4; /* by default */
2879 }
2880 }
2881
2882 if (enabled <= 0)
2883 return;
2884
2885 /* Single plane configs can enable self refresh */
2886 if (enabled == 1 && IS_PINEVIEW(dev))
2887 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2888 else if (IS_PINEVIEW(dev))
2889 pineview_disable_cxsr(dev);
2890
2891 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2892 sr_hdisplay, pixel_size);
2893 }
2894
2895 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2896 struct drm_display_mode *mode,
2897 struct drm_display_mode *adjusted_mode,
2898 int x, int y,
2899 struct drm_framebuffer *old_fb)
2900 {
2901 struct drm_device *dev = crtc->dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2904 int pipe = intel_crtc->pipe;
2905 int plane = intel_crtc->plane;
2906 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2907 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2908 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2909 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2910 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2911 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2912 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2913 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2914 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2915 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2916 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2917 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2918 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2919 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2920 int refclk, num_connectors = 0;
2921 intel_clock_t clock, reduced_clock;
2922 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2923 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2924 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2925 bool is_edp = false;
2926 struct drm_mode_config *mode_config = &dev->mode_config;
2927 struct drm_connector *connector;
2928 const intel_limit_t *limit;
2929 int ret;
2930 struct fdi_m_n m_n = {0};
2931 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2932 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2933 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2934 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2935 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2936 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2937 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2938 int lvds_reg = LVDS;
2939 u32 temp;
2940 int sdvo_pixel_multiply;
2941 int target_clock;
2942
2943 drm_vblank_pre_modeset(dev, pipe);
2944
2945 list_for_each_entry(connector, &mode_config->connector_list, head) {
2946 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2947
2948 if (!connector->encoder || connector->encoder->crtc != crtc)
2949 continue;
2950
2951 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS:
2953 is_lvds = true;
2954 break;
2955 case INTEL_OUTPUT_SDVO:
2956 case INTEL_OUTPUT_HDMI:
2957 is_sdvo = true;
2958 if (intel_encoder->needs_tv_clock)
2959 is_tv = true;
2960 break;
2961 case INTEL_OUTPUT_DVO:
2962 is_dvo = true;
2963 break;
2964 case INTEL_OUTPUT_TVOUT:
2965 is_tv = true;
2966 break;
2967 case INTEL_OUTPUT_ANALOG:
2968 is_crt = true;
2969 break;
2970 case INTEL_OUTPUT_DISPLAYPORT:
2971 is_dp = true;
2972 break;
2973 case INTEL_OUTPUT_EDP:
2974 is_edp = true;
2975 break;
2976 }
2977
2978 num_connectors++;
2979 }
2980
2981 if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
2982 refclk = dev_priv->lvds_ssc_freq * 1000;
2983 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2984 refclk / 1000);
2985 } else if (IS_I9XX(dev)) {
2986 refclk = 96000;
2987 if (HAS_PCH_SPLIT(dev))
2988 refclk = 120000; /* 120Mhz refclk */
2989 } else {
2990 refclk = 48000;
2991 }
2992
2993
2994 /*
2995 * Returns a set of divisors for the desired target clock with the given
2996 * refclk, or FALSE. The returned values represent the clock equation:
2997 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2998 */
2999 limit = intel_limit(crtc);
3000 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3001 if (!ok) {
3002 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3003 drm_vblank_post_modeset(dev, pipe);
3004 return -EINVAL;
3005 }
3006
3007 if (is_lvds && dev_priv->lvds_downclock_avail) {
3008 has_reduced_clock = limit->find_pll(limit, crtc,
3009 dev_priv->lvds_downclock,
3010 refclk,
3011 &reduced_clock);
3012 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3013 /*
3014 * If the different P is found, it means that we can't
3015 * switch the display clock by using the FP0/FP1.
3016 * In such case we will disable the LVDS downclock
3017 * feature.
3018 */
3019 DRM_DEBUG_KMS("Different P is found for "
3020 "LVDS clock/downclock\n");
3021 has_reduced_clock = 0;
3022 }
3023 }
3024 /* SDVO TV has fixed PLL values depend on its clock range,
3025 this mirrors vbios setting. */
3026 if (is_sdvo && is_tv) {
3027 if (adjusted_mode->clock >= 100000
3028 && adjusted_mode->clock < 140500) {
3029 clock.p1 = 2;
3030 clock.p2 = 10;
3031 clock.n = 3;
3032 clock.m1 = 16;
3033 clock.m2 = 8;
3034 } else if (adjusted_mode->clock >= 140500
3035 && adjusted_mode->clock <= 200000) {
3036 clock.p1 = 1;
3037 clock.p2 = 10;
3038 clock.n = 6;
3039 clock.m1 = 12;
3040 clock.m2 = 8;
3041 }
3042 }
3043
3044 /* FDI link */
3045 if (HAS_PCH_SPLIT(dev)) {
3046 int lane, link_bw, bpp;
3047 /* eDP doesn't require FDI link, so just set DP M/N
3048 according to current link config */
3049 if (is_edp) {
3050 struct drm_connector *edp;
3051 target_clock = mode->clock;
3052 edp = intel_pipe_get_connector(crtc);
3053 intel_edp_link_config(to_intel_encoder(edp),
3054 &lane, &link_bw);
3055 } else {
3056 /* DP over FDI requires target mode clock
3057 instead of link clock */
3058 if (is_dp)
3059 target_clock = mode->clock;
3060 else
3061 target_clock = adjusted_mode->clock;
3062 lane = 4;
3063 link_bw = 270000;
3064 }
3065
3066 /* determine panel color depth */
3067 temp = I915_READ(pipeconf_reg);
3068 temp &= ~PIPE_BPC_MASK;
3069 if (is_lvds) {
3070 int lvds_reg = I915_READ(PCH_LVDS);
3071 /* the BPC will be 6 if it is 18-bit LVDS panel */
3072 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3073 temp |= PIPE_8BPC;
3074 else
3075 temp |= PIPE_6BPC;
3076 } else if (is_edp) {
3077 switch (dev_priv->edp_bpp/3) {
3078 case 8:
3079 temp |= PIPE_8BPC;
3080 break;
3081 case 10:
3082 temp |= PIPE_10BPC;
3083 break;
3084 case 6:
3085 temp |= PIPE_6BPC;
3086 break;
3087 case 12:
3088 temp |= PIPE_12BPC;
3089 break;
3090 }
3091 } else
3092 temp |= PIPE_8BPC;
3093 I915_WRITE(pipeconf_reg, temp);
3094 I915_READ(pipeconf_reg);
3095
3096 switch (temp & PIPE_BPC_MASK) {
3097 case PIPE_8BPC:
3098 bpp = 24;
3099 break;
3100 case PIPE_10BPC:
3101 bpp = 30;
3102 break;
3103 case PIPE_6BPC:
3104 bpp = 18;
3105 break;
3106 case PIPE_12BPC:
3107 bpp = 36;
3108 break;
3109 default:
3110 DRM_ERROR("unknown pipe bpc value\n");
3111 bpp = 24;
3112 }
3113
3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3115 }
3116
3117 /* Ironlake: try to setup display ref clock before DPLL
3118 * enabling. This is only under driver's control after
3119 * PCH B stepping, previous chipset stepping should be
3120 * ignoring this setting.
3121 */
3122 if (HAS_PCH_SPLIT(dev)) {
3123 temp = I915_READ(PCH_DREF_CONTROL);
3124 /* Always enable nonspread source */
3125 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3126 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3127 I915_WRITE(PCH_DREF_CONTROL, temp);
3128 POSTING_READ(PCH_DREF_CONTROL);
3129
3130 temp &= ~DREF_SSC_SOURCE_MASK;
3131 temp |= DREF_SSC_SOURCE_ENABLE;
3132 I915_WRITE(PCH_DREF_CONTROL, temp);
3133 POSTING_READ(PCH_DREF_CONTROL);
3134
3135 udelay(200);
3136
3137 if (is_edp) {
3138 if (dev_priv->lvds_use_ssc) {
3139 temp |= DREF_SSC1_ENABLE;
3140 I915_WRITE(PCH_DREF_CONTROL, temp);
3141 POSTING_READ(PCH_DREF_CONTROL);
3142
3143 udelay(200);
3144
3145 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3146 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3147 I915_WRITE(PCH_DREF_CONTROL, temp);
3148 POSTING_READ(PCH_DREF_CONTROL);
3149 } else {
3150 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3151 I915_WRITE(PCH_DREF_CONTROL, temp);
3152 POSTING_READ(PCH_DREF_CONTROL);
3153 }
3154 }
3155 }
3156
3157 if (IS_PINEVIEW(dev)) {
3158 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3159 if (has_reduced_clock)
3160 fp2 = (1 << reduced_clock.n) << 16 |
3161 reduced_clock.m1 << 8 | reduced_clock.m2;
3162 } else {
3163 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3164 if (has_reduced_clock)
3165 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3166 reduced_clock.m2;
3167 }
3168
3169 if (!HAS_PCH_SPLIT(dev))
3170 dpll = DPLL_VGA_MODE_DIS;
3171
3172 if (IS_I9XX(dev)) {
3173 if (is_lvds)
3174 dpll |= DPLLB_MODE_LVDS;
3175 else
3176 dpll |= DPLLB_MODE_DAC_SERIAL;
3177 if (is_sdvo) {
3178 dpll |= DPLL_DVO_HIGH_SPEED;
3179 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3180 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3181 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3182 else if (HAS_PCH_SPLIT(dev))
3183 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3184 }
3185 if (is_dp)
3186 dpll |= DPLL_DVO_HIGH_SPEED;
3187
3188 /* compute bitmask from p1 value */
3189 if (IS_PINEVIEW(dev))
3190 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3191 else {
3192 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3193 /* also FPA1 */
3194 if (HAS_PCH_SPLIT(dev))
3195 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3196 if (IS_G4X(dev) && has_reduced_clock)
3197 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3198 }
3199 switch (clock.p2) {
3200 case 5:
3201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3202 break;
3203 case 7:
3204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3205 break;
3206 case 10:
3207 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3208 break;
3209 case 14:
3210 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3211 break;
3212 }
3213 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3214 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3215 } else {
3216 if (is_lvds) {
3217 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3218 } else {
3219 if (clock.p1 == 2)
3220 dpll |= PLL_P1_DIVIDE_BY_TWO;
3221 else
3222 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3223 if (clock.p2 == 4)
3224 dpll |= PLL_P2_DIVIDE_BY_4;
3225 }
3226 }
3227
3228 if (is_sdvo && is_tv)
3229 dpll |= PLL_REF_INPUT_TVCLKINBC;
3230 else if (is_tv)
3231 /* XXX: just matching BIOS for now */
3232 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3233 dpll |= 3;
3234 else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3235 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3236 else
3237 dpll |= PLL_REF_INPUT_DREFCLK;
3238
3239 /* setup pipeconf */
3240 pipeconf = I915_READ(pipeconf_reg);
3241
3242 /* Set up the display plane register */
3243 dspcntr = DISPPLANE_GAMMA_ENABLE;
3244
3245 /* Ironlake's plane is forced to pipe, bit 24 is to
3246 enable color space conversion */
3247 if (!HAS_PCH_SPLIT(dev)) {
3248 if (pipe == 0)
3249 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3250 else
3251 dspcntr |= DISPPLANE_SEL_PIPE_B;
3252 }
3253
3254 if (pipe == 0 && !IS_I965G(dev)) {
3255 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3256 * core speed.
3257 *
3258 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3259 * pipe == 0 check?
3260 */
3261 if (mode->clock >
3262 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3263 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3264 else
3265 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3266 }
3267
3268 dspcntr |= DISPLAY_PLANE_ENABLE;
3269 pipeconf |= PIPEACONF_ENABLE;
3270 dpll |= DPLL_VCO_ENABLE;
3271
3272
3273 /* Disable the panel fitter if it was on our pipe */
3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3275 I915_WRITE(PFIT_CONTROL, 0);
3276
3277 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3278 drm_mode_debug_printmodeline(mode);
3279
3280 /* assign to Ironlake registers */
3281 if (HAS_PCH_SPLIT(dev)) {
3282 fp_reg = pch_fp_reg;
3283 dpll_reg = pch_dpll_reg;
3284 }
3285
3286 if (is_edp) {
3287 ironlake_disable_pll_edp(crtc);
3288 } else if ((dpll & DPLL_VCO_ENABLE)) {
3289 I915_WRITE(fp_reg, fp);
3290 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3291 I915_READ(dpll_reg);
3292 udelay(150);
3293 }
3294
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn
3297 * things on.
3298 */
3299 if (is_lvds) {
3300 u32 lvds;
3301
3302 if (HAS_PCH_SPLIT(dev))
3303 lvds_reg = PCH_LVDS;
3304
3305 lvds = I915_READ(lvds_reg);
3306 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3307 /* set the corresponsding LVDS_BORDER bit */
3308 lvds |= dev_priv->lvds_border_bits;
3309 /* Set the B0-B3 data pairs corresponding to whether we're going to
3310 * set the DPLLs for dual-channel mode or not.
3311 */
3312 if (clock.p2 == 7)
3313 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3314 else
3315 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3316
3317 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3318 * appropriately here, but we need to look more thoroughly into how
3319 * panels behave in the two modes.
3320 */
3321 /* set the dithering flag */
3322 if (IS_I965G(dev)) {
3323 if (dev_priv->lvds_dither) {
3324 if (HAS_PCH_SPLIT(dev))
3325 pipeconf |= PIPE_ENABLE_DITHER;
3326 else
3327 lvds |= LVDS_ENABLE_DITHER;
3328 } else {
3329 if (HAS_PCH_SPLIT(dev))
3330 pipeconf &= ~PIPE_ENABLE_DITHER;
3331 else
3332 lvds &= ~LVDS_ENABLE_DITHER;
3333 }
3334 }
3335 I915_WRITE(lvds_reg, lvds);
3336 I915_READ(lvds_reg);
3337 }
3338 if (is_dp)
3339 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3340
3341 if (!is_edp) {
3342 I915_WRITE(fp_reg, fp);
3343 I915_WRITE(dpll_reg, dpll);
3344 I915_READ(dpll_reg);
3345 /* Wait for the clocks to stabilize. */
3346 udelay(150);
3347
3348 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3349 if (is_sdvo) {
3350 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3351 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3352 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3353 } else
3354 I915_WRITE(dpll_md_reg, 0);
3355 } else {
3356 /* write it again -- the BIOS does, after all */
3357 I915_WRITE(dpll_reg, dpll);
3358 }
3359 I915_READ(dpll_reg);
3360 /* Wait for the clocks to stabilize. */
3361 udelay(150);
3362 }
3363
3364 if (is_lvds && has_reduced_clock && i915_powersave) {
3365 I915_WRITE(fp_reg + 4, fp2);
3366 intel_crtc->lowfreq_avail = true;
3367 if (HAS_PIPE_CXSR(dev)) {
3368 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3369 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3370 }
3371 } else {
3372 I915_WRITE(fp_reg + 4, fp);
3373 intel_crtc->lowfreq_avail = false;
3374 if (HAS_PIPE_CXSR(dev)) {
3375 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3376 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3377 }
3378 }
3379
3380 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3381 ((adjusted_mode->crtc_htotal - 1) << 16));
3382 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3383 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3384 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3385 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3386 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3387 ((adjusted_mode->crtc_vtotal - 1) << 16));
3388 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3389 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3390 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3391 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3392 /* pipesrc and dspsize control the size that is scaled from, which should
3393 * always be the user's requested size.
3394 */
3395 if (!HAS_PCH_SPLIT(dev)) {
3396 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3397 (mode->hdisplay - 1));
3398 I915_WRITE(dsppos_reg, 0);
3399 }
3400 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3401
3402 if (HAS_PCH_SPLIT(dev)) {
3403 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3404 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3405 I915_WRITE(link_m1_reg, m_n.link_m);
3406 I915_WRITE(link_n1_reg, m_n.link_n);
3407
3408 if (is_edp) {
3409 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3410 } else {
3411 /* enable FDI RX PLL too */
3412 temp = I915_READ(fdi_rx_reg);
3413 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3414 udelay(200);
3415 }
3416 }
3417
3418 I915_WRITE(pipeconf_reg, pipeconf);
3419 I915_READ(pipeconf_reg);
3420
3421 intel_wait_for_vblank(dev);
3422
3423 if (IS_IRONLAKE(dev)) {
3424 /* enable address swizzle for tiling buffer */
3425 temp = I915_READ(DISP_ARB_CTL);
3426 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3427 }
3428
3429 I915_WRITE(dspcntr_reg, dspcntr);
3430
3431 /* Flush the plane changes */
3432 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3433
3434 if ((IS_I965G(dev) || plane == 0))
3435 intel_update_fbc(crtc, &crtc->mode);
3436
3437 intel_update_watermarks(dev);
3438
3439 drm_vblank_post_modeset(dev, pipe);
3440
3441 return ret;
3442 }
3443
3444 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3445 void intel_crtc_load_lut(struct drm_crtc *crtc)
3446 {
3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3451 int i;
3452
3453 /* The clocks have to be on to load the palette. */
3454 if (!crtc->enabled)
3455 return;
3456
3457 /* use legacy palette for Ironlake */
3458 if (HAS_PCH_SPLIT(dev))
3459 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3460 LGC_PALETTE_B;
3461
3462 for (i = 0; i < 256; i++) {
3463 I915_WRITE(palreg + 4 * i,
3464 (intel_crtc->lut_r[i] << 16) |
3465 (intel_crtc->lut_g[i] << 8) |
3466 intel_crtc->lut_b[i]);
3467 }
3468 }
3469
3470 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3471 struct drm_file *file_priv,
3472 uint32_t handle,
3473 uint32_t width, uint32_t height)
3474 {
3475 struct drm_device *dev = crtc->dev;
3476 struct drm_i915_private *dev_priv = dev->dev_private;
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 struct drm_gem_object *bo;
3479 struct drm_i915_gem_object *obj_priv;
3480 int pipe = intel_crtc->pipe;
3481 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3482 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3483 uint32_t temp = I915_READ(control);
3484 size_t addr;
3485 int ret;
3486
3487 DRM_DEBUG_KMS("\n");
3488
3489 /* if we want to turn off the cursor ignore width and height */
3490 if (!handle) {
3491 DRM_DEBUG_KMS("cursor off\n");
3492 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3493 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3494 temp |= CURSOR_MODE_DISABLE;
3495 } else {
3496 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3497 }
3498 addr = 0;
3499 bo = NULL;
3500 mutex_lock(&dev->struct_mutex);
3501 goto finish;
3502 }
3503
3504 /* Currently we only support 64x64 cursors */
3505 if (width != 64 || height != 64) {
3506 DRM_ERROR("we currently only support 64x64 cursors\n");
3507 return -EINVAL;
3508 }
3509
3510 bo = drm_gem_object_lookup(dev, file_priv, handle);
3511 if (!bo)
3512 return -ENOENT;
3513
3514 obj_priv = to_intel_bo(bo);
3515
3516 if (bo->size < width * height * 4) {
3517 DRM_ERROR("buffer is to small\n");
3518 ret = -ENOMEM;
3519 goto fail;
3520 }
3521
3522 /* we only need to pin inside GTT if cursor is non-phy */
3523 mutex_lock(&dev->struct_mutex);
3524 if (!dev_priv->info->cursor_needs_physical) {
3525 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3526 if (ret) {
3527 DRM_ERROR("failed to pin cursor bo\n");
3528 goto fail_locked;
3529 }
3530 addr = obj_priv->gtt_offset;
3531 } else {
3532 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3533 if (ret) {
3534 DRM_ERROR("failed to attach phys object\n");
3535 goto fail_locked;
3536 }
3537 addr = obj_priv->phys_obj->handle->busaddr;
3538 }
3539
3540 if (!IS_I9XX(dev))
3541 I915_WRITE(CURSIZE, (height << 12) | width);
3542
3543 /* Hooray for CUR*CNTR differences */
3544 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3545 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3546 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3547 temp |= (pipe << 28); /* Connect to correct pipe */
3548 } else {
3549 temp &= ~(CURSOR_FORMAT_MASK);
3550 temp |= CURSOR_ENABLE;
3551 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3552 }
3553
3554 finish:
3555 I915_WRITE(control, temp);
3556 I915_WRITE(base, addr);
3557
3558 if (intel_crtc->cursor_bo) {
3559 if (dev_priv->info->cursor_needs_physical) {
3560 if (intel_crtc->cursor_bo != bo)
3561 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3562 } else
3563 i915_gem_object_unpin(intel_crtc->cursor_bo);
3564 drm_gem_object_unreference(intel_crtc->cursor_bo);
3565 }
3566
3567 mutex_unlock(&dev->struct_mutex);
3568
3569 intel_crtc->cursor_addr = addr;
3570 intel_crtc->cursor_bo = bo;
3571
3572 return 0;
3573 fail_locked:
3574 mutex_unlock(&dev->struct_mutex);
3575 fail:
3576 drm_gem_object_unreference_unlocked(bo);
3577 return ret;
3578 }
3579
3580 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3581 {
3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3585 struct intel_framebuffer *intel_fb;
3586 int pipe = intel_crtc->pipe;
3587 uint32_t temp = 0;
3588 uint32_t adder;
3589
3590 if (crtc->fb) {
3591 intel_fb = to_intel_framebuffer(crtc->fb);
3592 intel_mark_busy(dev, intel_fb->obj);
3593 }
3594
3595 if (x < 0) {
3596 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3597 x = -x;
3598 }
3599 if (y < 0) {
3600 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3601 y = -y;
3602 }
3603
3604 temp |= x << CURSOR_X_SHIFT;
3605 temp |= y << CURSOR_Y_SHIFT;
3606
3607 adder = intel_crtc->cursor_addr;
3608 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3609 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3610
3611 return 0;
3612 }
3613
3614 /** Sets the color ramps on behalf of RandR */
3615 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3616 u16 blue, int regno)
3617 {
3618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619
3620 intel_crtc->lut_r[regno] = red >> 8;
3621 intel_crtc->lut_g[regno] = green >> 8;
3622 intel_crtc->lut_b[regno] = blue >> 8;
3623 }
3624
3625 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3626 u16 *blue, int regno)
3627 {
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629
3630 *red = intel_crtc->lut_r[regno] << 8;
3631 *green = intel_crtc->lut_g[regno] << 8;
3632 *blue = intel_crtc->lut_b[regno] << 8;
3633 }
3634
3635 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3636 u16 *blue, uint32_t size)
3637 {
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 int i;
3640
3641 if (size != 256)
3642 return;
3643
3644 for (i = 0; i < 256; i++) {
3645 intel_crtc->lut_r[i] = red[i] >> 8;
3646 intel_crtc->lut_g[i] = green[i] >> 8;
3647 intel_crtc->lut_b[i] = blue[i] >> 8;
3648 }
3649
3650 intel_crtc_load_lut(crtc);
3651 }
3652
3653 /**
3654 * Get a pipe with a simple mode set on it for doing load-based monitor
3655 * detection.
3656 *
3657 * It will be up to the load-detect code to adjust the pipe as appropriate for
3658 * its requirements. The pipe will be connected to no other encoders.
3659 *
3660 * Currently this code will only succeed if there is a pipe with no encoders
3661 * configured for it. In the future, it could choose to temporarily disable
3662 * some outputs to free up a pipe for its use.
3663 *
3664 * \return crtc, or NULL if no pipes are available.
3665 */
3666
3667 /* VESA 640x480x72Hz mode to set on the pipe */
3668 static struct drm_display_mode load_detect_mode = {
3669 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3670 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3671 };
3672
3673 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3674 struct drm_display_mode *mode,
3675 int *dpms_mode)
3676 {
3677 struct intel_crtc *intel_crtc;
3678 struct drm_crtc *possible_crtc;
3679 struct drm_crtc *supported_crtc =NULL;
3680 struct drm_encoder *encoder = &intel_encoder->enc;
3681 struct drm_crtc *crtc = NULL;
3682 struct drm_device *dev = encoder->dev;
3683 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3684 struct drm_crtc_helper_funcs *crtc_funcs;
3685 int i = -1;
3686
3687 /*
3688 * Algorithm gets a little messy:
3689 * - if the connector already has an assigned crtc, use it (but make
3690 * sure it's on first)
3691 * - try to find the first unused crtc that can drive this connector,
3692 * and use that if we find one
3693 * - if there are no unused crtcs available, try to use the first
3694 * one we found that supports the connector
3695 */
3696
3697 /* See if we already have a CRTC for this connector */
3698 if (encoder->crtc) {
3699 crtc = encoder->crtc;
3700 /* Make sure the crtc and connector are running */
3701 intel_crtc = to_intel_crtc(crtc);
3702 *dpms_mode = intel_crtc->dpms_mode;
3703 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3704 crtc_funcs = crtc->helper_private;
3705 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3706 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3707 }
3708 return crtc;
3709 }
3710
3711 /* Find an unused one (if possible) */
3712 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3713 i++;
3714 if (!(encoder->possible_crtcs & (1 << i)))
3715 continue;
3716 if (!possible_crtc->enabled) {
3717 crtc = possible_crtc;
3718 break;
3719 }
3720 if (!supported_crtc)
3721 supported_crtc = possible_crtc;
3722 }
3723
3724 /*
3725 * If we didn't find an unused CRTC, don't use any.
3726 */
3727 if (!crtc) {
3728 return NULL;
3729 }
3730
3731 encoder->crtc = crtc;
3732 intel_encoder->base.encoder = encoder;
3733 intel_encoder->load_detect_temp = true;
3734
3735 intel_crtc = to_intel_crtc(crtc);
3736 *dpms_mode = intel_crtc->dpms_mode;
3737
3738 if (!crtc->enabled) {
3739 if (!mode)
3740 mode = &load_detect_mode;
3741 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3742 } else {
3743 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3744 crtc_funcs = crtc->helper_private;
3745 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3746 }
3747
3748 /* Add this connector to the crtc */
3749 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3750 encoder_funcs->commit(encoder);
3751 }
3752 /* let the connector get through one full cycle before testing */
3753 intel_wait_for_vblank(dev);
3754
3755 return crtc;
3756 }
3757
3758 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode)
3759 {
3760 struct drm_encoder *encoder = &intel_encoder->enc;
3761 struct drm_device *dev = encoder->dev;
3762 struct drm_crtc *crtc = encoder->crtc;
3763 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3764 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3765
3766 if (intel_encoder->load_detect_temp) {
3767 encoder->crtc = NULL;
3768 intel_encoder->base.encoder = NULL;
3769 intel_encoder->load_detect_temp = false;
3770 crtc->enabled = drm_helper_crtc_in_use(crtc);
3771 drm_helper_disable_unused_functions(dev);
3772 }
3773
3774 /* Switch crtc and encoder back off if necessary */
3775 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3776 if (encoder->crtc == crtc)
3777 encoder_funcs->dpms(encoder, dpms_mode);
3778 crtc_funcs->dpms(crtc, dpms_mode);
3779 }
3780 }
3781
3782 /* Returns the clock of the currently programmed mode of the given pipe. */
3783 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3784 {
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787 int pipe = intel_crtc->pipe;
3788 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3789 u32 fp;
3790 intel_clock_t clock;
3791
3792 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3793 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3794 else
3795 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3796
3797 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3798 if (IS_PINEVIEW(dev)) {
3799 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3800 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3801 } else {
3802 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3803 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3804 }
3805
3806 if (IS_I9XX(dev)) {
3807 if (IS_PINEVIEW(dev))
3808 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3809 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3810 else
3811 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3812 DPLL_FPA01_P1_POST_DIV_SHIFT);
3813
3814 switch (dpll & DPLL_MODE_MASK) {
3815 case DPLLB_MODE_DAC_SERIAL:
3816 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3817 5 : 10;
3818 break;
3819 case DPLLB_MODE_LVDS:
3820 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3821 7 : 14;
3822 break;
3823 default:
3824 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3825 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3826 return 0;
3827 }
3828
3829 /* XXX: Handle the 100Mhz refclk */
3830 intel_clock(dev, 96000, &clock);
3831 } else {
3832 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3833
3834 if (is_lvds) {
3835 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3836 DPLL_FPA01_P1_POST_DIV_SHIFT);
3837 clock.p2 = 14;
3838
3839 if ((dpll & PLL_REF_INPUT_MASK) ==
3840 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3841 /* XXX: might not be 66MHz */
3842 intel_clock(dev, 66000, &clock);
3843 } else
3844 intel_clock(dev, 48000, &clock);
3845 } else {
3846 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3847 clock.p1 = 2;
3848 else {
3849 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3850 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3851 }
3852 if (dpll & PLL_P2_DIVIDE_BY_4)
3853 clock.p2 = 4;
3854 else
3855 clock.p2 = 2;
3856
3857 intel_clock(dev, 48000, &clock);
3858 }
3859 }
3860
3861 /* XXX: It would be nice to validate the clocks, but we can't reuse
3862 * i830PllIsValid() because it relies on the xf86_config connector
3863 * configuration being accurate, which it isn't necessarily.
3864 */
3865
3866 return clock.dot;
3867 }
3868
3869 /** Returns the currently programmed mode of the given pipe. */
3870 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3871 struct drm_crtc *crtc)
3872 {
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3875 int pipe = intel_crtc->pipe;
3876 struct drm_display_mode *mode;
3877 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3878 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3879 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3880 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3881
3882 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3883 if (!mode)
3884 return NULL;
3885
3886 mode->clock = intel_crtc_clock_get(dev, crtc);
3887 mode->hdisplay = (htot & 0xffff) + 1;
3888 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3889 mode->hsync_start = (hsync & 0xffff) + 1;
3890 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3891 mode->vdisplay = (vtot & 0xffff) + 1;
3892 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3893 mode->vsync_start = (vsync & 0xffff) + 1;
3894 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3895
3896 drm_mode_set_name(mode);
3897 drm_mode_set_crtcinfo(mode, 0);
3898
3899 return mode;
3900 }
3901
3902 #define GPU_IDLE_TIMEOUT 500 /* ms */
3903
3904 /* When this timer fires, we've been idle for awhile */
3905 static void intel_gpu_idle_timer(unsigned long arg)
3906 {
3907 struct drm_device *dev = (struct drm_device *)arg;
3908 drm_i915_private_t *dev_priv = dev->dev_private;
3909
3910 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3911
3912 dev_priv->busy = false;
3913
3914 queue_work(dev_priv->wq, &dev_priv->idle_work);
3915 }
3916
3917 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3918
3919 static void intel_crtc_idle_timer(unsigned long arg)
3920 {
3921 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3922 struct drm_crtc *crtc = &intel_crtc->base;
3923 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3924
3925 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3926
3927 intel_crtc->busy = false;
3928
3929 queue_work(dev_priv->wq, &dev_priv->idle_work);
3930 }
3931
3932 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3933 {
3934 struct drm_device *dev = crtc->dev;
3935 drm_i915_private_t *dev_priv = dev->dev_private;
3936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3937 int pipe = intel_crtc->pipe;
3938 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3939 int dpll = I915_READ(dpll_reg);
3940
3941 if (HAS_PCH_SPLIT(dev))
3942 return;
3943
3944 if (!dev_priv->lvds_downclock_avail)
3945 return;
3946
3947 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3948 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3949
3950 /* Unlock panel regs */
3951 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3952
3953 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3954 I915_WRITE(dpll_reg, dpll);
3955 dpll = I915_READ(dpll_reg);
3956 intel_wait_for_vblank(dev);
3957 dpll = I915_READ(dpll_reg);
3958 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3959 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3960
3961 /* ...and lock them again */
3962 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3963 }
3964
3965 /* Schedule downclock */
3966 if (schedule)
3967 mod_timer(&intel_crtc->idle_timer, jiffies +
3968 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3969 }
3970
3971 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3972 {
3973 struct drm_device *dev = crtc->dev;
3974 drm_i915_private_t *dev_priv = dev->dev_private;
3975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3976 int pipe = intel_crtc->pipe;
3977 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3978 int dpll = I915_READ(dpll_reg);
3979
3980 if (HAS_PCH_SPLIT(dev))
3981 return;
3982
3983 if (!dev_priv->lvds_downclock_avail)
3984 return;
3985
3986 /*
3987 * Since this is called by a timer, we should never get here in
3988 * the manual case.
3989 */
3990 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3991 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3992
3993 /* Unlock panel regs */
3994 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3995
3996 dpll |= DISPLAY_RATE_SELECT_FPA1;
3997 I915_WRITE(dpll_reg, dpll);
3998 dpll = I915_READ(dpll_reg);
3999 intel_wait_for_vblank(dev);
4000 dpll = I915_READ(dpll_reg);
4001 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4002 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4003
4004 /* ...and lock them again */
4005 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4006 }
4007
4008 }
4009
4010 /**
4011 * intel_idle_update - adjust clocks for idleness
4012 * @work: work struct
4013 *
4014 * Either the GPU or display (or both) went idle. Check the busy status
4015 * here and adjust the CRTC and GPU clocks as necessary.
4016 */
4017 static void intel_idle_update(struct work_struct *work)
4018 {
4019 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4020 idle_work);
4021 struct drm_device *dev = dev_priv->dev;
4022 struct drm_crtc *crtc;
4023 struct intel_crtc *intel_crtc;
4024
4025 if (!i915_powersave)
4026 return;
4027
4028 mutex_lock(&dev->struct_mutex);
4029
4030 if (IS_I945G(dev) || IS_I945GM(dev)) {
4031 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4032 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4033 }
4034
4035 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4036 /* Skip inactive CRTCs */
4037 if (!crtc->fb)
4038 continue;
4039
4040 intel_crtc = to_intel_crtc(crtc);
4041 if (!intel_crtc->busy)
4042 intel_decrease_pllclock(crtc);
4043 }
4044
4045 mutex_unlock(&dev->struct_mutex);
4046 }
4047
4048 /**
4049 * intel_mark_busy - mark the GPU and possibly the display busy
4050 * @dev: drm device
4051 * @obj: object we're operating on
4052 *
4053 * Callers can use this function to indicate that the GPU is busy processing
4054 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4055 * buffer), we'll also mark the display as busy, so we know to increase its
4056 * clock frequency.
4057 */
4058 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4059 {
4060 drm_i915_private_t *dev_priv = dev->dev_private;
4061 struct drm_crtc *crtc = NULL;
4062 struct intel_framebuffer *intel_fb;
4063 struct intel_crtc *intel_crtc;
4064
4065 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4066 return;
4067
4068 if (!dev_priv->busy) {
4069 if (IS_I945G(dev) || IS_I945GM(dev)) {
4070 u32 fw_blc_self;
4071
4072 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4073 fw_blc_self = I915_READ(FW_BLC_SELF);
4074 fw_blc_self &= ~FW_BLC_SELF_EN;
4075 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4076 }
4077 dev_priv->busy = true;
4078 } else
4079 mod_timer(&dev_priv->idle_timer, jiffies +
4080 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4081
4082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4083 if (!crtc->fb)
4084 continue;
4085
4086 intel_crtc = to_intel_crtc(crtc);
4087 intel_fb = to_intel_framebuffer(crtc->fb);
4088 if (intel_fb->obj == obj) {
4089 if (!intel_crtc->busy) {
4090 if (IS_I945G(dev) || IS_I945GM(dev)) {
4091 u32 fw_blc_self;
4092
4093 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4094 fw_blc_self = I915_READ(FW_BLC_SELF);
4095 fw_blc_self &= ~FW_BLC_SELF_EN;
4096 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4097 }
4098 /* Non-busy -> busy, upclock */
4099 intel_increase_pllclock(crtc, true);
4100 intel_crtc->busy = true;
4101 } else {
4102 /* Busy -> busy, put off timer */
4103 mod_timer(&intel_crtc->idle_timer, jiffies +
4104 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4105 }
4106 }
4107 }
4108 }
4109
4110 static void intel_crtc_destroy(struct drm_crtc *crtc)
4111 {
4112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4113
4114 drm_crtc_cleanup(crtc);
4115 kfree(intel_crtc);
4116 }
4117
4118 struct intel_unpin_work {
4119 struct work_struct work;
4120 struct drm_device *dev;
4121 struct drm_gem_object *old_fb_obj;
4122 struct drm_gem_object *pending_flip_obj;
4123 struct drm_pending_vblank_event *event;
4124 int pending;
4125 };
4126
4127 static void intel_unpin_work_fn(struct work_struct *__work)
4128 {
4129 struct intel_unpin_work *work =
4130 container_of(__work, struct intel_unpin_work, work);
4131
4132 mutex_lock(&work->dev->struct_mutex);
4133 i915_gem_object_unpin(work->old_fb_obj);
4134 drm_gem_object_unreference(work->pending_flip_obj);
4135 drm_gem_object_unreference(work->old_fb_obj);
4136 mutex_unlock(&work->dev->struct_mutex);
4137 kfree(work);
4138 }
4139
4140 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4141 {
4142 drm_i915_private_t *dev_priv = dev->dev_private;
4143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145 struct intel_unpin_work *work;
4146 struct drm_i915_gem_object *obj_priv;
4147 struct drm_pending_vblank_event *e;
4148 struct timeval now;
4149 unsigned long flags;
4150
4151 /* Ignore early vblank irqs */
4152 if (intel_crtc == NULL)
4153 return;
4154
4155 spin_lock_irqsave(&dev->event_lock, flags);
4156 work = intel_crtc->unpin_work;
4157 if (work == NULL || !work->pending) {
4158 if (work && !work->pending) {
4159 obj_priv = to_intel_bo(work->pending_flip_obj);
4160 DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4161 obj_priv,
4162 atomic_read(&obj_priv->pending_flip));
4163 }
4164 spin_unlock_irqrestore(&dev->event_lock, flags);
4165 return;
4166 }
4167
4168 intel_crtc->unpin_work = NULL;
4169 drm_vblank_put(dev, intel_crtc->pipe);
4170
4171 if (work->event) {
4172 e = work->event;
4173 do_gettimeofday(&now);
4174 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4175 e->event.tv_sec = now.tv_sec;
4176 e->event.tv_usec = now.tv_usec;
4177 list_add_tail(&e->base.link,
4178 &e->base.file_priv->event_list);
4179 wake_up_interruptible(&e->base.file_priv->event_wait);
4180 }
4181
4182 spin_unlock_irqrestore(&dev->event_lock, flags);
4183
4184 obj_priv = to_intel_bo(work->pending_flip_obj);
4185
4186 /* Initial scanout buffer will have a 0 pending flip count */
4187 if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4188 atomic_dec_and_test(&obj_priv->pending_flip))
4189 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4190 schedule_work(&work->work);
4191 }
4192
4193 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4194 {
4195 drm_i915_private_t *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc =
4197 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4198 unsigned long flags;
4199
4200 spin_lock_irqsave(&dev->event_lock, flags);
4201 if (intel_crtc->unpin_work) {
4202 intel_crtc->unpin_work->pending = 1;
4203 } else {
4204 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4205 }
4206 spin_unlock_irqrestore(&dev->event_lock, flags);
4207 }
4208
4209 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4210 struct drm_framebuffer *fb,
4211 struct drm_pending_vblank_event *event)
4212 {
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_framebuffer *intel_fb;
4216 struct drm_i915_gem_object *obj_priv;
4217 struct drm_gem_object *obj;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 struct intel_unpin_work *work;
4220 unsigned long flags;
4221 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4222 int ret, pipesrc;
4223 RING_LOCALS;
4224
4225 work = kzalloc(sizeof *work, GFP_KERNEL);
4226 if (work == NULL)
4227 return -ENOMEM;
4228
4229 mutex_lock(&dev->struct_mutex);
4230
4231 work->event = event;
4232 work->dev = crtc->dev;
4233 intel_fb = to_intel_framebuffer(crtc->fb);
4234 work->old_fb_obj = intel_fb->obj;
4235 INIT_WORK(&work->work, intel_unpin_work_fn);
4236
4237 /* We borrow the event spin lock for protecting unpin_work */
4238 spin_lock_irqsave(&dev->event_lock, flags);
4239 if (intel_crtc->unpin_work) {
4240 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4241 spin_unlock_irqrestore(&dev->event_lock, flags);
4242 kfree(work);
4243 mutex_unlock(&dev->struct_mutex);
4244 return -EBUSY;
4245 }
4246 intel_crtc->unpin_work = work;
4247 spin_unlock_irqrestore(&dev->event_lock, flags);
4248
4249 intel_fb = to_intel_framebuffer(fb);
4250 obj = intel_fb->obj;
4251
4252 ret = intel_pin_and_fence_fb_obj(dev, obj);
4253 if (ret != 0) {
4254 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4255 to_intel_bo(obj));
4256 kfree(work);
4257 intel_crtc->unpin_work = NULL;
4258 mutex_unlock(&dev->struct_mutex);
4259 return ret;
4260 }
4261
4262 /* Reference the objects for the scheduled work. */
4263 drm_gem_object_reference(work->old_fb_obj);
4264 drm_gem_object_reference(obj);
4265
4266 crtc->fb = fb;
4267 i915_gem_object_flush_write_domain(obj);
4268 drm_vblank_get(dev, intel_crtc->pipe);
4269 obj_priv = to_intel_bo(obj);
4270 atomic_inc(&obj_priv->pending_flip);
4271 work->pending_flip_obj = obj;
4272
4273 BEGIN_LP_RING(4);
4274 OUT_RING(MI_DISPLAY_FLIP |
4275 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4276 OUT_RING(fb->pitch);
4277 if (IS_I965G(dev)) {
4278 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4279 pipesrc = I915_READ(pipesrc_reg);
4280 OUT_RING(pipesrc & 0x0fff0fff);
4281 } else {
4282 OUT_RING(obj_priv->gtt_offset);
4283 OUT_RING(MI_NOOP);
4284 }
4285 ADVANCE_LP_RING();
4286
4287 mutex_unlock(&dev->struct_mutex);
4288
4289 return 0;
4290 }
4291
4292 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4293 .dpms = intel_crtc_dpms,
4294 .mode_fixup = intel_crtc_mode_fixup,
4295 .mode_set = intel_crtc_mode_set,
4296 .mode_set_base = intel_pipe_set_base,
4297 .prepare = intel_crtc_prepare,
4298 .commit = intel_crtc_commit,
4299 .load_lut = intel_crtc_load_lut,
4300 };
4301
4302 static const struct drm_crtc_funcs intel_crtc_funcs = {
4303 .cursor_set = intel_crtc_cursor_set,
4304 .cursor_move = intel_crtc_cursor_move,
4305 .gamma_set = intel_crtc_gamma_set,
4306 .set_config = drm_crtc_helper_set_config,
4307 .destroy = intel_crtc_destroy,
4308 .page_flip = intel_crtc_page_flip,
4309 };
4310
4311
4312 static void intel_crtc_init(struct drm_device *dev, int pipe)
4313 {
4314 drm_i915_private_t *dev_priv = dev->dev_private;
4315 struct intel_crtc *intel_crtc;
4316 int i;
4317
4318 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4319 if (intel_crtc == NULL)
4320 return;
4321
4322 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4323
4324 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4325 intel_crtc->pipe = pipe;
4326 intel_crtc->plane = pipe;
4327 for (i = 0; i < 256; i++) {
4328 intel_crtc->lut_r[i] = i;
4329 intel_crtc->lut_g[i] = i;
4330 intel_crtc->lut_b[i] = i;
4331 }
4332
4333 /* Swap pipes & planes for FBC on pre-965 */
4334 intel_crtc->pipe = pipe;
4335 intel_crtc->plane = pipe;
4336 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4337 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4338 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4339 }
4340
4341 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4342 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4343 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4344 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4345
4346 intel_crtc->cursor_addr = 0;
4347 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4348 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4349
4350 intel_crtc->busy = false;
4351
4352 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4353 (unsigned long)intel_crtc);
4354 }
4355
4356 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4357 struct drm_file *file_priv)
4358 {
4359 drm_i915_private_t *dev_priv = dev->dev_private;
4360 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4361 struct drm_mode_object *drmmode_obj;
4362 struct intel_crtc *crtc;
4363
4364 if (!dev_priv) {
4365 DRM_ERROR("called with no initialization\n");
4366 return -EINVAL;
4367 }
4368
4369 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4370 DRM_MODE_OBJECT_CRTC);
4371
4372 if (!drmmode_obj) {
4373 DRM_ERROR("no such CRTC id\n");
4374 return -EINVAL;
4375 }
4376
4377 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4378 pipe_from_crtc_id->pipe = crtc->pipe;
4379
4380 return 0;
4381 }
4382
4383 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4384 {
4385 struct drm_crtc *crtc = NULL;
4386
4387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4389 if (intel_crtc->pipe == pipe)
4390 break;
4391 }
4392 return crtc;
4393 }
4394
4395 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4396 {
4397 int index_mask = 0;
4398 struct drm_connector *connector;
4399 int entry = 0;
4400
4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4402 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4403 if (type_mask & intel_encoder->clone_mask)
4404 index_mask |= (1 << entry);
4405 entry++;
4406 }
4407 return index_mask;
4408 }
4409
4410
4411 static void intel_setup_outputs(struct drm_device *dev)
4412 {
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct drm_connector *connector;
4415
4416 intel_crt_init(dev);
4417
4418 /* Set up integrated LVDS */
4419 if (IS_MOBILE(dev) && !IS_I830(dev))
4420 intel_lvds_init(dev);
4421
4422 if (HAS_PCH_SPLIT(dev)) {
4423 int found;
4424
4425 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4426 intel_dp_init(dev, DP_A);
4427
4428 if (I915_READ(HDMIB) & PORT_DETECTED) {
4429 /* check SDVOB */
4430 /* found = intel_sdvo_init(dev, HDMIB); */
4431 found = 0;
4432 if (!found)
4433 intel_hdmi_init(dev, HDMIB);
4434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4435 intel_dp_init(dev, PCH_DP_B);
4436 }
4437
4438 if (I915_READ(HDMIC) & PORT_DETECTED)
4439 intel_hdmi_init(dev, HDMIC);
4440
4441 if (I915_READ(HDMID) & PORT_DETECTED)
4442 intel_hdmi_init(dev, HDMID);
4443
4444 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4445 intel_dp_init(dev, PCH_DP_C);
4446
4447 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4448 intel_dp_init(dev, PCH_DP_D);
4449
4450 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4451 bool found = false;
4452
4453 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4454 DRM_DEBUG_KMS("probing SDVOB\n");
4455 found = intel_sdvo_init(dev, SDVOB);
4456 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4457 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4458 intel_hdmi_init(dev, SDVOB);
4459 }
4460
4461 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4462 DRM_DEBUG_KMS("probing DP_B\n");
4463 intel_dp_init(dev, DP_B);
4464 }
4465 }
4466
4467 /* Before G4X SDVOC doesn't have its own detect register */
4468
4469 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4470 DRM_DEBUG_KMS("probing SDVOC\n");
4471 found = intel_sdvo_init(dev, SDVOC);
4472 }
4473
4474 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4475
4476 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4477 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4478 intel_hdmi_init(dev, SDVOC);
4479 }
4480 if (SUPPORTS_INTEGRATED_DP(dev)) {
4481 DRM_DEBUG_KMS("probing DP_C\n");
4482 intel_dp_init(dev, DP_C);
4483 }
4484 }
4485
4486 if (SUPPORTS_INTEGRATED_DP(dev) &&
4487 (I915_READ(DP_D) & DP_DETECTED)) {
4488 DRM_DEBUG_KMS("probing DP_D\n");
4489 intel_dp_init(dev, DP_D);
4490 }
4491 } else if (IS_GEN2(dev))
4492 intel_dvo_init(dev);
4493
4494 if (SUPPORTS_TV(dev))
4495 intel_tv_init(dev);
4496
4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4498 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4499 struct drm_encoder *encoder = &intel_encoder->enc;
4500
4501 encoder->possible_crtcs = intel_encoder->crtc_mask;
4502 encoder->possible_clones = intel_connector_clones(dev,
4503 intel_encoder->clone_mask);
4504 }
4505 }
4506
4507 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4508 {
4509 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4510 struct drm_device *dev = fb->dev;
4511
4512 if (fb->fbdev)
4513 intelfb_remove(dev, fb);
4514
4515 drm_framebuffer_cleanup(fb);
4516 drm_gem_object_unreference_unlocked(intel_fb->obj);
4517
4518 kfree(intel_fb);
4519 }
4520
4521 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4522 struct drm_file *file_priv,
4523 unsigned int *handle)
4524 {
4525 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4526 struct drm_gem_object *object = intel_fb->obj;
4527
4528 return drm_gem_handle_create(file_priv, object, handle);
4529 }
4530
4531 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4532 .destroy = intel_user_framebuffer_destroy,
4533 .create_handle = intel_user_framebuffer_create_handle,
4534 };
4535
4536 int intel_framebuffer_create(struct drm_device *dev,
4537 struct drm_mode_fb_cmd *mode_cmd,
4538 struct drm_framebuffer **fb,
4539 struct drm_gem_object *obj)
4540 {
4541 struct intel_framebuffer *intel_fb;
4542 int ret;
4543
4544 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4545 if (!intel_fb)
4546 return -ENOMEM;
4547
4548 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4549 if (ret) {
4550 DRM_ERROR("framebuffer init failed %d\n", ret);
4551 return ret;
4552 }
4553
4554 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4555
4556 intel_fb->obj = obj;
4557
4558 *fb = &intel_fb->base;
4559
4560 return 0;
4561 }
4562
4563
4564 static struct drm_framebuffer *
4565 intel_user_framebuffer_create(struct drm_device *dev,
4566 struct drm_file *filp,
4567 struct drm_mode_fb_cmd *mode_cmd)
4568 {
4569 struct drm_gem_object *obj;
4570 struct drm_framebuffer *fb;
4571 int ret;
4572
4573 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4574 if (!obj)
4575 return NULL;
4576
4577 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4578 if (ret) {
4579 drm_gem_object_unreference_unlocked(obj);
4580 return NULL;
4581 }
4582
4583 return fb;
4584 }
4585
4586 static const struct drm_mode_config_funcs intel_mode_funcs = {
4587 .fb_create = intel_user_framebuffer_create,
4588 .fb_changed = intelfb_probe,
4589 };
4590
4591 static struct drm_gem_object *
4592 intel_alloc_power_context(struct drm_device *dev)
4593 {
4594 struct drm_gem_object *pwrctx;
4595 int ret;
4596
4597 pwrctx = drm_gem_object_alloc(dev, 4096);
4598 if (!pwrctx) {
4599 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4600 return NULL;
4601 }
4602
4603 mutex_lock(&dev->struct_mutex);
4604 ret = i915_gem_object_pin(pwrctx, 4096);
4605 if (ret) {
4606 DRM_ERROR("failed to pin power context: %d\n", ret);
4607 goto err_unref;
4608 }
4609
4610 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4611 if (ret) {
4612 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4613 goto err_unpin;
4614 }
4615 mutex_unlock(&dev->struct_mutex);
4616
4617 return pwrctx;
4618
4619 err_unpin:
4620 i915_gem_object_unpin(pwrctx);
4621 err_unref:
4622 drm_gem_object_unreference(pwrctx);
4623 mutex_unlock(&dev->struct_mutex);
4624 return NULL;
4625 }
4626
4627 void ironlake_enable_drps(struct drm_device *dev)
4628 {
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4631 u8 fmax, fmin, fstart, vstart;
4632 int i = 0;
4633
4634 /* 100ms RC evaluation intervals */
4635 I915_WRITE(RCUPEI, 100000);
4636 I915_WRITE(RCDNEI, 100000);
4637
4638 /* Set max/min thresholds to 90ms and 80ms respectively */
4639 I915_WRITE(RCBMAXAVG, 90000);
4640 I915_WRITE(RCBMINAVG, 80000);
4641
4642 I915_WRITE(MEMIHYST, 1);
4643
4644 /* Set up min, max, and cur for interrupt handling */
4645 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4646 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4647 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4648 MEMMODE_FSTART_SHIFT;
4649 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4650 PXVFREQ_PX_SHIFT;
4651
4652 dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4653 dev_priv->min_delay = fmin;
4654 dev_priv->cur_delay = fstart;
4655
4656 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4657
4658 /*
4659 * Interrupts will be enabled in ironlake_irq_postinstall
4660 */
4661
4662 I915_WRITE(VIDSTART, vstart);
4663 POSTING_READ(VIDSTART);
4664
4665 rgvmodectl |= MEMMODE_SWMODE_EN;
4666 I915_WRITE(MEMMODECTL, rgvmodectl);
4667
4668 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4669 if (i++ > 100) {
4670 DRM_ERROR("stuck trying to change perf mode\n");
4671 break;
4672 }
4673 msleep(1);
4674 }
4675 msleep(1);
4676
4677 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4678 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4679 I915_WRITE(MEMSWCTL, rgvswctl);
4680 POSTING_READ(MEMSWCTL);
4681
4682 rgvswctl |= MEMCTL_CMD_STS;
4683 I915_WRITE(MEMSWCTL, rgvswctl);
4684 }
4685
4686 void ironlake_disable_drps(struct drm_device *dev)
4687 {
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689 u32 rgvswctl;
4690 u8 fstart;
4691
4692 /* Ack interrupts, disable EFC interrupt */
4693 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4694 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4695 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4696 I915_WRITE(DEIIR, DE_PCU_EVENT);
4697 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4698
4699 /* Go back to the starting frequency */
4700 fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4701 MEMMODE_FSTART_SHIFT;
4702 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4703 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4704 I915_WRITE(MEMSWCTL, rgvswctl);
4705 msleep(1);
4706 rgvswctl |= MEMCTL_CMD_STS;
4707 I915_WRITE(MEMSWCTL, rgvswctl);
4708 msleep(1);
4709
4710 }
4711
4712 void intel_init_clock_gating(struct drm_device *dev)
4713 {
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715
4716 /*
4717 * Disable clock gating reported to work incorrectly according to the
4718 * specs, but enable as much else as we can.
4719 */
4720 if (HAS_PCH_SPLIT(dev)) {
4721 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
4722
4723 if (IS_IRONLAKE(dev)) {
4724 /* Required for FBC */
4725 dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
4726 /* Required for CxSR */
4727 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
4728
4729 I915_WRITE(PCH_3DCGDIS0,
4730 MARIUNIT_CLOCK_GATE_DISABLE |
4731 SVSMUNIT_CLOCK_GATE_DISABLE);
4732 }
4733
4734 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
4735 return;
4736 } else if (IS_G4X(dev)) {
4737 uint32_t dspclk_gate;
4738 I915_WRITE(RENCLK_GATE_D1, 0);
4739 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4740 GS_UNIT_CLOCK_GATE_DISABLE |
4741 CL_UNIT_CLOCK_GATE_DISABLE);
4742 I915_WRITE(RAMCLK_GATE_D, 0);
4743 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4744 OVRUNIT_CLOCK_GATE_DISABLE |
4745 OVCUNIT_CLOCK_GATE_DISABLE;
4746 if (IS_GM45(dev))
4747 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4748 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4749 } else if (IS_I965GM(dev)) {
4750 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4751 I915_WRITE(RENCLK_GATE_D2, 0);
4752 I915_WRITE(DSPCLK_GATE_D, 0);
4753 I915_WRITE(RAMCLK_GATE_D, 0);
4754 I915_WRITE16(DEUC, 0);
4755 } else if (IS_I965G(dev)) {
4756 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4757 I965_RCC_CLOCK_GATE_DISABLE |
4758 I965_RCPB_CLOCK_GATE_DISABLE |
4759 I965_ISC_CLOCK_GATE_DISABLE |
4760 I965_FBC_CLOCK_GATE_DISABLE);
4761 I915_WRITE(RENCLK_GATE_D2, 0);
4762 } else if (IS_I9XX(dev)) {
4763 u32 dstate = I915_READ(D_STATE);
4764
4765 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4766 DSTATE_DOT_CLOCK_GATING;
4767 I915_WRITE(D_STATE, dstate);
4768 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4769 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4770 } else if (IS_I830(dev)) {
4771 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4772 }
4773
4774 /*
4775 * GPU can automatically power down the render unit if given a page
4776 * to save state.
4777 */
4778 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4779 struct drm_i915_gem_object *obj_priv = NULL;
4780
4781 if (dev_priv->pwrctx) {
4782 obj_priv = to_intel_bo(dev_priv->pwrctx);
4783 } else {
4784 struct drm_gem_object *pwrctx;
4785
4786 pwrctx = intel_alloc_power_context(dev);
4787 if (pwrctx) {
4788 dev_priv->pwrctx = pwrctx;
4789 obj_priv = to_intel_bo(pwrctx);
4790 }
4791 }
4792
4793 if (obj_priv) {
4794 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4795 I915_WRITE(MCHBAR_RENDER_STANDBY,
4796 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4797 }
4798 }
4799 }
4800
4801 /* Set up chip specific display functions */
4802 static void intel_init_display(struct drm_device *dev)
4803 {
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805
4806 /* We always want a DPMS function */
4807 if (HAS_PCH_SPLIT(dev))
4808 dev_priv->display.dpms = ironlake_crtc_dpms;
4809 else
4810 dev_priv->display.dpms = i9xx_crtc_dpms;
4811
4812 /* Only mobile has FBC, leave pointers NULL for other chips */
4813 if (IS_MOBILE(dev)) {
4814 if (IS_GM45(dev)) {
4815 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4816 dev_priv->display.enable_fbc = g4x_enable_fbc;
4817 dev_priv->display.disable_fbc = g4x_disable_fbc;
4818 } else if (IS_I965GM(dev)) {
4819 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4820 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4821 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4822 }
4823 /* 855GM needs testing */
4824 }
4825
4826 /* Returns the core display clock speed */
4827 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4828 dev_priv->display.get_display_clock_speed =
4829 i945_get_display_clock_speed;
4830 else if (IS_I915G(dev))
4831 dev_priv->display.get_display_clock_speed =
4832 i915_get_display_clock_speed;
4833 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4834 dev_priv->display.get_display_clock_speed =
4835 i9xx_misc_get_display_clock_speed;
4836 else if (IS_I915GM(dev))
4837 dev_priv->display.get_display_clock_speed =
4838 i915gm_get_display_clock_speed;
4839 else if (IS_I865G(dev))
4840 dev_priv->display.get_display_clock_speed =
4841 i865_get_display_clock_speed;
4842 else if (IS_I85X(dev))
4843 dev_priv->display.get_display_clock_speed =
4844 i855_get_display_clock_speed;
4845 else /* 852, 830 */
4846 dev_priv->display.get_display_clock_speed =
4847 i830_get_display_clock_speed;
4848
4849 /* For FIFO watermark updates */
4850 if (HAS_PCH_SPLIT(dev))
4851 dev_priv->display.update_wm = NULL;
4852 else if (IS_G4X(dev))
4853 dev_priv->display.update_wm = g4x_update_wm;
4854 else if (IS_I965G(dev))
4855 dev_priv->display.update_wm = i965_update_wm;
4856 else if (IS_I9XX(dev)) {
4857 dev_priv->display.update_wm = i9xx_update_wm;
4858 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4859 } else if (IS_I85X(dev)) {
4860 dev_priv->display.update_wm = i9xx_update_wm;
4861 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4862 } else {
4863 dev_priv->display.update_wm = i830_update_wm;
4864 if (IS_845G(dev))
4865 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4866 else
4867 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4868 }
4869 }
4870
4871 void intel_modeset_init(struct drm_device *dev)
4872 {
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 int num_pipe;
4875 int i;
4876
4877 drm_mode_config_init(dev);
4878
4879 dev->mode_config.min_width = 0;
4880 dev->mode_config.min_height = 0;
4881
4882 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4883
4884 intel_init_display(dev);
4885
4886 if (IS_I965G(dev)) {
4887 dev->mode_config.max_width = 8192;
4888 dev->mode_config.max_height = 8192;
4889 } else if (IS_I9XX(dev)) {
4890 dev->mode_config.max_width = 4096;
4891 dev->mode_config.max_height = 4096;
4892 } else {
4893 dev->mode_config.max_width = 2048;
4894 dev->mode_config.max_height = 2048;
4895 }
4896
4897 /* set memory base */
4898 if (IS_I9XX(dev))
4899 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4900 else
4901 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4902
4903 if (IS_MOBILE(dev) || IS_I9XX(dev))
4904 num_pipe = 2;
4905 else
4906 num_pipe = 1;
4907 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4908 num_pipe, num_pipe > 1 ? "s" : "");
4909
4910 for (i = 0; i < num_pipe; i++) {
4911 intel_crtc_init(dev, i);
4912 }
4913
4914 intel_setup_outputs(dev);
4915
4916 intel_init_clock_gating(dev);
4917
4918 if (IS_IRONLAKE_M(dev))
4919 ironlake_enable_drps(dev);
4920
4921 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4922 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4923 (unsigned long)dev);
4924
4925 intel_setup_overlay(dev);
4926
4927 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4928 dev_priv->fsb_freq,
4929 dev_priv->mem_freq))
4930 DRM_INFO("failed to find known CxSR latency "
4931 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4932 dev_priv->fsb_freq, dev_priv->mem_freq);
4933 }
4934
4935 void intel_modeset_cleanup(struct drm_device *dev)
4936 {
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 struct drm_crtc *crtc;
4939 struct intel_crtc *intel_crtc;
4940
4941 mutex_lock(&dev->struct_mutex);
4942
4943 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4944 /* Skip inactive CRTCs */
4945 if (!crtc->fb)
4946 continue;
4947
4948 intel_crtc = to_intel_crtc(crtc);
4949 intel_increase_pllclock(crtc, false);
4950 del_timer_sync(&intel_crtc->idle_timer);
4951 }
4952
4953 del_timer_sync(&dev_priv->idle_timer);
4954
4955 if (dev_priv->display.disable_fbc)
4956 dev_priv->display.disable_fbc(dev);
4957
4958 if (dev_priv->pwrctx) {
4959 struct drm_i915_gem_object *obj_priv;
4960
4961 obj_priv = to_intel_bo(dev_priv->pwrctx);
4962 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4963 I915_READ(PWRCTXA);
4964 i915_gem_object_unpin(dev_priv->pwrctx);
4965 drm_gem_object_unreference(dev_priv->pwrctx);
4966 }
4967
4968 if (IS_IRONLAKE_M(dev))
4969 ironlake_disable_drps(dev);
4970
4971 mutex_unlock(&dev->struct_mutex);
4972
4973 drm_mode_config_cleanup(dev);
4974 }
4975
4976
4977 /* current intel driver doesn't take advantage of encoders
4978 always give back the encoder for the connector
4979 */
4980 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4981 {
4982 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
4983
4984 return &intel_encoder->enc;
4985 }
4986
4987 /*
4988 * set vga decode state - true == enable VGA decode
4989 */
4990 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4991 {
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 u16 gmch_ctrl;
4994
4995 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4996 if (state)
4997 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4998 else
4999 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
5000 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
5001 return 0;
5002 }
Linux with added FPC-III support