drivers/gpu/drm/radeon/r420.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "radeon_reg.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "atom.h"
  35 #include "r100d.h"
  36 #include "r420d.h"
  37 #include "r420_reg_safe.h"
  38
  39 static void r420_set_reg_safe(struct radeon_device *rdev)
  40 {
  41         rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
  42         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
  43 }
  44
  45 void r420_pipes_init(struct radeon_device *rdev)
  46 {
  47         unsigned tmp;
  48         unsigned gb_pipe_select;
  49         unsigned num_pipes;
  50
  51         /* GA_ENHANCE workaround TCL deadlock issue */
  52         WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |
  53                (1 << 2) | (1 << 3));
  54         /* add idle wait as per freedesktop.org bug 24041 */
  55         if (r100_gui_wait_for_idle(rdev)) {
  56                 printk(KERN_WARNING "Failed to wait GUI idle while "
  57                        "programming pipes. Bad things might happen.\n");
  58         }
  59         /* get max number of pipes */
  60         gb_pipe_select = RREG32(0x402C);
  61         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  62
  63         /* SE chips have 1 pipe */
  64         if ((rdev->pdev->device == 0x5e4c) ||
  65             (rdev->pdev->device == 0x5e4f))
  66                 num_pipes = 1;
  67
  68         rdev->num_gb_pipes = num_pipes;
  69         tmp = 0;
  70         switch (num_pipes) {
  71         default:
  72                 /* force to 1 pipe */
  73                 num_pipes = 1;
  74         case 1:
  75                 tmp = (0 << 1);
  76                 break;
  77         case 2:
  78                 tmp = (3 << 1);
  79                 break;
  80         case 3:
  81                 tmp = (6 << 1);
  82                 break;
  83         case 4:
  84                 tmp = (7 << 1);
  85                 break;
  86         }
  87         WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);
  88         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  89         tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
  90         WREG32(R300_GB_TILE_CONFIG, tmp);
  91         if (r100_gui_wait_for_idle(rdev)) {
  92                 printk(KERN_WARNING "Failed to wait GUI idle while "
  93                        "programming pipes. Bad things might happen.\n");
  94         }
  95
  96         tmp = RREG32(R300_DST_PIPE_CONFIG);
  97         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
  98
  99         WREG32(R300_RB2D_DSTCACHE_MODE,
 100                RREG32(R300_RB2D_DSTCACHE_MODE) |
 101                R300_DC_AUTOFLUSH_ENABLE |
 102                R300_DC_DC_DISABLE_IGNORE_PE);
 103
 104         if (r100_gui_wait_for_idle(rdev)) {
 105                 printk(KERN_WARNING "Failed to wait GUI idle while "
 106                        "programming pipes. Bad things might happen.\n");
 107         }
 108
 109         if (rdev->family == CHIP_RV530) {
 110                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
 111                 if ((tmp & 3) == 3)
 112                         rdev->num_z_pipes = 2;
 113                 else
 114                         rdev->num_z_pipes = 1;
 115         } else
 116                 rdev->num_z_pipes = 1;
 117
 118         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
 119                  rdev->num_gb_pipes, rdev->num_z_pipes);
 120 }
 121
 122 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
 123 {
 124         u32 r;
 125
 126         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
 127         r = RREG32(R_0001FC_MC_IND_DATA);
 128         return r;
 129 }
 130
 131 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 132 {
 133         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
 134                 S_0001F8_MC_IND_WR_EN(1));
 135         WREG32(R_0001FC_MC_IND_DATA, v);
 136 }
 137
 138 static void r420_debugfs(struct radeon_device *rdev)
 139 {
 140         if (r100_debugfs_rbbm_init(rdev)) {
 141                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
 142         }
 143         if (r420_debugfs_pipes_info_init(rdev)) {
 144                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
 145         }
 146 }
 147
 148 static void r420_clock_resume(struct radeon_device *rdev)
 149 {
 150         u32 sclk_cntl;
 151
 152         if (radeon_dynclks != -1 && radeon_dynclks)
 153                 radeon_atom_set_clock_gating(rdev, 1);
 154         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
 155         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
 156         if (rdev->family == CHIP_R420)
 157                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
 158         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
 159 }
 160
 161 static void r420_cp_errata_init(struct radeon_device *rdev)
 162 {
 163         /* RV410 and R420 can lock up if CP DMA to host memory happens
 164          * while the 2D engine is busy.
 165          *
 166          * The proper workaround is to queue a RESYNC at the beginning
 167          * of the CP init, apparently.
 168          */
 169         radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
 170         radeon_ring_lock(rdev, 8);
 171         radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
 172         radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
 173         radeon_ring_write(rdev, 0xDEADBEEF);
 174         radeon_ring_unlock_commit(rdev);
 175 }
 176
 177 static void r420_cp_errata_fini(struct radeon_device *rdev)
 178 {
 179         /* Catch the RESYNC we dispatched all the way back,
 180          * at the very beginning of the CP init.
 181          */
 182         radeon_ring_lock(rdev, 8);
 183         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 184         radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
 185         radeon_ring_unlock_commit(rdev);
 186         radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
 187 }
 188
 189 static int r420_startup(struct radeon_device *rdev)
 190 {
 191         int r;
 192
 193         /* set common regs */
 194         r100_set_common_regs(rdev);
 195         /* program mc */
 196         r300_mc_program(rdev);
 197         /* Resume clock */
 198         r420_clock_resume(rdev);
 199         /* Initialize GART (initialize after TTM so we can allocate
 200          * memory through TTM but finalize after TTM) */
 201         if (rdev->flags & RADEON_IS_PCIE) {
 202                 r = rv370_pcie_gart_enable(rdev);
 203                 if (r)
 204                         return r;
 205         }
 206         if (rdev->flags & RADEON_IS_PCI) {
 207                 r = r100_pci_gart_enable(rdev);
 208                 if (r)
 209                         return r;
 210         }
 211         r420_pipes_init(rdev);
 212         /* Enable IRQ */
 213         r100_irq_set(rdev);
 214         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 215         /* 1M ring buffer */
 216         r = r100_cp_init(rdev, 1024 * 1024);
 217         if (r) {
 218                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
 219                 return r;
 220         }
 221         r420_cp_errata_init(rdev);
 222         r = r100_wb_init(rdev);
 223         if (r) {
 224                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
 225         }
 226         r = r100_ib_init(rdev);
 227         if (r) {
 228                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
 229                 return r;
 230         }
 231         return 0;
 232 }
 233
 234 int r420_resume(struct radeon_device *rdev)
 235 {
 236         /* Make sur GART are not working */
 237         if (rdev->flags & RADEON_IS_PCIE)
 238                 rv370_pcie_gart_disable(rdev);
 239         if (rdev->flags & RADEON_IS_PCI)
 240                 r100_pci_gart_disable(rdev);
 241         /* Resume clock before doing reset */
 242         r420_clock_resume(rdev);
 243         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 244         if (radeon_gpu_reset(rdev)) {
 245                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 246                         RREG32(R_000E40_RBBM_STATUS),
 247                         RREG32(R_0007C0_CP_STAT));
 248         }
 249         /* check if cards are posted or not */
 250         if (rdev->is_atom_bios) {
 251                 atom_asic_init(rdev->mode_info.atom_context);
 252         } else {
 253                 radeon_combios_asic_init(rdev->ddev);
 254         }
 255         /* Resume clock after posting */
 256         r420_clock_resume(rdev);
 257         /* Initialize surface registers */
 258         radeon_surface_init(rdev);
 259         return r420_startup(rdev);
 260 }
 261
 262 int r420_suspend(struct radeon_device *rdev)
 263 {
 264         r420_cp_errata_fini(rdev);
 265         r100_cp_disable(rdev);
 266         r100_wb_disable(rdev);
 267         r100_irq_disable(rdev);
 268         if (rdev->flags & RADEON_IS_PCIE)
 269                 rv370_pcie_gart_disable(rdev);
 270         if (rdev->flags & RADEON_IS_PCI)
 271                 r100_pci_gart_disable(rdev);
 272         return 0;
 273 }
 274
 275 void r420_fini(struct radeon_device *rdev)
 276 {
 277         radeon_pm_fini(rdev);
 278         r100_cp_fini(rdev);
 279         r100_wb_fini(rdev);
 280         r100_ib_fini(rdev);
 281         radeon_gem_fini(rdev);
 282         if (rdev->flags & RADEON_IS_PCIE)
 283                 rv370_pcie_gart_fini(rdev);
 284         if (rdev->flags & RADEON_IS_PCI)
 285                 r100_pci_gart_fini(rdev);
 286         radeon_agp_fini(rdev);
 287         radeon_irq_kms_fini(rdev);
 288         radeon_fence_driver_fini(rdev);
 289         radeon_bo_fini(rdev);
 290         if (rdev->is_atom_bios) {
 291                 radeon_atombios_fini(rdev);
 292         } else {
 293                 radeon_combios_fini(rdev);
 294         }
 295         kfree(rdev->bios);
 296         rdev->bios = NULL;
 297 }
 298
 299 int r420_init(struct radeon_device *rdev)
 300 {
 301         int r;
 302
 303         /* Initialize scratch registers */
 304         radeon_scratch_init(rdev);
 305         /* Initialize surface registers */
 306         radeon_surface_init(rdev);
 307         /* TODO: disable VGA need to use VGA request */
 308         /* BIOS*/
 309         if (!radeon_get_bios(rdev)) {
 310                 if (ASIC_IS_AVIVO(rdev))
 311                         return -EINVAL;
 312         }
 313         if (rdev->is_atom_bios) {
 314                 r = radeon_atombios_init(rdev);
 315                 if (r) {
 316                         return r;
 317                 }
 318         } else {
 319                 r = radeon_combios_init(rdev);
 320                 if (r) {
 321                         return r;
 322                 }
 323         }
 324         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 325         if (radeon_gpu_reset(rdev)) {
 326                 dev_warn(rdev->dev,
 327                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 328                         RREG32(R_000E40_RBBM_STATUS),
 329                         RREG32(R_0007C0_CP_STAT));
 330         }
 331         /* check if cards are posted or not */
 332         if (radeon_boot_test_post_card(rdev) == false)
 333                 return -EINVAL;
 334
 335         /* Initialize clocks */
 336         radeon_get_clock_info(rdev->ddev);
 337         /* Initialize power management */
 338         radeon_pm_init(rdev);
 339         /* initialize AGP */
 340         if (rdev->flags & RADEON_IS_AGP) {
 341                 r = radeon_agp_init(rdev);
 342                 if (r) {
 343                         radeon_agp_disable(rdev);
 344                 }
 345         }
 346         /* initialize memory controller */
 347         r300_mc_init(rdev);
 348         r420_debugfs(rdev);
 349         /* Fence driver */
 350         r = radeon_fence_driver_init(rdev);
 351         if (r) {
 352                 return r;
 353         }
 354         r = radeon_irq_kms_init(rdev);
 355         if (r) {
 356                 return r;
 357         }
 358         /* Memory manager */
 359         r = radeon_bo_init(rdev);
 360         if (r) {
 361                 return r;
 362         }
 363         if (rdev->family == CHIP_R420)
 364                 r100_enable_bm(rdev);
 365
 366         if (rdev->flags & RADEON_IS_PCIE) {
 367                 r = rv370_pcie_gart_init(rdev);
 368                 if (r)
 369                         return r;
 370         }
 371         if (rdev->flags & RADEON_IS_PCI) {
 372                 r = r100_pci_gart_init(rdev);
 373                 if (r)
 374                         return r;
 375         }
 376         r420_set_reg_safe(rdev);
 377         rdev->accel_working = true;
 378         r = r420_startup(rdev);
 379         if (r) {
 380                 /* Somethings want wront with the accel init stop accel */
 381                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 382                 r100_cp_fini(rdev);
 383                 r100_wb_fini(rdev);
 384                 r100_ib_fini(rdev);
 385                 radeon_irq_kms_fini(rdev);
 386                 if (rdev->flags & RADEON_IS_PCIE)
 387                         rv370_pcie_gart_fini(rdev);
 388                 if (rdev->flags & RADEON_IS_PCI)
 389                         r100_pci_gart_fini(rdev);
 390                 radeon_agp_fini(rdev);
 391                 rdev->accel_working = false;
 392         }
 393         return 0;
 394 }
 395
 396 /*
 397  * Debugfs info
 398  */
 399 #if defined(CONFIG_DEBUG_FS)
 400 static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
 401 {
 402         struct drm_info_node *node = (struct drm_info_node *) m->private;
 403         struct drm_device *dev = node->minor->dev;
 404         struct radeon_device *rdev = dev->dev_private;
 405         uint32_t tmp;
 406
 407         tmp = RREG32(R400_GB_PIPE_SELECT);
 408         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 409         tmp = RREG32(R300_GB_TILE_CONFIG);
 410         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 411         tmp = RREG32(R300_DST_PIPE_CONFIG);
 412         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 413         return 0;
 414 }
 415
 416 static struct drm_info_list r420_pipes_info_list[] = {
 417         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
 418 };
 419 #endif
 420
 421 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
 422 {
 423 #if defined(CONFIG_DEBUG_FS)
 424         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
 425 #else
 426         return 0;
 427 #endif
 428 }