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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / gpu / drm / radeon / r600_cs.c
blobc39c1bc13016075f2bd7151937b3faadc2bf0143
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "r600d.h"
31 #include "r600_reg_safe.h"
32
33 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
34 struct radeon_cs_reloc **cs_reloc);
35 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36 struct radeon_cs_reloc **cs_reloc);
37 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
38 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
39 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
40
41
42 struct r600_cs_track {
43 /* configuration we miror so that we use same code btw kms/ums */
44 u32 group_size;
45 u32 nbanks;
46 u32 npipes;
47 /* value we track */
48 u32 sq_config;
49 u32 nsamples;
50 u32 cb_color_base_last[8];
51 struct radeon_bo *cb_color_bo[8];
52 u32 cb_color_bo_offset[8];
53 struct radeon_bo *cb_color_frag_bo[8];
54 struct radeon_bo *cb_color_tile_bo[8];
55 u32 cb_color_info[8];
56 u32 cb_color_size_idx[8];
57 u32 cb_target_mask;
58 u32 cb_shader_mask;
59 u32 cb_color_size[8];
60 u32 vgt_strmout_en;
61 u32 vgt_strmout_buffer_en;
62 u32 db_depth_control;
63 u32 db_depth_info;
64 u32 db_depth_size_idx;
65 u32 db_depth_view;
66 u32 db_depth_size;
67 u32 db_offset;
68 struct radeon_bo *db_bo;
69 };
70
71 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
72 {
73 switch (format) {
74 case V_038004_COLOR_8:
75 case V_038004_COLOR_4_4:
76 case V_038004_COLOR_3_3_2:
77 case V_038004_FMT_1:
78 *bpe = 1;
79 break;
80 case V_038004_COLOR_16:
81 case V_038004_COLOR_16_FLOAT:
82 case V_038004_COLOR_8_8:
83 case V_038004_COLOR_5_6_5:
84 case V_038004_COLOR_6_5_5:
85 case V_038004_COLOR_1_5_5_5:
86 case V_038004_COLOR_4_4_4_4:
87 case V_038004_COLOR_5_5_5_1:
88 *bpe = 2;
89 break;
90 case V_038004_FMT_8_8_8:
91 *bpe = 3;
92 break;
93 case V_038004_COLOR_32:
94 case V_038004_COLOR_32_FLOAT:
95 case V_038004_COLOR_16_16:
96 case V_038004_COLOR_16_16_FLOAT:
97 case V_038004_COLOR_8_24:
98 case V_038004_COLOR_8_24_FLOAT:
99 case V_038004_COLOR_24_8:
100 case V_038004_COLOR_24_8_FLOAT:
101 case V_038004_COLOR_10_11_11:
102 case V_038004_COLOR_10_11_11_FLOAT:
103 case V_038004_COLOR_11_11_10:
104 case V_038004_COLOR_11_11_10_FLOAT:
105 case V_038004_COLOR_2_10_10_10:
106 case V_038004_COLOR_8_8_8_8:
107 case V_038004_COLOR_10_10_10_2:
108 case V_038004_FMT_5_9_9_9_SHAREDEXP:
109 case V_038004_FMT_32_AS_8:
110 case V_038004_FMT_32_AS_8_8:
111 *bpe = 4;
112 break;
113 case V_038004_COLOR_X24_8_32_FLOAT:
114 case V_038004_COLOR_32_32:
115 case V_038004_COLOR_32_32_FLOAT:
116 case V_038004_COLOR_16_16_16_16:
117 case V_038004_COLOR_16_16_16_16_FLOAT:
118 *bpe = 8;
119 break;
120 case V_038004_FMT_16_16_16:
121 case V_038004_FMT_16_16_16_FLOAT:
122 *bpe = 6;
123 break;
124 case V_038004_FMT_32_32_32:
125 case V_038004_FMT_32_32_32_FLOAT:
126 *bpe = 12;
127 break;
128 case V_038004_COLOR_32_32_32_32:
129 case V_038004_COLOR_32_32_32_32_FLOAT:
130 *bpe = 16;
131 break;
132 case V_038004_FMT_GB_GR:
133 case V_038004_FMT_BG_RG:
134 case V_038004_COLOR_INVALID:
135 *bpe = 16;
136 return -EINVAL;
137 }
138 return 0;
139 }
140
141 static void r600_cs_track_init(struct r600_cs_track *track)
142 {
143 int i;
144
145 /* assume DX9 mode */
146 track->sq_config = DX9_CONSTS;
147 for (i = 0; i < 8; i++) {
148 track->cb_color_base_last[i] = 0;
149 track->cb_color_size[i] = 0;
150 track->cb_color_size_idx[i] = 0;
151 track->cb_color_info[i] = 0;
152 track->cb_color_bo[i] = NULL;
153 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
154 }
155 track->cb_target_mask = 0xFFFFFFFF;
156 track->cb_shader_mask = 0xFFFFFFFF;
157 track->db_bo = NULL;
158 /* assume the biggest format and that htile is enabled */
159 track->db_depth_info = 7 | (1 << 25);
160 track->db_depth_view = 0xFFFFC000;
161 track->db_depth_size = 0xFFFFFFFF;
162 track->db_depth_size_idx = 0;
163 track->db_depth_control = 0xFFFFFFFF;
164 }
165
166 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
167 {
168 struct r600_cs_track *track = p->track;
169 u32 bpe = 0, pitch, slice_tile_max, size, tmp, height;
170 volatile u32 *ib = p->ib->ptr;
171
172 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
173 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
174 return -EINVAL;
175 }
176 size = radeon_bo_size(track->cb_color_bo[i]);
177 if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) {
178 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
179 __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]),
180 i, track->cb_color_info[i]);
181 return -EINVAL;
182 }
183 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
184 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
185 if (!pitch) {
186 dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid (0x%08X)\n",
187 __func__, __LINE__, pitch, i, track->cb_color_size[i]);
188 return -EINVAL;
189 }
190 height = size / (pitch * bpe);
191 if (height > 8192)
192 height = 8192;
193 switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
194 case V_0280A0_ARRAY_LINEAR_GENERAL:
195 case V_0280A0_ARRAY_LINEAR_ALIGNED:
196 if (pitch & 0x3f) {
197 dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) invalid\n",
198 __func__, __LINE__, pitch, bpe, pitch * bpe);
199 return -EINVAL;
200 }
201 if ((pitch * bpe) & (track->group_size - 1)) {
202 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
203 __func__, __LINE__, pitch);
204 return -EINVAL;
205 }
206 break;
207 case V_0280A0_ARRAY_1D_TILED_THIN1:
208 if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 1)) {
209 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
210 __func__, __LINE__, pitch);
211 return -EINVAL;
212 }
213 height &= ~0x7;
214 if (!height)
215 height = 8;
216 break;
217 case V_0280A0_ARRAY_2D_TILED_THIN1:
218 if (pitch & ((8 * track->nbanks) - 1)) {
219 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
220 __func__, __LINE__, pitch);
221 return -EINVAL;
222 }
223 tmp = pitch * 8 * bpe * track->nsamples;
224 tmp = tmp / track->nbanks;
225 if (tmp & (track->group_size - 1)) {
226 dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
227 __func__, __LINE__, pitch);
228 return -EINVAL;
229 }
230 height &= ~((16 * track->npipes) - 1);
231 if (!height)
232 height = 16 * track->npipes;
233 break;
234 default:
235 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
236 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
237 track->cb_color_info[i]);
238 return -EINVAL;
239 }
240 /* check offset */
241 tmp = height * pitch;
242 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
243 dev_warn(p->dev, "%s offset[%d] %d to big\n", __func__, i, track->cb_color_bo_offset[i]);
244 return -EINVAL;
245 }
246 /* limit max tile */
247 tmp = (height * pitch) >> 6;
248 if (tmp < slice_tile_max)
249 slice_tile_max = tmp;
250 tmp = S_028060_PITCH_TILE_MAX((pitch >> 3) - 1) |
251 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
252 ib[track->cb_color_size_idx[i]] = tmp;
253 return 0;
254 }
255
256 static int r600_cs_track_check(struct radeon_cs_parser *p)
257 {
258 struct r600_cs_track *track = p->track;
259 u32 tmp;
260 int r, i;
261 volatile u32 *ib = p->ib->ptr;
262
263 /* on legacy kernel we don't perform advanced check */
264 if (p->rdev == NULL)
265 return 0;
266 /* we don't support out buffer yet */
267 if (track->vgt_strmout_en || track->vgt_strmout_buffer_en) {
268 dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n");
269 return -EINVAL;
270 }
271 /* check that we have a cb for each enabled target, we don't check
272 * shader_mask because it seems mesa isn't always setting it :(
273 */
274 tmp = track->cb_target_mask;
275 for (i = 0; i < 8; i++) {
276 if ((tmp >> (i * 4)) & 0xF) {
277 /* at least one component is enabled */
278 if (track->cb_color_bo[i] == NULL) {
279 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
280 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
281 return -EINVAL;
282 }
283 /* perform rewrite of CB_COLOR[0-7]_SIZE */
284 r = r600_cs_track_validate_cb(p, i);
285 if (r)
286 return r;
287 }
288 }
289 /* Check depth buffer */
290 if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
291 G_028800_Z_ENABLE(track->db_depth_control)) {
292 u32 nviews, bpe, ntiles;
293 if (track->db_bo == NULL) {
294 dev_warn(p->dev, "z/stencil with no depth buffer\n");
295 return -EINVAL;
296 }
297 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
298 dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n");
299 return -EINVAL;
300 }
301 switch (G_028010_FORMAT(track->db_depth_info)) {
302 case V_028010_DEPTH_16:
303 bpe = 2;
304 break;
305 case V_028010_DEPTH_X8_24:
306 case V_028010_DEPTH_8_24:
307 case V_028010_DEPTH_X8_24_FLOAT:
308 case V_028010_DEPTH_8_24_FLOAT:
309 case V_028010_DEPTH_32_FLOAT:
310 bpe = 4;
311 break;
312 case V_028010_DEPTH_X24_8_32_FLOAT:
313 bpe = 8;
314 break;
315 default:
316 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
317 return -EINVAL;
318 }
319 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
320 if (!track->db_depth_size_idx) {
321 dev_warn(p->dev, "z/stencil buffer size not set\n");
322 return -EINVAL;
323 }
324 printk_once(KERN_WARNING "You have old & broken userspace please consider updating mesa\n");
325 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
326 tmp = (tmp / bpe) >> 6;
327 if (!tmp) {
328 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
329 track->db_depth_size, bpe, track->db_offset,
330 radeon_bo_size(track->db_bo));
331 return -EINVAL;
332 }
333 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
334 } else {
335 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
336 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
337 tmp = ntiles * bpe * 64 * nviews;
338 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
339 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
340 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
341 radeon_bo_size(track->db_bo));
342 return -EINVAL;
343 }
344 }
345 }
346 return 0;
347 }
348
349 /**
350 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
351 * @parser: parser structure holding parsing context.
352 * @pkt: where to store packet informations
353 *
354 * Assume that chunk_ib_index is properly set. Will return -EINVAL
355 * if packet is bigger than remaining ib size. or if packets is unknown.
356 **/
357 int r600_cs_packet_parse(struct radeon_cs_parser *p,
358 struct radeon_cs_packet *pkt,
359 unsigned idx)
360 {
361 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
362 uint32_t header;
363
364 if (idx >= ib_chunk->length_dw) {
365 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
366 idx, ib_chunk->length_dw);
367 return -EINVAL;
368 }
369 header = radeon_get_ib_value(p, idx);
370 pkt->idx = idx;
371 pkt->type = CP_PACKET_GET_TYPE(header);
372 pkt->count = CP_PACKET_GET_COUNT(header);
373 pkt->one_reg_wr = 0;
374 switch (pkt->type) {
375 case PACKET_TYPE0:
376 pkt->reg = CP_PACKET0_GET_REG(header);
377 break;
378 case PACKET_TYPE3:
379 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
380 break;
381 case PACKET_TYPE2:
382 pkt->count = -1;
383 break;
384 default:
385 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
386 return -EINVAL;
387 }
388 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
389 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
390 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
391 return -EINVAL;
392 }
393 return 0;
394 }
395
396 /**
397 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
398 * @parser: parser structure holding parsing context.
399 * @data: pointer to relocation data
400 * @offset_start: starting offset
401 * @offset_mask: offset mask (to align start offset on)
402 * @reloc: reloc informations
403 *
404 * Check next packet is relocation packet3, do bo validation and compute
405 * GPU offset using the provided start.
406 **/
407 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
408 struct radeon_cs_reloc **cs_reloc)
409 {
410 struct radeon_cs_chunk *relocs_chunk;
411 struct radeon_cs_packet p3reloc;
412 unsigned idx;
413 int r;
414
415 if (p->chunk_relocs_idx == -1) {
416 DRM_ERROR("No relocation chunk !\n");
417 return -EINVAL;
418 }
419 *cs_reloc = NULL;
420 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
421 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
422 if (r) {
423 return r;
424 }
425 p->idx += p3reloc.count + 2;
426 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
427 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
428 p3reloc.idx);
429 return -EINVAL;
430 }
431 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
432 if (idx >= relocs_chunk->length_dw) {
433 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
434 idx, relocs_chunk->length_dw);
435 return -EINVAL;
436 }
437 /* FIXME: we assume reloc size is 4 dwords */
438 *cs_reloc = p->relocs_ptr[(idx / 4)];
439 return 0;
440 }
441
442 /**
443 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
444 * @parser: parser structure holding parsing context.
445 * @data: pointer to relocation data
446 * @offset_start: starting offset
447 * @offset_mask: offset mask (to align start offset on)
448 * @reloc: reloc informations
449 *
450 * Check next packet is relocation packet3, do bo validation and compute
451 * GPU offset using the provided start.
452 **/
453 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
454 struct radeon_cs_reloc **cs_reloc)
455 {
456 struct radeon_cs_chunk *relocs_chunk;
457 struct radeon_cs_packet p3reloc;
458 unsigned idx;
459 int r;
460
461 if (p->chunk_relocs_idx == -1) {
462 DRM_ERROR("No relocation chunk !\n");
463 return -EINVAL;
464 }
465 *cs_reloc = NULL;
466 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
467 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
468 if (r) {
469 return r;
470 }
471 p->idx += p3reloc.count + 2;
472 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
473 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
474 p3reloc.idx);
475 return -EINVAL;
476 }
477 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
478 if (idx >= relocs_chunk->length_dw) {
479 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
480 idx, relocs_chunk->length_dw);
481 return -EINVAL;
482 }
483 *cs_reloc = p->relocs;
484 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
485 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
486 return 0;
487 }
488
489 /**
490 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
491 * @parser: parser structure holding parsing context.
492 *
493 * Check next packet is relocation packet3, do bo validation and compute
494 * GPU offset using the provided start.
495 **/
496 static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
497 {
498 struct radeon_cs_packet p3reloc;
499 int r;
500
501 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
502 if (r) {
503 return 0;
504 }
505 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
506 return 0;
507 }
508 return 1;
509 }
510
511 /**
512 * r600_cs_packet_next_vline() - parse userspace VLINE packet
513 * @parser: parser structure holding parsing context.
514 *
515 * Userspace sends a special sequence for VLINE waits.
516 * PACKET0 - VLINE_START_END + value
517 * PACKET3 - WAIT_REG_MEM poll vline status reg
518 * RELOC (P3) - crtc_id in reloc.
519 *
520 * This function parses this and relocates the VLINE START END
521 * and WAIT_REG_MEM packets to the correct crtc.
522 * It also detects a switched off crtc and nulls out the
523 * wait in that case.
524 */
525 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
526 {
527 struct drm_mode_object *obj;
528 struct drm_crtc *crtc;
529 struct radeon_crtc *radeon_crtc;
530 struct radeon_cs_packet p3reloc, wait_reg_mem;
531 int crtc_id;
532 int r;
533 uint32_t header, h_idx, reg, wait_reg_mem_info;
534 volatile uint32_t *ib;
535
536 ib = p->ib->ptr;
537
538 /* parse the WAIT_REG_MEM */
539 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
540 if (r)
541 return r;
542
543 /* check its a WAIT_REG_MEM */
544 if (wait_reg_mem.type != PACKET_TYPE3 ||
545 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
546 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
547 r = -EINVAL;
548 return r;
549 }
550
551 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
552 /* bit 4 is reg (0) or mem (1) */
553 if (wait_reg_mem_info & 0x10) {
554 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
555 r = -EINVAL;
556 return r;
557 }
558 /* waiting for value to be equal */
559 if ((wait_reg_mem_info & 0x7) != 0x3) {
560 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
561 r = -EINVAL;
562 return r;
563 }
564 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
565 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
566 r = -EINVAL;
567 return r;
568 }
569
570 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
571 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
572 r = -EINVAL;
573 return r;
574 }
575
576 /* jump over the NOP */
577 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
578 if (r)
579 return r;
580
581 h_idx = p->idx - 2;
582 p->idx += wait_reg_mem.count + 2;
583 p->idx += p3reloc.count + 2;
584
585 header = radeon_get_ib_value(p, h_idx);
586 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
587 reg = CP_PACKET0_GET_REG(header);
588 mutex_lock(&p->rdev->ddev->mode_config.mutex);
589 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
590 if (!obj) {
591 DRM_ERROR("cannot find crtc %d\n", crtc_id);
592 r = -EINVAL;
593 goto out;
594 }
595 crtc = obj_to_crtc(obj);
596 radeon_crtc = to_radeon_crtc(crtc);
597 crtc_id = radeon_crtc->crtc_id;
598
599 if (!crtc->enabled) {
600 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
601 ib[h_idx + 2] = PACKET2(0);
602 ib[h_idx + 3] = PACKET2(0);
603 ib[h_idx + 4] = PACKET2(0);
604 ib[h_idx + 5] = PACKET2(0);
605 ib[h_idx + 6] = PACKET2(0);
606 ib[h_idx + 7] = PACKET2(0);
607 ib[h_idx + 8] = PACKET2(0);
608 } else if (crtc_id == 1) {
609 switch (reg) {
610 case AVIVO_D1MODE_VLINE_START_END:
611 header &= ~R600_CP_PACKET0_REG_MASK;
612 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
613 break;
614 default:
615 DRM_ERROR("unknown crtc reloc\n");
616 r = -EINVAL;
617 goto out;
618 }
619 ib[h_idx] = header;
620 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
621 }
622 out:
623 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
624 return r;
625 }
626
627 static int r600_packet0_check(struct radeon_cs_parser *p,
628 struct radeon_cs_packet *pkt,
629 unsigned idx, unsigned reg)
630 {
631 int r;
632
633 switch (reg) {
634 case AVIVO_D1MODE_VLINE_START_END:
635 r = r600_cs_packet_parse_vline(p);
636 if (r) {
637 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
638 idx, reg);
639 return r;
640 }
641 break;
642 default:
643 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
644 reg, idx);
645 return -EINVAL;
646 }
647 return 0;
648 }
649
650 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
651 struct radeon_cs_packet *pkt)
652 {
653 unsigned reg, i;
654 unsigned idx;
655 int r;
656
657 idx = pkt->idx + 1;
658 reg = pkt->reg;
659 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
660 r = r600_packet0_check(p, pkt, idx, reg);
661 if (r) {
662 return r;
663 }
664 }
665 return 0;
666 }
667
668 /**
669 * r600_cs_check_reg() - check if register is authorized or not
670 * @parser: parser structure holding parsing context
671 * @reg: register we are testing
672 * @idx: index into the cs buffer
673 *
674 * This function will test against r600_reg_safe_bm and return 0
675 * if register is safe. If register is not flag as safe this function
676 * will test it against a list of register needind special handling.
677 */
678 static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
679 {
680 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
681 struct radeon_cs_reloc *reloc;
682 u32 last_reg = ARRAY_SIZE(r600_reg_safe_bm);
683 u32 m, i, tmp, *ib;
684 int r;
685
686 i = (reg >> 7);
687 if (i > last_reg) {
688 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
689 return -EINVAL;
690 }
691 m = 1 << ((reg >> 2) & 31);
692 if (!(r600_reg_safe_bm[i] & m))
693 return 0;
694 ib = p->ib->ptr;
695 switch (reg) {
696 /* force following reg to 0 in an attemp to disable out buffer
697 * which will need us to better understand how it works to perform
698 * security check on it (Jerome)
699 */
700 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
701 case R_008C44_SQ_ESGS_RING_SIZE:
702 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
703 case R_008C54_SQ_ESTMP_RING_SIZE:
704 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
705 case R_008C74_SQ_FBUF_RING_SIZE:
706 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
707 case R_008C5C_SQ_GSTMP_RING_SIZE:
708 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
709 case R_008C4C_SQ_GSVS_RING_SIZE:
710 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
711 case R_008C6C_SQ_PSTMP_RING_SIZE:
712 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
713 case R_008C7C_SQ_REDUC_RING_SIZE:
714 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
715 case R_008C64_SQ_VSTMP_RING_SIZE:
716 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
717 /* get value to populate the IB don't remove */
718 tmp =radeon_get_ib_value(p, idx);
719 ib[idx] = 0;
720 break;
721 case SQ_CONFIG:
722 track->sq_config = radeon_get_ib_value(p, idx);
723 break;
724 case R_028800_DB_DEPTH_CONTROL:
725 track->db_depth_control = radeon_get_ib_value(p, idx);
726 break;
727 case R_028010_DB_DEPTH_INFO:
728 track->db_depth_info = radeon_get_ib_value(p, idx);
729 break;
730 case R_028004_DB_DEPTH_VIEW:
731 track->db_depth_view = radeon_get_ib_value(p, idx);
732 break;
733 case R_028000_DB_DEPTH_SIZE:
734 track->db_depth_size = radeon_get_ib_value(p, idx);
735 track->db_depth_size_idx = idx;
736 break;
737 case R_028AB0_VGT_STRMOUT_EN:
738 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
739 break;
740 case R_028B20_VGT_STRMOUT_BUFFER_EN:
741 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
742 break;
743 case R_028238_CB_TARGET_MASK:
744 track->cb_target_mask = radeon_get_ib_value(p, idx);
745 break;
746 case R_02823C_CB_SHADER_MASK:
747 track->cb_shader_mask = radeon_get_ib_value(p, idx);
748 break;
749 case R_028C04_PA_SC_AA_CONFIG:
750 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
751 track->nsamples = 1 << tmp;
752 break;
753 case R_0280A0_CB_COLOR0_INFO:
754 case R_0280A4_CB_COLOR1_INFO:
755 case R_0280A8_CB_COLOR2_INFO:
756 case R_0280AC_CB_COLOR3_INFO:
757 case R_0280B0_CB_COLOR4_INFO:
758 case R_0280B4_CB_COLOR5_INFO:
759 case R_0280B8_CB_COLOR6_INFO:
760 case R_0280BC_CB_COLOR7_INFO:
761 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
762 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
763 break;
764 case R_028060_CB_COLOR0_SIZE:
765 case R_028064_CB_COLOR1_SIZE:
766 case R_028068_CB_COLOR2_SIZE:
767 case R_02806C_CB_COLOR3_SIZE:
768 case R_028070_CB_COLOR4_SIZE:
769 case R_028074_CB_COLOR5_SIZE:
770 case R_028078_CB_COLOR6_SIZE:
771 case R_02807C_CB_COLOR7_SIZE:
772 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
773 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
774 track->cb_color_size_idx[tmp] = idx;
775 break;
776 /* This register were added late, there is userspace
777 * which does provide relocation for those but set
778 * 0 offset. In order to avoid breaking old userspace
779 * we detect this and set address to point to last
780 * CB_COLOR0_BASE, note that if userspace doesn't set
781 * CB_COLOR0_BASE before this register we will report
782 * error. Old userspace always set CB_COLOR0_BASE
783 * before any of this.
784 */
785 case R_0280E0_CB_COLOR0_FRAG:
786 case R_0280E4_CB_COLOR1_FRAG:
787 case R_0280E8_CB_COLOR2_FRAG:
788 case R_0280EC_CB_COLOR3_FRAG:
789 case R_0280F0_CB_COLOR4_FRAG:
790 case R_0280F4_CB_COLOR5_FRAG:
791 case R_0280F8_CB_COLOR6_FRAG:
792 case R_0280FC_CB_COLOR7_FRAG:
793 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
794 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
795 if (!track->cb_color_base_last[tmp]) {
796 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
797 return -EINVAL;
798 }
799 ib[idx] = track->cb_color_base_last[tmp];
800 printk_once(KERN_WARNING "You have old & broken userspace "
801 "please consider updating mesa & xf86-video-ati\n");
802 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
803 } else {
804 r = r600_cs_packet_next_reloc(p, &reloc);
805 if (r) {
806 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
807 return -EINVAL;
808 }
809 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
810 track->cb_color_frag_bo[tmp] = reloc->robj;
811 }
812 break;
813 case R_0280C0_CB_COLOR0_TILE:
814 case R_0280C4_CB_COLOR1_TILE:
815 case R_0280C8_CB_COLOR2_TILE:
816 case R_0280CC_CB_COLOR3_TILE:
817 case R_0280D0_CB_COLOR4_TILE:
818 case R_0280D4_CB_COLOR5_TILE:
819 case R_0280D8_CB_COLOR6_TILE:
820 case R_0280DC_CB_COLOR7_TILE:
821 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
822 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
823 if (!track->cb_color_base_last[tmp]) {
824 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
825 return -EINVAL;
826 }
827 ib[idx] = track->cb_color_base_last[tmp];
828 printk_once(KERN_WARNING "You have old & broken userspace "
829 "please consider updating mesa & xf86-video-ati\n");
830 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
831 } else {
832 r = r600_cs_packet_next_reloc(p, &reloc);
833 if (r) {
834 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
835 return -EINVAL;
836 }
837 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
838 track->cb_color_tile_bo[tmp] = reloc->robj;
839 }
840 break;
841 case CB_COLOR0_BASE:
842 case CB_COLOR1_BASE:
843 case CB_COLOR2_BASE:
844 case CB_COLOR3_BASE:
845 case CB_COLOR4_BASE:
846 case CB_COLOR5_BASE:
847 case CB_COLOR6_BASE:
848 case CB_COLOR7_BASE:
849 r = r600_cs_packet_next_reloc(p, &reloc);
850 if (r) {
851 dev_warn(p->dev, "bad SET_CONTEXT_REG "
852 "0x%04X\n", reg);
853 return -EINVAL;
854 }
855 tmp = (reg - CB_COLOR0_BASE) / 4;
856 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
857 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
858 track->cb_color_base_last[tmp] = ib[idx];
859 track->cb_color_bo[tmp] = reloc->robj;
860 break;
861 case DB_DEPTH_BASE:
862 r = r600_cs_packet_next_reloc(p, &reloc);
863 if (r) {
864 dev_warn(p->dev, "bad SET_CONTEXT_REG "
865 "0x%04X\n", reg);
866 return -EINVAL;
867 }
868 track->db_offset = radeon_get_ib_value(p, idx);
869 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
870 track->db_bo = reloc->robj;
871 break;
872 case DB_HTILE_DATA_BASE:
873 case SQ_PGM_START_FS:
874 case SQ_PGM_START_ES:
875 case SQ_PGM_START_VS:
876 case SQ_PGM_START_GS:
877 case SQ_PGM_START_PS:
878 case SQ_ALU_CONST_CACHE_GS_0:
879 case SQ_ALU_CONST_CACHE_GS_1:
880 case SQ_ALU_CONST_CACHE_GS_2:
881 case SQ_ALU_CONST_CACHE_GS_3:
882 case SQ_ALU_CONST_CACHE_GS_4:
883 case SQ_ALU_CONST_CACHE_GS_5:
884 case SQ_ALU_CONST_CACHE_GS_6:
885 case SQ_ALU_CONST_CACHE_GS_7:
886 case SQ_ALU_CONST_CACHE_GS_8:
887 case SQ_ALU_CONST_CACHE_GS_9:
888 case SQ_ALU_CONST_CACHE_GS_10:
889 case SQ_ALU_CONST_CACHE_GS_11:
890 case SQ_ALU_CONST_CACHE_GS_12:
891 case SQ_ALU_CONST_CACHE_GS_13:
892 case SQ_ALU_CONST_CACHE_GS_14:
893 case SQ_ALU_CONST_CACHE_GS_15:
894 case SQ_ALU_CONST_CACHE_PS_0:
895 case SQ_ALU_CONST_CACHE_PS_1:
896 case SQ_ALU_CONST_CACHE_PS_2:
897 case SQ_ALU_CONST_CACHE_PS_3:
898 case SQ_ALU_CONST_CACHE_PS_4:
899 case SQ_ALU_CONST_CACHE_PS_5:
900 case SQ_ALU_CONST_CACHE_PS_6:
901 case SQ_ALU_CONST_CACHE_PS_7:
902 case SQ_ALU_CONST_CACHE_PS_8:
903 case SQ_ALU_CONST_CACHE_PS_9:
904 case SQ_ALU_CONST_CACHE_PS_10:
905 case SQ_ALU_CONST_CACHE_PS_11:
906 case SQ_ALU_CONST_CACHE_PS_12:
907 case SQ_ALU_CONST_CACHE_PS_13:
908 case SQ_ALU_CONST_CACHE_PS_14:
909 case SQ_ALU_CONST_CACHE_PS_15:
910 case SQ_ALU_CONST_CACHE_VS_0:
911 case SQ_ALU_CONST_CACHE_VS_1:
912 case SQ_ALU_CONST_CACHE_VS_2:
913 case SQ_ALU_CONST_CACHE_VS_3:
914 case SQ_ALU_CONST_CACHE_VS_4:
915 case SQ_ALU_CONST_CACHE_VS_5:
916 case SQ_ALU_CONST_CACHE_VS_6:
917 case SQ_ALU_CONST_CACHE_VS_7:
918 case SQ_ALU_CONST_CACHE_VS_8:
919 case SQ_ALU_CONST_CACHE_VS_9:
920 case SQ_ALU_CONST_CACHE_VS_10:
921 case SQ_ALU_CONST_CACHE_VS_11:
922 case SQ_ALU_CONST_CACHE_VS_12:
923 case SQ_ALU_CONST_CACHE_VS_13:
924 case SQ_ALU_CONST_CACHE_VS_14:
925 case SQ_ALU_CONST_CACHE_VS_15:
926 r = r600_cs_packet_next_reloc(p, &reloc);
927 if (r) {
928 dev_warn(p->dev, "bad SET_CONTEXT_REG "
929 "0x%04X\n", reg);
930 return -EINVAL;
931 }
932 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
933 break;
934 default:
935 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
936 return -EINVAL;
937 }
938 return 0;
939 }
940
941 static inline unsigned minify(unsigned size, unsigned levels)
942 {
943 size = size >> levels;
944 if (size < 1)
945 size = 1;
946 return size;
947 }
948
949 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels,
950 unsigned w0, unsigned h0, unsigned d0, unsigned bpe,
951 unsigned *l0_size, unsigned *mipmap_size)
952 {
953 unsigned offset, i, level, face;
954 unsigned width, height, depth, rowstride, size;
955
956 w0 = minify(w0, 0);
957 h0 = minify(h0, 0);
958 d0 = minify(d0, 0);
959 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
960 width = minify(w0, i);
961 height = minify(h0, i);
962 depth = minify(d0, i);
963 for(face = 0; face < nfaces; face++) {
964 rowstride = ((width * bpe) + 255) & ~255;
965 size = height * rowstride * depth;
966 offset += size;
967 offset = (offset + 0x1f) & ~0x1f;
968 }
969 }
970 *l0_size = (((w0 * bpe) + 255) & ~255) * h0 * d0;
971 *mipmap_size = offset;
972 if (!blevel)
973 *mipmap_size -= *l0_size;
974 if (!nlevels)
975 *mipmap_size = *l0_size;
976 }
977
978 /**
979 * r600_check_texture_resource() - check if register is authorized or not
980 * @p: parser structure holding parsing context
981 * @idx: index into the cs buffer
982 * @texture: texture's bo structure
983 * @mipmap: mipmap's bo structure
984 *
985 * This function will check that the resource has valid field and that
986 * the texture and mipmap bo object are big enough to cover this resource.
987 */
988 static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
989 struct radeon_bo *texture,
990 struct radeon_bo *mipmap)
991 {
992 u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
993 u32 word0, word1, l0_size, mipmap_size;
994
995 /* on legacy kernel we don't perform advanced check */
996 if (p->rdev == NULL)
997 return 0;
998 word0 = radeon_get_ib_value(p, idx + 0);
999 word1 = radeon_get_ib_value(p, idx + 1);
1000 w0 = G_038000_TEX_WIDTH(word0) + 1;
1001 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1002 d0 = G_038004_TEX_DEPTH(word1);
1003 nfaces = 1;
1004 switch (G_038000_DIM(word0)) {
1005 case V_038000_SQ_TEX_DIM_1D:
1006 case V_038000_SQ_TEX_DIM_2D:
1007 case V_038000_SQ_TEX_DIM_3D:
1008 break;
1009 case V_038000_SQ_TEX_DIM_CUBEMAP:
1010 nfaces = 6;
1011 break;
1012 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1013 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1014 case V_038000_SQ_TEX_DIM_2D_MSAA:
1015 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1016 default:
1017 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1018 return -EINVAL;
1019 }
1020 if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) {
1021 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1022 __func__, __LINE__, G_038004_DATA_FORMAT(word1));
1023 return -EINVAL;
1024 }
1025 word0 = radeon_get_ib_value(p, idx + 4);
1026 word1 = radeon_get_ib_value(p, idx + 5);
1027 blevel = G_038010_BASE_LEVEL(word0);
1028 nlevels = G_038014_LAST_LEVEL(word1);
1029 r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, &l0_size, &mipmap_size);
1030 /* using get ib will give us the offset into the texture bo */
1031 word0 = radeon_get_ib_value(p, idx + 2);
1032 if ((l0_size + word0) > radeon_bo_size(texture)) {
1033 dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n",
1034 w0, h0, bpe, word0, l0_size, radeon_bo_size(texture));
1035 return -EINVAL;
1036 }
1037 /* using get ib will give us the offset into the mipmap bo */
1038 word0 = radeon_get_ib_value(p, idx + 3);
1039 if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
1040 dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1041 w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
1042 return -EINVAL;
1043 }
1044 return 0;
1045 }
1046
1047 static int r600_packet3_check(struct radeon_cs_parser *p,
1048 struct radeon_cs_packet *pkt)
1049 {
1050 struct radeon_cs_reloc *reloc;
1051 struct r600_cs_track *track;
1052 volatile u32 *ib;
1053 unsigned idx;
1054 unsigned i;
1055 unsigned start_reg, end_reg, reg;
1056 int r;
1057 u32 idx_value;
1058
1059 track = (struct r600_cs_track *)p->track;
1060 ib = p->ib->ptr;
1061 idx = pkt->idx + 1;
1062 idx_value = radeon_get_ib_value(p, idx);
1063
1064 switch (pkt->opcode) {
1065 case PACKET3_START_3D_CMDBUF:
1066 if (p->family >= CHIP_RV770 || pkt->count) {
1067 DRM_ERROR("bad START_3D\n");
1068 return -EINVAL;
1069 }
1070 break;
1071 case PACKET3_CONTEXT_CONTROL:
1072 if (pkt->count != 1) {
1073 DRM_ERROR("bad CONTEXT_CONTROL\n");
1074 return -EINVAL;
1075 }
1076 break;
1077 case PACKET3_INDEX_TYPE:
1078 case PACKET3_NUM_INSTANCES:
1079 if (pkt->count) {
1080 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1081 return -EINVAL;
1082 }
1083 break;
1084 case PACKET3_DRAW_INDEX:
1085 if (pkt->count != 3) {
1086 DRM_ERROR("bad DRAW_INDEX\n");
1087 return -EINVAL;
1088 }
1089 r = r600_cs_packet_next_reloc(p, &reloc);
1090 if (r) {
1091 DRM_ERROR("bad DRAW_INDEX\n");
1092 return -EINVAL;
1093 }
1094 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1095 ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1096 r = r600_cs_track_check(p);
1097 if (r) {
1098 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1099 return r;
1100 }
1101 break;
1102 case PACKET3_DRAW_INDEX_AUTO:
1103 if (pkt->count != 1) {
1104 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1105 return -EINVAL;
1106 }
1107 r = r600_cs_track_check(p);
1108 if (r) {
1109 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1110 return r;
1111 }
1112 break;
1113 case PACKET3_DRAW_INDEX_IMMD_BE:
1114 case PACKET3_DRAW_INDEX_IMMD:
1115 if (pkt->count < 2) {
1116 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1117 return -EINVAL;
1118 }
1119 r = r600_cs_track_check(p);
1120 if (r) {
1121 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1122 return r;
1123 }
1124 break;
1125 case PACKET3_WAIT_REG_MEM:
1126 if (pkt->count != 5) {
1127 DRM_ERROR("bad WAIT_REG_MEM\n");
1128 return -EINVAL;
1129 }
1130 /* bit 4 is reg (0) or mem (1) */
1131 if (idx_value & 0x10) {
1132 r = r600_cs_packet_next_reloc(p, &reloc);
1133 if (r) {
1134 DRM_ERROR("bad WAIT_REG_MEM\n");
1135 return -EINVAL;
1136 }
1137 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1138 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1139 }
1140 break;
1141 case PACKET3_SURFACE_SYNC:
1142 if (pkt->count != 3) {
1143 DRM_ERROR("bad SURFACE_SYNC\n");
1144 return -EINVAL;
1145 }
1146 /* 0xffffffff/0x0 is flush all cache flag */
1147 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1148 radeon_get_ib_value(p, idx + 2) != 0) {
1149 r = r600_cs_packet_next_reloc(p, &reloc);
1150 if (r) {
1151 DRM_ERROR("bad SURFACE_SYNC\n");
1152 return -EINVAL;
1153 }
1154 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1155 }
1156 break;
1157 case PACKET3_EVENT_WRITE:
1158 if (pkt->count != 2 && pkt->count != 0) {
1159 DRM_ERROR("bad EVENT_WRITE\n");
1160 return -EINVAL;
1161 }
1162 if (pkt->count) {
1163 r = r600_cs_packet_next_reloc(p, &reloc);
1164 if (r) {
1165 DRM_ERROR("bad EVENT_WRITE\n");
1166 return -EINVAL;
1167 }
1168 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1169 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1170 }
1171 break;
1172 case PACKET3_EVENT_WRITE_EOP:
1173 if (pkt->count != 4) {
1174 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1175 return -EINVAL;
1176 }
1177 r = r600_cs_packet_next_reloc(p, &reloc);
1178 if (r) {
1179 DRM_ERROR("bad EVENT_WRITE\n");
1180 return -EINVAL;
1181 }
1182 ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff);
1183 ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1184 break;
1185 case PACKET3_SET_CONFIG_REG:
1186 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1187 end_reg = 4 * pkt->count + start_reg - 4;
1188 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1189 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1190 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1191 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1192 return -EINVAL;
1193 }
1194 for (i = 0; i < pkt->count; i++) {
1195 reg = start_reg + (4 * i);
1196 r = r600_cs_check_reg(p, reg, idx+1+i);
1197 if (r)
1198 return r;
1199 }
1200 break;
1201 case PACKET3_SET_CONTEXT_REG:
1202 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1203 end_reg = 4 * pkt->count + start_reg - 4;
1204 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1205 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1206 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1207 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1208 return -EINVAL;
1209 }
1210 for (i = 0; i < pkt->count; i++) {
1211 reg = start_reg + (4 * i);
1212 r = r600_cs_check_reg(p, reg, idx+1+i);
1213 if (r)
1214 return r;
1215 }
1216 break;
1217 case PACKET3_SET_RESOURCE:
1218 if (pkt->count % 7) {
1219 DRM_ERROR("bad SET_RESOURCE\n");
1220 return -EINVAL;
1221 }
1222 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1223 end_reg = 4 * pkt->count + start_reg - 4;
1224 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1225 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1226 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1227 DRM_ERROR("bad SET_RESOURCE\n");
1228 return -EINVAL;
1229 }
1230 for (i = 0; i < (pkt->count / 7); i++) {
1231 struct radeon_bo *texture, *mipmap;
1232 u32 size, offset;
1233
1234 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1235 case SQ_TEX_VTX_VALID_TEXTURE:
1236 /* tex base */
1237 r = r600_cs_packet_next_reloc(p, &reloc);
1238 if (r) {
1239 DRM_ERROR("bad SET_RESOURCE\n");
1240 return -EINVAL;
1241 }
1242 ib[idx+1+(i*7)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1243 texture = reloc->robj;
1244 /* tex mip base */
1245 r = r600_cs_packet_next_reloc(p, &reloc);
1246 if (r) {
1247 DRM_ERROR("bad SET_RESOURCE\n");
1248 return -EINVAL;
1249 }
1250 ib[idx+1+(i*7)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1251 mipmap = reloc->robj;
1252 r = r600_check_texture_resource(p, idx+(i*7)+1,
1253 texture, mipmap);
1254 if (r)
1255 return r;
1256 break;
1257 case SQ_TEX_VTX_VALID_BUFFER:
1258 /* vtx base */
1259 r = r600_cs_packet_next_reloc(p, &reloc);
1260 if (r) {
1261 DRM_ERROR("bad SET_RESOURCE\n");
1262 return -EINVAL;
1263 }
1264 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
1265 size = radeon_get_ib_value(p, idx+1+(i*7)+1);
1266 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
1267 /* force size to size of the buffer */
1268 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
1269 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj);
1270 }
1271 ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff);
1272 ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff;
1273 break;
1274 case SQ_TEX_VTX_INVALID_TEXTURE:
1275 case SQ_TEX_VTX_INVALID_BUFFER:
1276 default:
1277 DRM_ERROR("bad SET_RESOURCE\n");
1278 return -EINVAL;
1279 }
1280 }
1281 break;
1282 case PACKET3_SET_ALU_CONST:
1283 if (track->sq_config & DX9_CONSTS) {
1284 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1285 end_reg = 4 * pkt->count + start_reg - 4;
1286 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
1287 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
1288 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
1289 DRM_ERROR("bad SET_ALU_CONST\n");
1290 return -EINVAL;
1291 }
1292 }
1293 break;
1294 case PACKET3_SET_BOOL_CONST:
1295 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
1296 end_reg = 4 * pkt->count + start_reg - 4;
1297 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
1298 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
1299 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
1300 DRM_ERROR("bad SET_BOOL_CONST\n");
1301 return -EINVAL;
1302 }
1303 break;
1304 case PACKET3_SET_LOOP_CONST:
1305 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
1306 end_reg = 4 * pkt->count + start_reg - 4;
1307 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
1308 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
1309 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
1310 DRM_ERROR("bad SET_LOOP_CONST\n");
1311 return -EINVAL;
1312 }
1313 break;
1314 case PACKET3_SET_CTL_CONST:
1315 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
1316 end_reg = 4 * pkt->count + start_reg - 4;
1317 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
1318 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
1319 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
1320 DRM_ERROR("bad SET_CTL_CONST\n");
1321 return -EINVAL;
1322 }
1323 break;
1324 case PACKET3_SET_SAMPLER:
1325 if (pkt->count % 3) {
1326 DRM_ERROR("bad SET_SAMPLER\n");
1327 return -EINVAL;
1328 }
1329 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
1330 end_reg = 4 * pkt->count + start_reg - 4;
1331 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
1332 (start_reg >= PACKET3_SET_SAMPLER_END) ||
1333 (end_reg >= PACKET3_SET_SAMPLER_END)) {
1334 DRM_ERROR("bad SET_SAMPLER\n");
1335 return -EINVAL;
1336 }
1337 break;
1338 case PACKET3_SURFACE_BASE_UPDATE:
1339 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
1340 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1341 return -EINVAL;
1342 }
1343 if (pkt->count) {
1344 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
1345 return -EINVAL;
1346 }
1347 break;
1348 case PACKET3_NOP:
1349 break;
1350 default:
1351 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1352 return -EINVAL;
1353 }
1354 return 0;
1355 }
1356
1357 int r600_cs_parse(struct radeon_cs_parser *p)
1358 {
1359 struct radeon_cs_packet pkt;
1360 struct r600_cs_track *track;
1361 int r;
1362
1363 if (p->track == NULL) {
1364 /* initialize tracker, we are in kms */
1365 track = kzalloc(sizeof(*track), GFP_KERNEL);
1366 if (track == NULL)
1367 return -ENOMEM;
1368 r600_cs_track_init(track);
1369 if (p->rdev->family < CHIP_RV770) {
1370 track->npipes = p->rdev->config.r600.tiling_npipes;
1371 track->nbanks = p->rdev->config.r600.tiling_nbanks;
1372 track->group_size = p->rdev->config.r600.tiling_group_size;
1373 } else if (p->rdev->family <= CHIP_RV740) {
1374 track->npipes = p->rdev->config.rv770.tiling_npipes;
1375 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
1376 track->group_size = p->rdev->config.rv770.tiling_group_size;
1377 }
1378 p->track = track;
1379 }
1380 do {
1381 r = r600_cs_packet_parse(p, &pkt, p->idx);
1382 if (r) {
1383 kfree(p->track);
1384 p->track = NULL;
1385 return r;
1386 }
1387 p->idx += pkt.count + 2;
1388 switch (pkt.type) {
1389 case PACKET_TYPE0:
1390 r = r600_cs_parse_packet0(p, &pkt);
1391 break;
1392 case PACKET_TYPE2:
1393 break;
1394 case PACKET_TYPE3:
1395 r = r600_packet3_check(p, &pkt);
1396 break;
1397 default:
1398 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1399 kfree(p->track);
1400 p->track = NULL;
1401 return -EINVAL;
1402 }
1403 if (r) {
1404 kfree(p->track);
1405 p->track = NULL;
1406 return r;
1407 }
1408 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1409 #if 0
1410 for (r = 0; r < p->ib->length_dw; r++) {
1411 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
1412 mdelay(1);
1413 }
1414 #endif
1415 kfree(p->track);
1416 p->track = NULL;
1417 return 0;
1418 }
1419
1420 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
1421 {
1422 if (p->chunk_relocs_idx == -1) {
1423 return 0;
1424 }
1425 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
1426 if (p->relocs == NULL) {
1427 return -ENOMEM;
1428 }
1429 return 0;
1430 }
1431
1432 /**
1433 * cs_parser_fini() - clean parser states
1434 * @parser: parser structure holding parsing context.
1435 * @error: error number
1436 *
1437 * If error is set than unvalidate buffer, otherwise just free memory
1438 * used by parsing context.
1439 **/
1440 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
1441 {
1442 unsigned i;
1443
1444 kfree(parser->relocs);
1445 for (i = 0; i < parser->nchunks; i++) {
1446 kfree(parser->chunks[i].kdata);
1447 kfree(parser->chunks[i].kpage[0]);
1448 kfree(parser->chunks[i].kpage[1]);
1449 }
1450 kfree(parser->chunks);
1451 kfree(parser->chunks_array);
1452 }
1453
1454 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
1455 unsigned family, u32 *ib, int *l)
1456 {
1457 struct radeon_cs_parser parser;
1458 struct radeon_cs_chunk *ib_chunk;
1459 struct radeon_ib fake_ib;
1460 struct r600_cs_track *track;
1461 int r;
1462
1463 /* initialize tracker */
1464 track = kzalloc(sizeof(*track), GFP_KERNEL);
1465 if (track == NULL)
1466 return -ENOMEM;
1467 r600_cs_track_init(track);
1468 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
1469 /* initialize parser */
1470 memset(&parser, 0, sizeof(struct radeon_cs_parser));
1471 parser.filp = filp;
1472 parser.dev = &dev->pdev->dev;
1473 parser.rdev = NULL;
1474 parser.family = family;
1475 parser.ib = &fake_ib;
1476 parser.track = track;
1477 fake_ib.ptr = ib;
1478 r = radeon_cs_parser_init(&parser, data);
1479 if (r) {
1480 DRM_ERROR("Failed to initialize parser !\n");
1481 r600_cs_parser_fini(&parser, r);
1482 return r;
1483 }
1484 r = r600_cs_parser_relocs_legacy(&parser);
1485 if (r) {
1486 DRM_ERROR("Failed to parse relocation !\n");
1487 r600_cs_parser_fini(&parser, r);
1488 return r;
1489 }
1490 /* Copy the packet into the IB, the parser will read from the
1491 * input memory (cached) and write to the IB (which can be
1492 * uncached). */
1493 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
1494 parser.ib->length_dw = ib_chunk->length_dw;
1495 *l = parser.ib->length_dw;
1496 r = r600_cs_parse(&parser);
1497 if (r) {
1498 DRM_ERROR("Invalid command stream !\n");
1499 r600_cs_parser_fini(&parser, r);
1500 return r;
1501 }
1502 r = radeon_cs_finish_pages(&parser);
1503 if (r) {
1504 DRM_ERROR("Invalid command stream !\n");
1505 r600_cs_parser_fini(&parser, r);
1506 return r;
1507 }
1508 r600_cs_parser_fini(&parser, r);
1509 return r;
1510 }
1511
1512 void r600_cs_legacy_init(void)
1513 {
1514 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
1515 }
Linux with added FPC-III support