drivers/gpu/drm/radeon/radeon_asic.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_ASIC_H__
  29 #define __RADEON_ASIC_H__
  30
  31 /*
  32  * common functions
  33  */
  34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45 /*
  46  * r100,rv100,rs100,rv200,rs200
  47  */
  48 struct r100_mc_save {
  49         u32     GENMO_WT;
  50         u32     CRTC_EXT_CNTL;
  51         u32     CRTC_GEN_CNTL;
  52         u32     CRTC2_GEN_CNTL;
  53         u32     CUR_OFFSET;
  54         u32     CUR2_OFFSET;
  55 };
  56 int r100_init(struct radeon_device *rdev);
  57 void r100_fini(struct radeon_device *rdev);
  58 int r100_suspend(struct radeon_device *rdev);
  59 int r100_resume(struct radeon_device *rdev);
  60 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  61 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  62 void r100_vga_set_state(struct radeon_device *rdev, bool state);
  63 int r100_gpu_reset(struct radeon_device *rdev);
  64 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  65 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  66 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  67 void r100_cp_commit(struct radeon_device *rdev);
  68 void r100_ring_start(struct radeon_device *rdev);
  69 int r100_irq_set(struct radeon_device *rdev);
  70 int r100_irq_process(struct radeon_device *rdev);
  71 void r100_fence_ring_emit(struct radeon_device *rdev,
  72                           struct radeon_fence *fence);
  73 int r100_cs_parse(struct radeon_cs_parser *p);
  74 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  75 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  76 int r100_copy_blit(struct radeon_device *rdev,
  77                    uint64_t src_offset,
  78                    uint64_t dst_offset,
  79                    unsigned num_pages,
  80                    struct radeon_fence *fence);
  81 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  82                          uint32_t tiling_flags, uint32_t pitch,
  83                          uint32_t offset, uint32_t obj_size);
  84 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  85 void r100_bandwidth_update(struct radeon_device *rdev);
  86 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  87 int r100_ring_test(struct radeon_device *rdev);
  88 void r100_hpd_init(struct radeon_device *rdev);
  89 void r100_hpd_fini(struct radeon_device *rdev);
  90 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  91 void r100_hpd_set_polarity(struct radeon_device *rdev,
  92                            enum radeon_hpd_id hpd);
  93 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  94 int r100_debugfs_cp_init(struct radeon_device *rdev);
  95 void r100_cp_disable(struct radeon_device *rdev);
  96 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  97 void r100_cp_fini(struct radeon_device *rdev);
  98 int r100_pci_gart_init(struct radeon_device *rdev);
  99 void r100_pci_gart_fini(struct radeon_device *rdev);
 100 int r100_pci_gart_enable(struct radeon_device *rdev);
 101 void r100_pci_gart_disable(struct radeon_device *rdev);
 102 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
 103 int r100_gui_wait_for_idle(struct radeon_device *rdev);
 104 void r100_ib_fini(struct radeon_device *rdev);
 105 int r100_ib_init(struct radeon_device *rdev);
 106 void r100_irq_disable(struct radeon_device *rdev);
 107 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 108 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 109 void r100_vram_init_sizes(struct radeon_device *rdev);
 110 void r100_wb_disable(struct radeon_device *rdev);
 111 void r100_wb_fini(struct radeon_device *rdev);
 112 int r100_wb_init(struct radeon_device *rdev);
 113 void r100_hdp_reset(struct radeon_device *rdev);
 114 int r100_rb2d_reset(struct radeon_device *rdev);
 115 int r100_cp_reset(struct radeon_device *rdev);
 116 void r100_vga_render_disable(struct radeon_device *rdev);
 117 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 118                                          struct radeon_cs_packet *pkt,
 119                                          struct radeon_bo *robj);
 120 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 121                           struct radeon_cs_packet *pkt,
 122                           const unsigned *auth, unsigned n,
 123                           radeon_packet0_check_t check);
 124 int r100_cs_packet_parse(struct radeon_cs_parser *p,
 125                          struct radeon_cs_packet *pkt,
 126                          unsigned idx);
 127 void r100_enable_bm(struct radeon_device *rdev);
 128 void r100_set_common_regs(struct radeon_device *rdev);
 129
 130 /*
 131  * r200,rv250,rs300,rv280
 132  */
 133 extern int r200_copy_dma(struct radeon_device *rdev,
 134                         uint64_t src_offset,
 135                         uint64_t dst_offset,
 136                         unsigned num_pages,
 137                         struct radeon_fence *fence);
 138
 139 /*
 140  * r300,r350,rv350,rv380
 141  */
 142 extern int r300_init(struct radeon_device *rdev);
 143 extern void r300_fini(struct radeon_device *rdev);
 144 extern int r300_suspend(struct radeon_device *rdev);
 145 extern int r300_resume(struct radeon_device *rdev);
 146 extern int r300_gpu_reset(struct radeon_device *rdev);
 147 extern void r300_ring_start(struct radeon_device *rdev);
 148 extern void r300_fence_ring_emit(struct radeon_device *rdev,
 149                                 struct radeon_fence *fence);
 150 extern int r300_cs_parse(struct radeon_cs_parser *p);
 151 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 152 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 153 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 154 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 155 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 156 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 157
 158 /*
 159  * r420,r423,rv410
 160  */
 161 extern int r420_init(struct radeon_device *rdev);
 162 extern void r420_fini(struct radeon_device *rdev);
 163 extern int r420_suspend(struct radeon_device *rdev);
 164 extern int r420_resume(struct radeon_device *rdev);
 165
 166 /*
 167  * rs400,rs480
 168  */
 169 extern int rs400_init(struct radeon_device *rdev);
 170 extern void rs400_fini(struct radeon_device *rdev);
 171 extern int rs400_suspend(struct radeon_device *rdev);
 172 extern int rs400_resume(struct radeon_device *rdev);
 173 void rs400_gart_tlb_flush(struct radeon_device *rdev);
 174 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 175 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 176 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 177
 178 /*
 179  * rs600.
 180  */
 181 extern int rs600_init(struct radeon_device *rdev);
 182 extern void rs600_fini(struct radeon_device *rdev);
 183 extern int rs600_suspend(struct radeon_device *rdev);
 184 extern int rs600_resume(struct radeon_device *rdev);
 185 int rs600_irq_set(struct radeon_device *rdev);
 186 int rs600_irq_process(struct radeon_device *rdev);
 187 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 188 void rs600_gart_tlb_flush(struct radeon_device *rdev);
 189 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
 190 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 191 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 192 void rs600_bandwidth_update(struct radeon_device *rdev);
 193 void rs600_hpd_init(struct radeon_device *rdev);
 194 void rs600_hpd_fini(struct radeon_device *rdev);
 195 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 196 void rs600_hpd_set_polarity(struct radeon_device *rdev,
 197                             enum radeon_hpd_id hpd);
 198
 199 /*
 200  * rs690,rs740
 201  */
 202 int rs690_init(struct radeon_device *rdev);
 203 void rs690_fini(struct radeon_device *rdev);
 204 int rs690_resume(struct radeon_device *rdev);
 205 int rs690_suspend(struct radeon_device *rdev);
 206 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 207 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 208 void rs690_bandwidth_update(struct radeon_device *rdev);
 209
 210 /*
 211  * rv515
 212  */
 213 int rv515_init(struct radeon_device *rdev);
 214 void rv515_fini(struct radeon_device *rdev);
 215 int rv515_gpu_reset(struct radeon_device *rdev);
 216 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 217 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 218 void rv515_ring_start(struct radeon_device *rdev);
 219 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 220 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 221 void rv515_bandwidth_update(struct radeon_device *rdev);
 222 int rv515_resume(struct radeon_device *rdev);
 223 int rv515_suspend(struct radeon_device *rdev);
 224
 225 /*
 226  * r520,rv530,rv560,rv570,r580
 227  */
 228 int r520_init(struct radeon_device *rdev);
 229 int r520_resume(struct radeon_device *rdev);
 230
 231 /*
 232  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 233  */
 234 int r600_init(struct radeon_device *rdev);
 235 void r600_fini(struct radeon_device *rdev);
 236 int r600_suspend(struct radeon_device *rdev);
 237 int r600_resume(struct radeon_device *rdev);
 238 void r600_vga_set_state(struct radeon_device *rdev, bool state);
 239 int r600_wb_init(struct radeon_device *rdev);
 240 void r600_wb_fini(struct radeon_device *rdev);
 241 void r600_cp_commit(struct radeon_device *rdev);
 242 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 243 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 244 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 245 int r600_cs_parse(struct radeon_cs_parser *p);
 246 void r600_fence_ring_emit(struct radeon_device *rdev,
 247                           struct radeon_fence *fence);
 248 int r600_copy_dma(struct radeon_device *rdev,
 249                   uint64_t src_offset,
 250                   uint64_t dst_offset,
 251                   unsigned num_pages,
 252                   struct radeon_fence *fence);
 253 int r600_irq_process(struct radeon_device *rdev);
 254 int r600_irq_set(struct radeon_device *rdev);
 255 int r600_gpu_reset(struct radeon_device *rdev);
 256 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 257                          uint32_t tiling_flags, uint32_t pitch,
 258                          uint32_t offset, uint32_t obj_size);
 259 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 260 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 261 int r600_ring_test(struct radeon_device *rdev);
 262 int r600_copy_blit(struct radeon_device *rdev,
 263                    uint64_t src_offset, uint64_t dst_offset,
 264                    unsigned num_pages, struct radeon_fence *fence);
 265 void r600_hpd_init(struct radeon_device *rdev);
 266 void r600_hpd_fini(struct radeon_device *rdev);
 267 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 268 void r600_hpd_set_polarity(struct radeon_device *rdev,
 269                            enum radeon_hpd_id hpd);
 270 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
 271
 272 /*
 273  * rv770,rv730,rv710,rv740
 274  */
 275 int rv770_init(struct radeon_device *rdev);
 276 void rv770_fini(struct radeon_device *rdev);
 277 int rv770_suspend(struct radeon_device *rdev);
 278 int rv770_resume(struct radeon_device *rdev);
 279 int rv770_gpu_reset(struct radeon_device *rdev);
 280
 281 /*
 282  * evergreen
 283  */
 284 int evergreen_init(struct radeon_device *rdev);
 285 void evergreen_fini(struct radeon_device *rdev);
 286 int evergreen_suspend(struct radeon_device *rdev);
 287 int evergreen_resume(struct radeon_device *rdev);
 288 int evergreen_gpu_reset(struct radeon_device *rdev);
 289 void evergreen_bandwidth_update(struct radeon_device *rdev);
 290 void evergreen_hpd_init(struct radeon_device *rdev);
 291 void evergreen_hpd_fini(struct radeon_device *rdev);
 292 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 293 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 294                                 enum radeon_hpd_id hpd);
 295 #endif