drivers/gpu/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 /*
  36  * BIOS.
  37  */
  38
  39 /* If you boot an IGP board with a discrete card as the primary,
  40  * the IGP rom is not accessible via the rom bar as the IGP rom is
  41  * part of the system bios.  On boot, the system bios puts a
  42  * copy of the igp rom at the start of vram if a discrete card is
  43  * present.
  44  */
  45 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  46 {
  47         uint8_t __iomem *bios;
  48         resource_size_t vram_base;
  49         resource_size_t size = 256 * 1024; /* ??? */
  50
  51         rdev->bios = NULL;
  52         vram_base = drm_get_resource_start(rdev->ddev, 0);
  53         bios = ioremap(vram_base, size);
  54         if (!bios) {
  55                 return false;
  56         }
  57
  58         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  59                 iounmap(bios);
  60                 return false;
  61         }
  62         rdev->bios = kmalloc(size, GFP_KERNEL);
  63         if (rdev->bios == NULL) {
  64                 iounmap(bios);
  65                 return false;
  66         }
  67         memcpy_fromio(rdev->bios, bios, size);
  68         iounmap(bios);
  69         return true;
  70 }
  71
  72 static bool radeon_read_bios(struct radeon_device *rdev)
  73 {
  74         uint8_t __iomem *bios;
  75         size_t size;
  76
  77         rdev->bios = NULL;
  78         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  79         bios = pci_map_rom(rdev->pdev, &size);
  80         if (!bios) {
  81                 return false;
  82         }
  83
  84         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  85                 pci_unmap_rom(rdev->pdev, bios);
  86                 return false;
  87         }
  88         rdev->bios = kmalloc(size, GFP_KERNEL);
  89         if (rdev->bios == NULL) {
  90                 pci_unmap_rom(rdev->pdev, bios);
  91                 return false;
  92         }
  93         memcpy(rdev->bios, bios, size);
  94         pci_unmap_rom(rdev->pdev, bios);
  95         return true;
  96 }
  97
  98 /* ATRM is used to get the BIOS on the discrete cards in
  99  * dual-gpu systems.
 100  */
 101 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 102 {
 103         int ret;
 104         int size = 64 * 1024;
 105         int i;
 106
 107         if (!radeon_atrm_supported(rdev->pdev))
 108                 return false;
 109
 110         rdev->bios = kmalloc(size, GFP_KERNEL);
 111         if (!rdev->bios) {
 112                 DRM_ERROR("Unable to allocate bios\n");
 113                 return false;
 114         }
 115
 116         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 117                 ret = radeon_atrm_get_bios_chunk(rdev->bios,
 118                                                  (i * ATRM_BIOS_PAGE),
 119                                                  ATRM_BIOS_PAGE);
 120                 if (ret <= 0)
 121                         break;
 122         }
 123
 124         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 125                 kfree(rdev->bios);
 126                 return false;
 127         }
 128         return true;
 129 }
 130 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 131 {
 132         uint32_t viph_control;
 133         uint32_t bus_cntl;
 134         uint32_t d1vga_control;
 135         uint32_t d2vga_control;
 136         uint32_t vga_render_control;
 137         uint32_t rom_cntl;
 138         uint32_t cg_spll_func_cntl = 0;
 139         uint32_t cg_spll_status;
 140         bool r;
 141
 142         viph_control = RREG32(RADEON_VIPH_CONTROL);
 143         bus_cntl = RREG32(RADEON_BUS_CNTL);
 144         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 145         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 146         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 147         rom_cntl = RREG32(R600_ROM_CNTL);
 148
 149         /* disable VIP */
 150         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 151         /* enable the rom */
 152         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 153         /* Disable VGA mode */
 154         WREG32(AVIVO_D1VGA_CONTROL,
 155                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 156                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 157         WREG32(AVIVO_D2VGA_CONTROL,
 158                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 159                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 160         WREG32(AVIVO_VGA_RENDER_CONTROL,
 161                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 162
 163         if (rdev->family == CHIP_RV730) {
 164                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 165
 166                 /* enable bypass mode */
 167                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 168                                                 R600_SPLL_BYPASS_EN));
 169
 170                 /* wait for SPLL_CHG_STATUS to change to 1 */
 171                 cg_spll_status = 0;
 172                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 173                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 174
 175                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 176         } else
 177                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 178
 179         r = radeon_read_bios(rdev);
 180
 181         /* restore regs */
 182         if (rdev->family == CHIP_RV730) {
 183                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 184
 185                 /* wait for SPLL_CHG_STATUS to change to 1 */
 186                 cg_spll_status = 0;
 187                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 188                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 189         }
 190         WREG32(RADEON_VIPH_CONTROL, viph_control);
 191         WREG32(RADEON_BUS_CNTL, bus_cntl);
 192         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 193         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 194         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 195         WREG32(R600_ROM_CNTL, rom_cntl);
 196         return r;
 197 }
 198
 199 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 200 {
 201         uint32_t viph_control;
 202         uint32_t bus_cntl;
 203         uint32_t d1vga_control;
 204         uint32_t d2vga_control;
 205         uint32_t vga_render_control;
 206         uint32_t rom_cntl;
 207         uint32_t general_pwrmgt;
 208         uint32_t low_vid_lower_gpio_cntl;
 209         uint32_t medium_vid_lower_gpio_cntl;
 210         uint32_t high_vid_lower_gpio_cntl;
 211         uint32_t ctxsw_vid_lower_gpio_cntl;
 212         uint32_t lower_gpio_enable;
 213         bool r;
 214
 215         viph_control = RREG32(RADEON_VIPH_CONTROL);
 216         bus_cntl = RREG32(RADEON_BUS_CNTL);
 217         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 218         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 219         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 220         rom_cntl = RREG32(R600_ROM_CNTL);
 221         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 222         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 223         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 224         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 225         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 226         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 227
 228         /* disable VIP */
 229         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 230         /* enable the rom */
 231         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 232         /* Disable VGA mode */
 233         WREG32(AVIVO_D1VGA_CONTROL,
 234                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 235                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 236         WREG32(AVIVO_D2VGA_CONTROL,
 237                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 238                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 239         WREG32(AVIVO_VGA_RENDER_CONTROL,
 240                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 241
 242         WREG32(R600_ROM_CNTL,
 243                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 244                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 245                 R600_SCK_OVERWRITE));
 246
 247         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 248         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 249                (low_vid_lower_gpio_cntl & ~0x400));
 250         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 251                (medium_vid_lower_gpio_cntl & ~0x400));
 252         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 253                (high_vid_lower_gpio_cntl & ~0x400));
 254         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 255                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 256         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 257
 258         r = radeon_read_bios(rdev);
 259
 260         /* restore regs */
 261         WREG32(RADEON_VIPH_CONTROL, viph_control);
 262         WREG32(RADEON_BUS_CNTL, bus_cntl);
 263         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 264         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 265         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 266         WREG32(R600_ROM_CNTL, rom_cntl);
 267         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 268         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 269         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 270         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 271         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 272         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 273         return r;
 274 }
 275
 276 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 277 {
 278         uint32_t seprom_cntl1;
 279         uint32_t viph_control;
 280         uint32_t bus_cntl;
 281         uint32_t d1vga_control;
 282         uint32_t d2vga_control;
 283         uint32_t vga_render_control;
 284         uint32_t gpiopad_a;
 285         uint32_t gpiopad_en;
 286         uint32_t gpiopad_mask;
 287         bool r;
 288
 289         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 290         viph_control = RREG32(RADEON_VIPH_CONTROL);
 291         bus_cntl = RREG32(RADEON_BUS_CNTL);
 292         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 293         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 294         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 295         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 296         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 297         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 298
 299         WREG32(RADEON_SEPROM_CNTL1,
 300                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 301                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 302         WREG32(RADEON_GPIOPAD_A, 0);
 303         WREG32(RADEON_GPIOPAD_EN, 0);
 304         WREG32(RADEON_GPIOPAD_MASK, 0);
 305
 306         /* disable VIP */
 307         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 308
 309         /* enable the rom */
 310         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 311
 312         /* Disable VGA mode */
 313         WREG32(AVIVO_D1VGA_CONTROL,
 314                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 315                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 316         WREG32(AVIVO_D2VGA_CONTROL,
 317                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 318                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 319         WREG32(AVIVO_VGA_RENDER_CONTROL,
 320                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 321
 322         r = radeon_read_bios(rdev);
 323
 324         /* restore regs */
 325         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 326         WREG32(RADEON_VIPH_CONTROL, viph_control);
 327         WREG32(RADEON_BUS_CNTL, bus_cntl);
 328         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 329         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 330         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 331         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 332         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 333         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 334         return r;
 335 }
 336
 337 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 338 {
 339         uint32_t seprom_cntl1;
 340         uint32_t viph_control;
 341         uint32_t bus_cntl;
 342         uint32_t crtc_gen_cntl;
 343         uint32_t crtc2_gen_cntl;
 344         uint32_t crtc_ext_cntl;
 345         uint32_t fp2_gen_cntl;
 346         bool r;
 347
 348         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 349         viph_control = RREG32(RADEON_VIPH_CONTROL);
 350         bus_cntl = RREG32(RADEON_BUS_CNTL);
 351         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 352         crtc2_gen_cntl = 0;
 353         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 354         fp2_gen_cntl = 0;
 355
 356         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 357                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 358         }
 359
 360         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 361                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 362         }
 363
 364         WREG32(RADEON_SEPROM_CNTL1,
 365                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 366                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 367
 368         /* disable VIP */
 369         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 370
 371         /* enable the rom */
 372         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 373
 374         /* Turn off mem requests and CRTC for both controllers */
 375         WREG32(RADEON_CRTC_GEN_CNTL,
 376                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 377                 (RADEON_CRTC_DISP_REQ_EN_B |
 378                  RADEON_CRTC_EXT_DISP_EN)));
 379         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 380                 WREG32(RADEON_CRTC2_GEN_CNTL,
 381                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 382                         RADEON_CRTC2_DISP_REQ_EN_B));
 383         }
 384         /* Turn off CRTC */
 385         WREG32(RADEON_CRTC_EXT_CNTL,
 386                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 387                 (RADEON_CRTC_SYNC_TRISTAT |
 388                  RADEON_CRTC_DISPLAY_DIS)));
 389
 390         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 391                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 392         }
 393
 394         r = radeon_read_bios(rdev);
 395
 396         /* restore regs */
 397         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 398         WREG32(RADEON_VIPH_CONTROL, viph_control);
 399         WREG32(RADEON_BUS_CNTL, bus_cntl);
 400         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 401         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 402                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 403         }
 404         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 405         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 406                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 407         }
 408         return r;
 409 }
 410
 411 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 412 {
 413         if (rdev->flags & RADEON_IS_IGP)
 414                 return igp_read_bios_from_vram(rdev);
 415         else if (rdev->family >= CHIP_RV770)
 416                 return r700_read_disabled_bios(rdev);
 417         else if (rdev->family >= CHIP_R600)
 418                 return r600_read_disabled_bios(rdev);
 419         else if (rdev->family >= CHIP_RS600)
 420                 return avivo_read_disabled_bios(rdev);
 421         else
 422                 return legacy_read_disabled_bios(rdev);
 423 }
 424
 425
 426 bool radeon_get_bios(struct radeon_device *rdev)
 427 {
 428         bool r;
 429         uint16_t tmp;
 430
 431         r = radeon_atrm_get_bios(rdev);
 432         if (r == false)
 433                 r = igp_read_bios_from_vram(rdev);
 434         if (r == false)
 435                 r = radeon_read_bios(rdev);
 436         if (r == false) {
 437                 r = radeon_read_disabled_bios(rdev);
 438         }
 439         if (r == false || rdev->bios == NULL) {
 440                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 441                 rdev->bios = NULL;
 442                 return false;
 443         }
 444         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 445                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 446                 goto free_bios;
 447         }
 448
 449         tmp = RBIOS16(0x18);
 450         if (RBIOS8(tmp + 0x14) != 0x0) {
 451                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 452                 goto free_bios;
 453         }
 454
 455         rdev->bios_header_start = RBIOS16(0x48);
 456         if (!rdev->bios_header_start) {
 457                 goto free_bios;
 458         }
 459         tmp = rdev->bios_header_start + 4;
 460         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 461             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 462                 rdev->is_atom_bios = true;
 463         } else {
 464                 rdev->is_atom_bios = false;
 465         }
 466
 467         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 468         return true;
 469 free_bios:
 470         kfree(rdev->bios);
 471         rdev->bios = NULL;
 472         return false;
 473 }