drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
 103                         else
 104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 112                                   else*/
 113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 119                         else
 120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 127                 else
 128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
 137                 else
 138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
 148                 else
 149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179 void
 180 radeon_link_encoder_connector(struct drm_device *dev)
 181 {
 182         struct drm_connector *connector;
 183         struct radeon_connector *radeon_connector;
 184         struct drm_encoder *encoder;
 185         struct radeon_encoder *radeon_encoder;
 186
 187         /* walk the list and link encoders to connectors */
 188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 189                 radeon_connector = to_radeon_connector(connector);
 190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 191                         radeon_encoder = to_radeon_encoder(encoder);
 192                         if (radeon_encoder->devices & radeon_connector->devices)
 193                                 drm_mode_connector_attach_encoder(connector, encoder);
 194                 }
 195         }
 196 }
 197
 198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 199 {
 200         struct drm_device *dev = encoder->dev;
 201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 202         struct drm_connector *connector;
 203
 204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 205                 if (connector->encoder == encoder) {
 206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
 209                                   radeon_encoder->active_device, radeon_encoder->devices,
 210                                   radeon_connector->devices, encoder->encoder_type);
 211                 }
 212         }
 213 }
 214
 215 static struct drm_connector *
 216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 217 {
 218         struct drm_device *dev = encoder->dev;
 219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 220         struct drm_connector *connector;
 221         struct radeon_connector *radeon_connector;
 222
 223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 224                 radeon_connector = to_radeon_connector(connector);
 225                 if (radeon_encoder->active_device & radeon_connector->devices)
 226                         return connector;
 227         }
 228         return NULL;
 229 }
 230
 231 static struct radeon_connector_atom_dig *
 232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_device *rdev = dev->dev_private;
 236         struct drm_connector *connector;
 237         struct radeon_connector *radeon_connector;
 238         struct radeon_connector_atom_dig *dig_connector;
 239
 240         if (!rdev->is_atom_bios)
 241                 return NULL;
 242
 243         connector = radeon_get_connector_for_encoder(encoder);
 244         if (!connector)
 245                 return NULL;
 246
 247         radeon_connector = to_radeon_connector(connector);
 248
 249         if (!radeon_connector->con_priv)
 250                 return NULL;
 251
 252         dig_connector = radeon_connector->con_priv;
 253
 254         return dig_connector;
 255 }
 256
 257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 258                                    struct drm_display_mode *mode,
 259                                    struct drm_display_mode *adjusted_mode)
 260 {
 261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 262         struct drm_device *dev = encoder->dev;
 263         struct radeon_device *rdev = dev->dev_private;
 264
 265         /* adjust pm to upcoming mode change */
 266         radeon_pm_compute_clocks(rdev);
 267
 268         /* set the active encoder to connector routing */
 269         radeon_encoder_set_active_device(encoder);
 270         drm_mode_set_crtcinfo(adjusted_mode, 0);
 271
 272         /* hw bug */
 273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 276
 277         /* get the native mode for LVDS */
 278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 280                 int mode_id = adjusted_mode->base.id;
 281                 *adjusted_mode = *native_mode;
 282                 if (!ASIC_IS_AVIVO(rdev)) {
 283                         adjusted_mode->hdisplay = mode->hdisplay;
 284                         adjusted_mode->vdisplay = mode->vdisplay;
 285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
 286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
 287                 }
 288                 adjusted_mode->base.id = mode_id;
 289         }
 290
 291         /* get the native mode for TV */
 292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 294                 if (tv_dac) {
 295                         if (tv_dac->tv_std == TV_STD_NTSC ||
 296                             tv_dac->tv_std == TV_STD_NTSC_J ||
 297                             tv_dac->tv_std == TV_STD_PAL_M)
 298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 299                         else
 300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 301                 }
 302         }
 303
 304         if (ASIC_IS_DCE3(rdev) &&
 305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 307                 radeon_dp_set_link_config(connector, mode);
 308         }
 309
 310         return true;
 311 }
 312
 313 static void
 314 atombios_dac_setup(struct drm_encoder *encoder, int action)
 315 {
 316         struct drm_device *dev = encoder->dev;
 317         struct radeon_device *rdev = dev->dev_private;
 318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 320         int index = 0;
 321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 322
 323         memset(&args, 0, sizeof(args));
 324
 325         switch (radeon_encoder->encoder_id) {
 326         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 327         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 328                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 329                 break;
 330         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 332                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 333                 break;
 334         }
 335
 336         args.ucAction = action;
 337
 338         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 339                 args.ucDacStandard = ATOM_DAC1_PS2;
 340         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 341                 args.ucDacStandard = ATOM_DAC1_CV;
 342         else {
 343                 switch (dac_info->tv_std) {
 344                 case TV_STD_PAL:
 345                 case TV_STD_PAL_M:
 346                 case TV_STD_SCART_PAL:
 347                 case TV_STD_SECAM:
 348                 case TV_STD_PAL_CN:
 349                         args.ucDacStandard = ATOM_DAC1_PAL;
 350                         break;
 351                 case TV_STD_NTSC:
 352                 case TV_STD_NTSC_J:
 353                 case TV_STD_PAL_60:
 354                 default:
 355                         args.ucDacStandard = ATOM_DAC1_NTSC;
 356                         break;
 357                 }
 358         }
 359         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 360
 361         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 362
 363 }
 364
 365 static void
 366 atombios_tv_setup(struct drm_encoder *encoder, int action)
 367 {
 368         struct drm_device *dev = encoder->dev;
 369         struct radeon_device *rdev = dev->dev_private;
 370         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 371         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 372         int index = 0;
 373         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 374
 375         memset(&args, 0, sizeof(args));
 376
 377         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 378
 379         args.sTVEncoder.ucAction = action;
 380
 381         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 382                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 383         else {
 384                 switch (dac_info->tv_std) {
 385                 case TV_STD_NTSC:
 386                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 387                         break;
 388                 case TV_STD_PAL:
 389                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 390                         break;
 391                 case TV_STD_PAL_M:
 392                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 393                         break;
 394                 case TV_STD_PAL_60:
 395                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 396                         break;
 397                 case TV_STD_NTSC_J:
 398                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 399                         break;
 400                 case TV_STD_SCART_PAL:
 401                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 402                         break;
 403                 case TV_STD_SECAM:
 404                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 405                         break;
 406                 case TV_STD_PAL_CN:
 407                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 408                         break;
 409                 default:
 410                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 411                         break;
 412                 }
 413         }
 414
 415         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 416
 417         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 418
 419 }
 420
 421 void
 422 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
 423 {
 424         struct drm_device *dev = encoder->dev;
 425         struct radeon_device *rdev = dev->dev_private;
 426         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 427         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
 428         int index = 0;
 429
 430         memset(&args, 0, sizeof(args));
 431
 432         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 433
 434         args.sXTmdsEncoder.ucEnable = action;
 435
 436         if (radeon_encoder->pixel_clock > 165000)
 437                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
 438
 439         /*if (pScrn->rgbBits == 8)*/
 440         args.sXTmdsEncoder.ucMisc |= (1 << 1);
 441
 442         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 443
 444 }
 445
 446 static void
 447 atombios_ddia_setup(struct drm_encoder *encoder, int action)
 448 {
 449         struct drm_device *dev = encoder->dev;
 450         struct radeon_device *rdev = dev->dev_private;
 451         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 452         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
 453         int index = 0;
 454
 455         memset(&args, 0, sizeof(args));
 456
 457         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 458
 459         args.sDVOEncoder.ucAction = action;
 460         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 461
 462         if (radeon_encoder->pixel_clock > 165000)
 463                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
 464
 465         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 466
 467 }
 468
 469 union lvds_encoder_control {
 470         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 471         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 472 };
 473
 474 void
 475 atombios_digital_setup(struct drm_encoder *encoder, int action)
 476 {
 477         struct drm_device *dev = encoder->dev;
 478         struct radeon_device *rdev = dev->dev_private;
 479         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 480         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 481         struct radeon_connector_atom_dig *dig_connector =
 482                 radeon_get_atom_connector_priv_from_encoder(encoder);
 483         union lvds_encoder_control args;
 484         int index = 0;
 485         int hdmi_detected = 0;
 486         uint8_t frev, crev;
 487
 488         if (!dig || !dig_connector)
 489                 return;
 490
 491         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 492                 hdmi_detected = 1;
 493
 494         memset(&args, 0, sizeof(args));
 495
 496         switch (radeon_encoder->encoder_id) {
 497         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 498                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 499                 break;
 500         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 501         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 502                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 503                 break;
 504         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 505                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 506                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 507                 else
 508                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 509                 break;
 510         }
 511
 512         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 513                 return;
 514
 515         switch (frev) {
 516         case 1:
 517         case 2:
 518                 switch (crev) {
 519                 case 1:
 520                         args.v1.ucMisc = 0;
 521                         args.v1.ucAction = action;
 522                         if (hdmi_detected)
 523                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 524                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 525                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 526                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 527                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 528                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 529                                         args.v1.ucMisc |= (1 << 1);
 530                         } else {
 531                                 if (dig_connector->linkb)
 532                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 533                                 if (radeon_encoder->pixel_clock > 165000)
 534                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 535                                 /*if (pScrn->rgbBits == 8) */
 536                                 args.v1.ucMisc |= (1 << 1);
 537                         }
 538                         break;
 539                 case 2:
 540                 case 3:
 541                         args.v2.ucMisc = 0;
 542                         args.v2.ucAction = action;
 543                         if (crev == 3) {
 544                                 if (dig->coherent_mode)
 545                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 546                         }
 547                         if (hdmi_detected)
 548                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 549                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 550                         args.v2.ucTruncate = 0;
 551                         args.v2.ucSpatial = 0;
 552                         args.v2.ucTemporal = 0;
 553                         args.v2.ucFRC = 0;
 554                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 555                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
 556                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 557                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
 558                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 559                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 560                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 561                                 }
 562                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
 563                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 564                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
 565                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 566                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 567                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 568                                 }
 569                         } else {
 570                                 if (dig_connector->linkb)
 571                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 572                                 if (radeon_encoder->pixel_clock > 165000)
 573                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 574                         }
 575                         break;
 576                 default:
 577                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 578                         break;
 579                 }
 580                 break;
 581         default:
 582                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 583                 break;
 584         }
 585
 586         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 587 }
 588
 589 int
 590 atombios_get_encoder_mode(struct drm_encoder *encoder)
 591 {
 592         struct drm_connector *connector;
 593         struct radeon_connector *radeon_connector;
 594         struct radeon_connector_atom_dig *dig_connector;
 595
 596         connector = radeon_get_connector_for_encoder(encoder);
 597         if (!connector)
 598                 return 0;
 599
 600         radeon_connector = to_radeon_connector(connector);
 601
 602         switch (connector->connector_type) {
 603         case DRM_MODE_CONNECTOR_DVII:
 604         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 605                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 606                         return ATOM_ENCODER_MODE_HDMI;
 607                 else if (radeon_connector->use_digital)
 608                         return ATOM_ENCODER_MODE_DVI;
 609                 else
 610                         return ATOM_ENCODER_MODE_CRT;
 611                 break;
 612         case DRM_MODE_CONNECTOR_DVID:
 613         case DRM_MODE_CONNECTOR_HDMIA:
 614         default:
 615                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
 616                         return ATOM_ENCODER_MODE_HDMI;
 617                 else
 618                         return ATOM_ENCODER_MODE_DVI;
 619                 break;
 620         case DRM_MODE_CONNECTOR_LVDS:
 621                 return ATOM_ENCODER_MODE_LVDS;
 622                 break;
 623         case DRM_MODE_CONNECTOR_DisplayPort:
 624         case DRM_MODE_CONNECTOR_eDP:
 625                 dig_connector = radeon_connector->con_priv;
 626                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 627                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 628                         return ATOM_ENCODER_MODE_DP;
 629                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
 630                         return ATOM_ENCODER_MODE_HDMI;
 631                 else
 632                         return ATOM_ENCODER_MODE_DVI;
 633                 break;
 634         case DRM_MODE_CONNECTOR_DVIA:
 635         case DRM_MODE_CONNECTOR_VGA:
 636                 return ATOM_ENCODER_MODE_CRT;
 637                 break;
 638         case DRM_MODE_CONNECTOR_Composite:
 639         case DRM_MODE_CONNECTOR_SVIDEO:
 640         case DRM_MODE_CONNECTOR_9PinDIN:
 641                 /* fix me */
 642                 return ATOM_ENCODER_MODE_TV;
 643                 /*return ATOM_ENCODER_MODE_CV;*/
 644                 break;
 645         }
 646 }
 647
 648 /*
 649  * DIG Encoder/Transmitter Setup
 650  *
 651  * DCE 3.0/3.1
 652  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 653  * Supports up to 3 digital outputs
 654  * - 2 DIG encoder blocks.
 655  * DIG1 can drive UNIPHY link A or link B
 656  * DIG2 can drive UNIPHY link B or LVTMA
 657  *
 658  * DCE 3.2
 659  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 660  * Supports up to 5 digital outputs
 661  * - 2 DIG encoder blocks.
 662  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 663  *
 664  * DCE 4.0
 665  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
 666  * Supports up to 6 digital outputs
 667  * - 6 DIG encoder blocks.
 668  * - DIG to PHY mapping is hardcoded
 669  * DIG1 drives UNIPHY0 link A, A+B
 670  * DIG2 drives UNIPHY0 link B
 671  * DIG3 drives UNIPHY1 link A, A+B
 672  * DIG4 drives UNIPHY1 link B
 673  * DIG5 drives UNIPHY2 link A, A+B
 674  * DIG6 drives UNIPHY2 link B
 675  *
 676  * Routing
 677  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 678  * Examples:
 679  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 680  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 681  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 682  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 683  */
 684
 685 union dig_encoder_control {
 686         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 687         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 688         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 689 };
 690
 691 void
 692 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 693 {
 694         struct drm_device *dev = encoder->dev;
 695         struct radeon_device *rdev = dev->dev_private;
 696         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 697         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 698         struct radeon_connector_atom_dig *dig_connector =
 699                 radeon_get_atom_connector_priv_from_encoder(encoder);
 700         union dig_encoder_control args;
 701         int index = 0;
 702         uint8_t frev, crev;
 703
 704         if (!dig || !dig_connector)
 705                 return;
 706
 707         memset(&args, 0, sizeof(args));
 708
 709         if (ASIC_IS_DCE4(rdev))
 710                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 711         else {
 712                 if (dig->dig_encoder)
 713                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 714                 else
 715                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 716         }
 717
 718         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 719                 return;
 720
 721         args.v1.ucAction = action;
 722         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 723         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 724
 725         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 726                 if (dig_connector->dp_clock == 270000)
 727                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 728                 args.v1.ucLaneNum = dig_connector->dp_lane_count;
 729         } else if (radeon_encoder->pixel_clock > 165000)
 730                 args.v1.ucLaneNum = 8;
 731         else
 732                 args.v1.ucLaneNum = 4;
 733
 734         if (ASIC_IS_DCE4(rdev)) {
 735                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 736                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 737         } else {
 738                 switch (radeon_encoder->encoder_id) {
 739                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 740                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 741                         break;
 742                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 743                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 744                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 745                         break;
 746                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 747                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 748                         break;
 749                 }
 750                 if (dig_connector->linkb)
 751                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 752                 else
 753                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 754         }
 755
 756         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 757
 758 }
 759
 760 union dig_transmitter_control {
 761         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 762         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 763         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 764 };
 765
 766 void
 767 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 768 {
 769         struct drm_device *dev = encoder->dev;
 770         struct radeon_device *rdev = dev->dev_private;
 771         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 772         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 773         struct radeon_connector_atom_dig *dig_connector =
 774                 radeon_get_atom_connector_priv_from_encoder(encoder);
 775         struct drm_connector *connector;
 776         struct radeon_connector *radeon_connector;
 777         union dig_transmitter_control args;
 778         int index = 0;
 779         uint8_t frev, crev;
 780         bool is_dp = false;
 781         int pll_id = 0;
 782
 783         if (!dig || !dig_connector)
 784                 return;
 785
 786         connector = radeon_get_connector_for_encoder(encoder);
 787         radeon_connector = to_radeon_connector(connector);
 788
 789         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 790                 is_dp = true;
 791
 792         memset(&args, 0, sizeof(args));
 793
 794         if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
 795                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 796         else {
 797                 switch (radeon_encoder->encoder_id) {
 798                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 799                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
 800                         break;
 801                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 802                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
 803                         break;
 804                 }
 805         }
 806
 807         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 808                 return;
 809
 810         args.v1.ucAction = action;
 811         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 812                 args.v1.usInitInfo = radeon_connector->connector_object_id;
 813         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 814                 args.v1.asMode.ucLaneSel = lane_num;
 815                 args.v1.asMode.ucLaneSet = lane_set;
 816         } else {
 817                 if (is_dp)
 818                         args.v1.usPixelClock =
 819                                 cpu_to_le16(dig_connector->dp_clock / 10);
 820                 else if (radeon_encoder->pixel_clock > 165000)
 821                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 822                 else
 823                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 824         }
 825         if (ASIC_IS_DCE4(rdev)) {
 826                 if (is_dp)
 827                         args.v3.ucLaneNum = dig_connector->dp_lane_count;
 828                 else if (radeon_encoder->pixel_clock > 165000)
 829                         args.v3.ucLaneNum = 8;
 830                 else
 831                         args.v3.ucLaneNum = 4;
 832
 833                 if (dig_connector->linkb) {
 834                         args.v3.acConfig.ucLinkSel = 1;
 835                         args.v3.acConfig.ucEncoderSel = 1;
 836                 }
 837
 838                 /* Select the PLL for the PHY
 839                  * DP PHY should be clocked from external src if there is
 840                  * one.
 841                  */
 842                 if (encoder->crtc) {
 843                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 844                         pll_id = radeon_crtc->pll_id;
 845                 }
 846                 if (is_dp && rdev->clock.dp_extclk)
 847                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 848                 else
 849                         args.v3.acConfig.ucRefClkSource = pll_id;
 850
 851                 switch (radeon_encoder->encoder_id) {
 852                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 853                         args.v3.acConfig.ucTransmitterSel = 0;
 854                         break;
 855                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 856                         args.v3.acConfig.ucTransmitterSel = 1;
 857                         break;
 858                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 859                         args.v3.acConfig.ucTransmitterSel = 2;
 860                         break;
 861                 }
 862
 863                 if (is_dp)
 864                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 865                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 866                         if (dig->coherent_mode)
 867                                 args.v3.acConfig.fCoherentMode = 1;
 868                         if (radeon_encoder->pixel_clock > 165000)
 869                                 args.v3.acConfig.fDualLinkConnector = 1;
 870                 }
 871         } else if (ASIC_IS_DCE32(rdev)) {
 872                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 873                 if (dig_connector->linkb)
 874                         args.v2.acConfig.ucLinkSel = 1;
 875
 876                 switch (radeon_encoder->encoder_id) {
 877                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 878                         args.v2.acConfig.ucTransmitterSel = 0;
 879                         break;
 880                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 881                         args.v2.acConfig.ucTransmitterSel = 1;
 882                         break;
 883                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 884                         args.v2.acConfig.ucTransmitterSel = 2;
 885                         break;
 886                 }
 887
 888                 if (is_dp)
 889                         args.v2.acConfig.fCoherentMode = 1;
 890                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 891                         if (dig->coherent_mode)
 892                                 args.v2.acConfig.fCoherentMode = 1;
 893                         if (radeon_encoder->pixel_clock > 165000)
 894                                 args.v2.acConfig.fDualLinkConnector = 1;
 895                 }
 896         } else {
 897                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 898
 899                 if (dig->dig_encoder)
 900                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 901                 else
 902                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 903
 904                 if ((rdev->flags & RADEON_IS_IGP) &&
 905                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 906                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 907                                 if (dig_connector->igp_lane_info & 0x1)
 908                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 909                                 else if (dig_connector->igp_lane_info & 0x2)
 910                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 911                                 else if (dig_connector->igp_lane_info & 0x4)
 912                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 913                                 else if (dig_connector->igp_lane_info & 0x8)
 914                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 915                         } else {
 916                                 if (dig_connector->igp_lane_info & 0x3)
 917                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 918                                 else if (dig_connector->igp_lane_info & 0xc)
 919                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
 920                         }
 921                 }
 922
 923                 if (dig_connector->linkb)
 924                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
 925                 else
 926                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
 927
 928                 if (is_dp)
 929                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 930                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 931                         if (dig->coherent_mode)
 932                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
 933                         if (radeon_encoder->pixel_clock > 165000)
 934                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
 935                 }
 936         }
 937
 938         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 939 }
 940
 941 static void
 942 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
 943 {
 944         struct drm_device *dev = encoder->dev;
 945         struct radeon_device *rdev = dev->dev_private;
 946         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 947         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 948         ENABLE_YUV_PS_ALLOCATION args;
 949         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
 950         uint32_t temp, reg;
 951
 952         memset(&args, 0, sizeof(args));
 953
 954         if (rdev->family >= CHIP_R600)
 955                 reg = R600_BIOS_3_SCRATCH;
 956         else
 957                 reg = RADEON_BIOS_3_SCRATCH;
 958
 959         /* XXX: fix up scratch reg handling */
 960         temp = RREG32(reg);
 961         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 962                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
 963                              (radeon_crtc->crtc_id << 18)));
 964         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 965                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
 966         else
 967                 WREG32(reg, 0);
 968
 969         if (enable)
 970                 args.ucEnable = ATOM_ENABLE;
 971         args.ucCRTC = radeon_crtc->crtc_id;
 972
 973         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 974
 975         WREG32(reg, temp);
 976 }
 977
 978 static void
 979 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
 980 {
 981         struct drm_device *dev = encoder->dev;
 982         struct radeon_device *rdev = dev->dev_private;
 983         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 984         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 985         int index = 0;
 986         bool is_dig = false;
 987
 988         memset(&args, 0, sizeof(args));
 989
 990         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
 991                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
 992                   radeon_encoder->active_device);
 993         switch (radeon_encoder->encoder_id) {
 994         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 995         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 996                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
 997                 break;
 998         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 999         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1000         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1001         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1002                 is_dig = true;
1003                 break;
1004         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1005         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1006         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1007                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1008                 break;
1009         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1010                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1011                 break;
1012         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1013                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1014                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1015                 else
1016                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1017                 break;
1018         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1019         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1020                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1021                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1022                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1023                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1024                 else
1025                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1026                 break;
1027         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1028         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1029                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1030                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1031                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1032                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1033                 else
1034                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1035                 break;
1036         }
1037
1038         if (is_dig) {
1039                 switch (mode) {
1040                 case DRM_MODE_DPMS_ON:
1041                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1042                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1043
1044                                 dp_link_train(encoder, connector);
1045                                 if (ASIC_IS_DCE4(rdev))
1046                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1047                         }
1048                         if (!ASIC_IS_DCE4(rdev))
1049                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1050                         break;
1051                 case DRM_MODE_DPMS_STANDBY:
1052                 case DRM_MODE_DPMS_SUSPEND:
1053                 case DRM_MODE_DPMS_OFF:
1054                         if (!ASIC_IS_DCE4(rdev))
1055                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1056                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1057                                 if (ASIC_IS_DCE4(rdev))
1058                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1059                         }
1060                         break;
1061                 }
1062         } else {
1063                 switch (mode) {
1064                 case DRM_MODE_DPMS_ON:
1065                         args.ucAction = ATOM_ENABLE;
1066                         break;
1067                 case DRM_MODE_DPMS_STANDBY:
1068                 case DRM_MODE_DPMS_SUSPEND:
1069                 case DRM_MODE_DPMS_OFF:
1070                         args.ucAction = ATOM_DISABLE;
1071                         break;
1072                 }
1073                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1074         }
1075         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1076
1077         /* adjust pm to dpms change */
1078         radeon_pm_compute_clocks(rdev);
1079 }
1080
1081 union crtc_source_param {
1082         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1083         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1084 };
1085
1086 static void
1087 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1088 {
1089         struct drm_device *dev = encoder->dev;
1090         struct radeon_device *rdev = dev->dev_private;
1091         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1092         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1093         union crtc_source_param args;
1094         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1095         uint8_t frev, crev;
1096         struct radeon_encoder_atom_dig *dig;
1097
1098         memset(&args, 0, sizeof(args));
1099
1100         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1101                 return;
1102
1103         switch (frev) {
1104         case 1:
1105                 switch (crev) {
1106                 case 1:
1107                 default:
1108                         if (ASIC_IS_AVIVO(rdev))
1109                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1110                         else {
1111                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1112                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1113                                 } else {
1114                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1115                                 }
1116                         }
1117                         switch (radeon_encoder->encoder_id) {
1118                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1119                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1120                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1121                                 break;
1122                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1123                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1124                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1125                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1126                                 else
1127                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1128                                 break;
1129                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1130                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1131                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1132                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1133                                 break;
1134                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1135                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1136                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1137                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1138                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1139                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1140                                 else
1141                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1142                                 break;
1143                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1144                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1145                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1146                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1147                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1148                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1149                                 else
1150                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1151                                 break;
1152                         }
1153                         break;
1154                 case 2:
1155                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1156                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1157                         switch (radeon_encoder->encoder_id) {
1158                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1159                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1160                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1161                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1162                                 dig = radeon_encoder->enc_priv;
1163                                 switch (dig->dig_encoder) {
1164                                 case 0:
1165                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1166                                         break;
1167                                 case 1:
1168                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1169                                         break;
1170                                 case 2:
1171                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1172                                         break;
1173                                 case 3:
1174                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1175                                         break;
1176                                 case 4:
1177                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1178                                         break;
1179                                 case 5:
1180                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1181                                         break;
1182                                 }
1183                                 break;
1184                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1185                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1186                                 break;
1187                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1188                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1189                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1190                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1191                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1192                                 else
1193                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1194                                 break;
1195                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1196                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1197                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1198                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1199                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1200                                 else
1201                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1202                                 break;
1203                         }
1204                         break;
1205                 }
1206                 break;
1207         default:
1208                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1209                 break;
1210         }
1211
1212         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1213
1214         /* update scratch regs with new routing */
1215         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1216 }
1217
1218 static void
1219 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1220                               struct drm_display_mode *mode)
1221 {
1222         struct drm_device *dev = encoder->dev;
1223         struct radeon_device *rdev = dev->dev_private;
1224         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1226
1227         /* Funky macbooks */
1228         if ((dev->pdev->device == 0x71C5) &&
1229             (dev->pdev->subsystem_vendor == 0x106b) &&
1230             (dev->pdev->subsystem_device == 0x0080)) {
1231                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1232                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1233
1234                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1235                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1236
1237                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1238                 }
1239         }
1240
1241         /* set scaler clears this on some chips */
1242         /* XXX check DCE4 */
1243         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1244                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1245                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1246                                AVIVO_D1MODE_INTERLEAVE_EN);
1247         }
1248 }
1249
1250 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1251 {
1252         struct drm_device *dev = encoder->dev;
1253         struct radeon_device *rdev = dev->dev_private;
1254         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1255         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1256         struct drm_encoder *test_encoder;
1257         struct radeon_encoder_atom_dig *dig;
1258         uint32_t dig_enc_in_use = 0;
1259
1260         if (ASIC_IS_DCE4(rdev)) {
1261                 struct radeon_connector_atom_dig *dig_connector =
1262                         radeon_get_atom_connector_priv_from_encoder(encoder);
1263
1264                 switch (radeon_encoder->encoder_id) {
1265                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1266                         if (dig_connector->linkb)
1267                                 return 1;
1268                         else
1269                                 return 0;
1270                         break;
1271                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1272                         if (dig_connector->linkb)
1273                                 return 3;
1274                         else
1275                                 return 2;
1276                         break;
1277                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1278                         if (dig_connector->linkb)
1279                                 return 5;
1280                         else
1281                                 return 4;
1282                         break;
1283                 }
1284         }
1285
1286         /* on DCE32 and encoder can driver any block so just crtc id */
1287         if (ASIC_IS_DCE32(rdev)) {
1288                 return radeon_crtc->crtc_id;
1289         }
1290
1291         /* on DCE3 - LVTMA can only be driven by DIGB */
1292         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1293                 struct radeon_encoder *radeon_test_encoder;
1294
1295                 if (encoder == test_encoder)
1296                         continue;
1297
1298                 if (!radeon_encoder_is_digital(test_encoder))
1299                         continue;
1300
1301                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1302                 dig = radeon_test_encoder->enc_priv;
1303
1304                 if (dig->dig_encoder >= 0)
1305                         dig_enc_in_use |= (1 << dig->dig_encoder);
1306         }
1307
1308         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1309                 if (dig_enc_in_use & 0x2)
1310                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1311                 return 1;
1312         }
1313         if (!(dig_enc_in_use & 1))
1314                 return 0;
1315         return 1;
1316 }
1317
1318 static void
1319 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1320                              struct drm_display_mode *mode,
1321                              struct drm_display_mode *adjusted_mode)
1322 {
1323         struct drm_device *dev = encoder->dev;
1324         struct radeon_device *rdev = dev->dev_private;
1325         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1326
1327         radeon_encoder->pixel_clock = adjusted_mode->clock;
1328
1329         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1330                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1331                         atombios_yuv_setup(encoder, true);
1332                 else
1333                         atombios_yuv_setup(encoder, false);
1334         }
1335
1336         switch (radeon_encoder->encoder_id) {
1337         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1338         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1339         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1340         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1341                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1342                 break;
1343         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1344         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1345         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1346         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1347                 if (ASIC_IS_DCE4(rdev)) {
1348                         /* disable the transmitter */
1349                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1350                         /* setup and enable the encoder */
1351                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1352
1353                         /* init and enable the transmitter */
1354                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1355                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1356                 } else {
1357                         /* disable the encoder and transmitter */
1358                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1359                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1360
1361                         /* setup and enable the encoder and transmitter */
1362                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1363                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1364                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1365                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1366                 }
1367                 break;
1368         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1369                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1370                 break;
1371         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1372         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1373                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1374                 break;
1375         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1376         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1377         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1378         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1379                 atombios_dac_setup(encoder, ATOM_ENABLE);
1380                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1381                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1382                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1383                         else
1384                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1385                 }
1386                 break;
1387         }
1388         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1389
1390         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1391                 r600_hdmi_enable(encoder);
1392                 r600_hdmi_setmode(encoder, adjusted_mode);
1393         }
1394 }
1395
1396 static bool
1397 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1398 {
1399         struct drm_device *dev = encoder->dev;
1400         struct radeon_device *rdev = dev->dev_private;
1401         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1402         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1403
1404         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1405                                        ATOM_DEVICE_CV_SUPPORT |
1406                                        ATOM_DEVICE_CRT_SUPPORT)) {
1407                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1408                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1409                 uint8_t frev, crev;
1410
1411                 memset(&args, 0, sizeof(args));
1412
1413                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1414                         return false;
1415
1416                 args.sDacload.ucMisc = 0;
1417
1418                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1419                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1420                         args.sDacload.ucDacType = ATOM_DAC_A;
1421                 else
1422                         args.sDacload.ucDacType = ATOM_DAC_B;
1423
1424                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1425                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1426                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1427                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1428                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1429                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1430                         if (crev >= 3)
1431                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1432                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1433                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1434                         if (crev >= 3)
1435                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1436                 }
1437
1438                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1439
1440                 return true;
1441         } else
1442                 return false;
1443 }
1444
1445 static enum drm_connector_status
1446 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1447 {
1448         struct drm_device *dev = encoder->dev;
1449         struct radeon_device *rdev = dev->dev_private;
1450         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1451         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1452         uint32_t bios_0_scratch;
1453
1454         if (!atombios_dac_load_detect(encoder, connector)) {
1455                 DRM_DEBUG("detect returned false \n");
1456                 return connector_status_unknown;
1457         }
1458
1459         if (rdev->family >= CHIP_R600)
1460                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1461         else
1462                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1463
1464         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1465         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1466                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1467                         return connector_status_connected;
1468         }
1469         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1470                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1471                         return connector_status_connected;
1472         }
1473         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1474                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1475                         return connector_status_connected;
1476         }
1477         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1478                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1479                         return connector_status_connected; /* CTV */
1480                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1481                         return connector_status_connected; /* STV */
1482         }
1483         return connector_status_disconnected;
1484 }
1485
1486 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1487 {
1488         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1489
1490         if (radeon_encoder->active_device &
1491             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1492                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1493                 if (dig)
1494                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1495         }
1496
1497         radeon_atom_output_lock(encoder, true);
1498         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1499
1500         /* this is needed for the pll/ss setup to work correctly in some cases */
1501         atombios_set_encoder_crtc_source(encoder);
1502 }
1503
1504 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1505 {
1506         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1507         radeon_atom_output_lock(encoder, false);
1508 }
1509
1510 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1511 {
1512         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1513         struct radeon_encoder_atom_dig *dig;
1514         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1515
1516         if (radeon_encoder_is_digital(encoder)) {
1517                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1518                         r600_hdmi_disable(encoder);
1519                 dig = radeon_encoder->enc_priv;
1520                 dig->dig_encoder = -1;
1521         }
1522         radeon_encoder->active_device = 0;
1523 }
1524
1525 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1526         .dpms = radeon_atom_encoder_dpms,
1527         .mode_fixup = radeon_atom_mode_fixup,
1528         .prepare = radeon_atom_encoder_prepare,
1529         .mode_set = radeon_atom_encoder_mode_set,
1530         .commit = radeon_atom_encoder_commit,
1531         .disable = radeon_atom_encoder_disable,
1532         /* no detect for TMDS/LVDS yet */
1533 };
1534
1535 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1536         .dpms = radeon_atom_encoder_dpms,
1537         .mode_fixup = radeon_atom_mode_fixup,
1538         .prepare = radeon_atom_encoder_prepare,
1539         .mode_set = radeon_atom_encoder_mode_set,
1540         .commit = radeon_atom_encoder_commit,
1541         .detect = radeon_atom_dac_detect,
1542 };
1543
1544 void radeon_enc_destroy(struct drm_encoder *encoder)
1545 {
1546         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1547         kfree(radeon_encoder->enc_priv);
1548         drm_encoder_cleanup(encoder);
1549         kfree(radeon_encoder);
1550 }
1551
1552 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1553         .destroy = radeon_enc_destroy,
1554 };
1555
1556 struct radeon_encoder_atom_dac *
1557 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1558 {
1559         struct drm_device *dev = radeon_encoder->base.dev;
1560         struct radeon_device *rdev = dev->dev_private;
1561         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1562
1563         if (!dac)
1564                 return NULL;
1565
1566         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1567         return dac;
1568 }
1569
1570 struct radeon_encoder_atom_dig *
1571 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1572 {
1573         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1574
1575         if (!dig)
1576                 return NULL;
1577
1578         /* coherent mode by default */
1579         dig->coherent_mode = true;
1580         dig->dig_encoder = -1;
1581
1582         return dig;
1583 }
1584
1585 void
1586 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1587 {
1588         struct radeon_device *rdev = dev->dev_private;
1589         struct drm_encoder *encoder;
1590         struct radeon_encoder *radeon_encoder;
1591
1592         /* see if we already added it */
1593         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1594                 radeon_encoder = to_radeon_encoder(encoder);
1595                 if (radeon_encoder->encoder_id == encoder_id) {
1596                         radeon_encoder->devices |= supported_device;
1597                         return;
1598                 }
1599
1600         }
1601
1602         /* add a new one */
1603         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1604         if (!radeon_encoder)
1605                 return;
1606
1607         encoder = &radeon_encoder->base;
1608         switch (rdev->num_crtc) {
1609         case 1:
1610                 encoder->possible_crtcs = 0x1;
1611                 break;
1612         case 2:
1613         default:
1614                 encoder->possible_crtcs = 0x3;
1615                 break;
1616         case 6:
1617                 encoder->possible_crtcs = 0x3f;
1618                 break;
1619         }
1620
1621         radeon_encoder->enc_priv = NULL;
1622
1623         radeon_encoder->encoder_id = encoder_id;
1624         radeon_encoder->devices = supported_device;
1625         radeon_encoder->rmx_type = RMX_OFF;
1626
1627         switch (radeon_encoder->encoder_id) {
1628         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1629         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1630         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1631         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1632                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1633                         radeon_encoder->rmx_type = RMX_FULL;
1634                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1635                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1636                 } else {
1637                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1638                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1639                 }
1640                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1641                 break;
1642         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1643                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1644                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1645                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1646                 break;
1647         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1648         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1649         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1650                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1651                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1652                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1653                 break;
1654         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1655         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1656         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1657         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1658         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1659         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1660         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1661                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1662                         radeon_encoder->rmx_type = RMX_FULL;
1663                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1664                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1665                 } else {
1666                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1667                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1668                 }
1669                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1670                 break;
1671         }
1672 }