drivers/i2c/busses/i2c-amd8111.c

   1 /*
   2  * SMBus 2.0 driver for AMD-8111 IO-Hub.
   3  *
   4  * Copyright (c) 2002 Vojtech Pavlik
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation version 2.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/kernel.h>
  14 #include <linux/stddef.h>
  15 #include <linux/ioport.h>
  16 #include <linux/init.h>
  17 #include <linux/i2c.h>
  18 #include <linux/delay.h>
  19 #include <linux/acpi.h>
  20 #include <linux/slab.h>
  21 #include <asm/io.h>
  22
  23 MODULE_LICENSE("GPL");
  24 MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
  25 MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
  26
  27 struct amd_smbus {
  28         struct pci_dev *dev;
  29         struct i2c_adapter adapter;
  30         int base;
  31         int size;
  32 };
  33
  34 static struct pci_driver amd8111_driver;
  35
  36 /*
  37  * AMD PCI control registers definitions.
  38  */
  39
  40 #define AMD_PCI_MISC    0x48
  41
  42 #define AMD_PCI_MISC_SCI        0x04    /* deliver SCI */
  43 #define AMD_PCI_MISC_INT        0x02    /* deliver PCI IRQ */
  44 #define AMD_PCI_MISC_SPEEDUP    0x01    /* 16x clock speedup */
  45
  46 /*
  47  * ACPI 2.0 chapter 13 PCI interface definitions.
  48  */
  49
  50 #define AMD_EC_DATA     0x00    /* data register */
  51 #define AMD_EC_SC       0x04    /* status of controller */
  52 #define AMD_EC_CMD      0x04    /* command register */
  53 #define AMD_EC_ICR      0x08    /* interrupt control register */
  54
  55 #define AMD_EC_SC_SMI   0x04    /* smi event pending */
  56 #define AMD_EC_SC_SCI   0x02    /* sci event pending */
  57 #define AMD_EC_SC_BURST 0x01    /* burst mode enabled */
  58 #define AMD_EC_SC_CMD   0x08    /* byte in data reg is command */
  59 #define AMD_EC_SC_IBF   0x02    /* data ready for embedded controller */
  60 #define AMD_EC_SC_OBF   0x01    /* data ready for host */
  61
  62 #define AMD_EC_CMD_RD   0x80    /* read EC */
  63 #define AMD_EC_CMD_WR   0x81    /* write EC */
  64 #define AMD_EC_CMD_BE   0x82    /* enable burst mode */
  65 #define AMD_EC_CMD_BD   0x83    /* disable burst mode */
  66 #define AMD_EC_CMD_QR   0x84    /* query EC */
  67
  68 /*
  69  * ACPI 2.0 chapter 13 access of registers of the EC
  70  */
  71
  72 static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
  73 {
  74         int timeout = 500;
  75
  76         while ((inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF) && --timeout)
  77                 udelay(1);
  78
  79         if (!timeout) {
  80                 dev_warn(&smbus->dev->dev,
  81                          "Timeout while waiting for IBF to clear\n");
  82                 return -ETIMEDOUT;
  83         }
  84
  85         return 0;
  86 }
  87
  88 static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
  89 {
  90         int timeout = 500;
  91
  92         while ((~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF) && --timeout)
  93                 udelay(1);
  94
  95         if (!timeout) {
  96                 dev_warn(&smbus->dev->dev,
  97                          "Timeout while waiting for OBF to set\n");
  98                 return -ETIMEDOUT;
  99         }
 100
 101         return 0;
 102 }
 103
 104 static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address,
 105                 unsigned char *data)
 106 {
 107         int status;
 108
 109         status = amd_ec_wait_write(smbus);
 110         if (status)
 111                 return status;
 112         outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
 113
 114         status = amd_ec_wait_write(smbus);
 115         if (status)
 116                 return status;
 117         outb(address, smbus->base + AMD_EC_DATA);
 118
 119         status = amd_ec_wait_read(smbus);
 120         if (status)
 121                 return status;
 122         *data = inb(smbus->base + AMD_EC_DATA);
 123
 124         return 0;
 125 }
 126
 127 static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address,
 128                 unsigned char data)
 129 {
 130         int status;
 131
 132         status = amd_ec_wait_write(smbus);
 133         if (status)
 134                 return status;
 135         outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
 136
 137         status = amd_ec_wait_write(smbus);
 138         if (status)
 139                 return status;
 140         outb(address, smbus->base + AMD_EC_DATA);
 141
 142         status = amd_ec_wait_write(smbus);
 143         if (status)
 144                 return status;
 145         outb(data, smbus->base + AMD_EC_DATA);
 146
 147         return 0;
 148 }
 149
 150 /*
 151  * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
 152  */
 153
 154 #define AMD_SMB_PRTCL   0x00    /* protocol, PEC */
 155 #define AMD_SMB_STS     0x01    /* status */
 156 #define AMD_SMB_ADDR    0x02    /* address */
 157 #define AMD_SMB_CMD     0x03    /* command */
 158 #define AMD_SMB_DATA    0x04    /* 32 data registers */
 159 #define AMD_SMB_BCNT    0x24    /* number of data bytes */
 160 #define AMD_SMB_ALRM_A  0x25    /* alarm address */
 161 #define AMD_SMB_ALRM_D  0x26    /* 2 bytes alarm data */
 162
 163 #define AMD_SMB_STS_DONE        0x80
 164 #define AMD_SMB_STS_ALRM        0x40
 165 #define AMD_SMB_STS_RES         0x20
 166 #define AMD_SMB_STS_STATUS      0x1f
 167
 168 #define AMD_SMB_STATUS_OK       0x00
 169 #define AMD_SMB_STATUS_FAIL     0x07
 170 #define AMD_SMB_STATUS_DNAK     0x10
 171 #define AMD_SMB_STATUS_DERR     0x11
 172 #define AMD_SMB_STATUS_CMD_DENY 0x12
 173 #define AMD_SMB_STATUS_UNKNOWN  0x13
 174 #define AMD_SMB_STATUS_ACC_DENY 0x17
 175 #define AMD_SMB_STATUS_TIMEOUT  0x18
 176 #define AMD_SMB_STATUS_NOTSUP   0x19
 177 #define AMD_SMB_STATUS_BUSY     0x1A
 178 #define AMD_SMB_STATUS_PEC      0x1F
 179
 180 #define AMD_SMB_PRTCL_WRITE             0x00
 181 #define AMD_SMB_PRTCL_READ              0x01
 182 #define AMD_SMB_PRTCL_QUICK             0x02
 183 #define AMD_SMB_PRTCL_BYTE              0x04
 184 #define AMD_SMB_PRTCL_BYTE_DATA         0x06
 185 #define AMD_SMB_PRTCL_WORD_DATA         0x08
 186 #define AMD_SMB_PRTCL_BLOCK_DATA        0x0a
 187 #define AMD_SMB_PRTCL_PROC_CALL         0x0c
 188 #define AMD_SMB_PRTCL_BLOCK_PROC_CALL   0x0d
 189 #define AMD_SMB_PRTCL_I2C_BLOCK_DATA    0x4a
 190 #define AMD_SMB_PRTCL_PEC               0x80
 191
 192
 193 static s32 amd8111_access(struct i2c_adapter * adap, u16 addr,
 194                 unsigned short flags, char read_write, u8 command, int size,
 195                 union i2c_smbus_data * data)
 196 {
 197         struct amd_smbus *smbus = adap->algo_data;
 198         unsigned char protocol, len, pec, temp[2];
 199         int i;
 200
 201         protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ
 202                                                   : AMD_SMB_PRTCL_WRITE;
 203         pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
 204
 205         switch (size) {
 206                 case I2C_SMBUS_QUICK:
 207                         protocol |= AMD_SMB_PRTCL_QUICK;
 208                         read_write = I2C_SMBUS_WRITE;
 209                         break;
 210
 211                 case I2C_SMBUS_BYTE:
 212                         if (read_write == I2C_SMBUS_WRITE)
 213                                 amd_ec_write(smbus, AMD_SMB_CMD, command);
 214                         protocol |= AMD_SMB_PRTCL_BYTE;
 215                         break;
 216
 217                 case I2C_SMBUS_BYTE_DATA:
 218                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 219                         if (read_write == I2C_SMBUS_WRITE)
 220                                 amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
 221                         protocol |= AMD_SMB_PRTCL_BYTE_DATA;
 222                         break;
 223
 224                 case I2C_SMBUS_WORD_DATA:
 225                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 226                         if (read_write == I2C_SMBUS_WRITE) {
 227                                 amd_ec_write(smbus, AMD_SMB_DATA,
 228                                              data->word & 0xff);
 229                                 amd_ec_write(smbus, AMD_SMB_DATA + 1,
 230                                              data->word >> 8);
 231                         }
 232                         protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
 233                         break;
 234
 235                 case I2C_SMBUS_BLOCK_DATA:
 236                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 237                         if (read_write == I2C_SMBUS_WRITE) {
 238                                 len = min_t(u8, data->block[0],
 239                                             I2C_SMBUS_BLOCK_MAX);
 240                                 amd_ec_write(smbus, AMD_SMB_BCNT, len);
 241                                 for (i = 0; i < len; i++)
 242                                         amd_ec_write(smbus, AMD_SMB_DATA + i,
 243                                                      data->block[i + 1]);
 244                         }
 245                         protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
 246                         break;
 247
 248                 case I2C_SMBUS_I2C_BLOCK_DATA:
 249                         len = min_t(u8, data->block[0],
 250                                     I2C_SMBUS_BLOCK_MAX);
 251                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 252                         amd_ec_write(smbus, AMD_SMB_BCNT, len);
 253                         if (read_write == I2C_SMBUS_WRITE)
 254                                 for (i = 0; i < len; i++)
 255                                         amd_ec_write(smbus, AMD_SMB_DATA + i,
 256                                                      data->block[i + 1]);
 257                         protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
 258                         break;
 259
 260                 case I2C_SMBUS_PROC_CALL:
 261                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 262                         amd_ec_write(smbus, AMD_SMB_DATA, data->word & 0xff);
 263                         amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
 264                         protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
 265                         read_write = I2C_SMBUS_READ;
 266                         break;
 267
 268                 case I2C_SMBUS_BLOCK_PROC_CALL:
 269                         len = min_t(u8, data->block[0],
 270                                     I2C_SMBUS_BLOCK_MAX - 1);
 271                         amd_ec_write(smbus, AMD_SMB_CMD, command);
 272                         amd_ec_write(smbus, AMD_SMB_BCNT, len);
 273                         for (i = 0; i < len; i++)
 274                                 amd_ec_write(smbus, AMD_SMB_DATA + i,
 275                                              data->block[i + 1]);
 276                         protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
 277                         read_write = I2C_SMBUS_READ;
 278                         break;
 279
 280                 default:
 281                         dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 282                         return -EOPNOTSUPP;
 283         }
 284
 285         amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
 286         amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
 287
 288         /* FIXME this discards status from ec_read(); so temp[0] will
 289          * hold stack garbage ... the rest of this routine will act
 290          * nonsensically.  Ignored ec_write() status might explain
 291          * some such failures...
 292          */
 293         amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
 294
 295         if (~temp[0] & AMD_SMB_STS_DONE) {
 296                 udelay(500);
 297                 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
 298         }
 299
 300         if (~temp[0] & AMD_SMB_STS_DONE) {
 301                 msleep(1);
 302                 amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
 303         }
 304
 305         if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
 306                 return -EIO;
 307
 308         if (read_write == I2C_SMBUS_WRITE)
 309                 return 0;
 310
 311         switch (size) {
 312                 case I2C_SMBUS_BYTE:
 313                 case I2C_SMBUS_BYTE_DATA:
 314                         amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
 315                         break;
 316
 317                 case I2C_SMBUS_WORD_DATA:
 318                 case I2C_SMBUS_PROC_CALL:
 319                         amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
 320                         amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
 321                         data->word = (temp[1] << 8) | temp[0];
 322                         break;
 323
 324                 case I2C_SMBUS_BLOCK_DATA:
 325                 case I2C_SMBUS_BLOCK_PROC_CALL:
 326                         amd_ec_read(smbus, AMD_SMB_BCNT, &len);
 327                         len = min_t(u8, len, I2C_SMBUS_BLOCK_MAX);
 328                 case I2C_SMBUS_I2C_BLOCK_DATA:
 329                         for (i = 0; i < len; i++)
 330                                 amd_ec_read(smbus, AMD_SMB_DATA + i,
 331                                             data->block + i + 1);
 332                         data->block[0] = len;
 333                         break;
 334         }
 335
 336         return 0;
 337 }
 338
 339
 340 static u32 amd8111_func(struct i2c_adapter *adapter)
 341 {
 342         return  I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 343                 I2C_FUNC_SMBUS_BYTE_DATA |
 344                 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
 345                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
 346                 I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_PEC;
 347 }
 348
 349 static const struct i2c_algorithm smbus_algorithm = {
 350         .smbus_xfer = amd8111_access,
 351         .functionality = amd8111_func,
 352 };
 353
 354
 355 static const struct pci_device_id amd8111_ids[] = {
 356         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
 357         { 0, }
 358 };
 359
 360 MODULE_DEVICE_TABLE (pci, amd8111_ids);
 361
 362 static int __devinit amd8111_probe(struct pci_dev *dev,
 363                 const struct pci_device_id *id)
 364 {
 365         struct amd_smbus *smbus;
 366         int error;
 367
 368         if (!(pci_resource_flags(dev, 0) & IORESOURCE_IO))
 369                 return -ENODEV;
 370
 371         smbus = kzalloc(sizeof(struct amd_smbus), GFP_KERNEL);
 372         if (!smbus)
 373                 return -ENOMEM;
 374
 375         smbus->dev = dev;
 376         smbus->base = pci_resource_start(dev, 0);
 377         smbus->size = pci_resource_len(dev, 0);
 378
 379         error = acpi_check_resource_conflict(&dev->resource[0]);
 380         if (error) {
 381                 error = -ENODEV;
 382                 goto out_kfree;
 383         }
 384
 385         if (!request_region(smbus->base, smbus->size, amd8111_driver.name)) {
 386                 error = -EBUSY;
 387                 goto out_kfree;
 388         }
 389
 390         smbus->adapter.owner = THIS_MODULE;
 391         snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
 392                 "SMBus2 AMD8111 adapter at %04x", smbus->base);
 393         smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 394         smbus->adapter.algo = &smbus_algorithm;
 395         smbus->adapter.algo_data = smbus;
 396
 397         /* set up the sysfs linkage to our parent device */
 398         smbus->adapter.dev.parent = &dev->dev;
 399
 400         pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
 401         error = i2c_add_adapter(&smbus->adapter);
 402         if (error)
 403                 goto out_release_region;
 404
 405         pci_set_drvdata(dev, smbus);
 406         return 0;
 407
 408  out_release_region:
 409         release_region(smbus->base, smbus->size);
 410  out_kfree:
 411         kfree(smbus);
 412         return error;
 413 }
 414
 415 static void __devexit amd8111_remove(struct pci_dev *dev)
 416 {
 417         struct amd_smbus *smbus = pci_get_drvdata(dev);
 418
 419         i2c_del_adapter(&smbus->adapter);
 420         release_region(smbus->base, smbus->size);
 421         kfree(smbus);
 422 }
 423
 424 static struct pci_driver amd8111_driver = {
 425         .name           = "amd8111_smbus2",
 426         .id_table       = amd8111_ids,
 427         .probe          = amd8111_probe,
 428         .remove         = __devexit_p(amd8111_remove),
 429 };
 430
 431 static int __init i2c_amd8111_init(void)
 432 {
 433         return pci_register_driver(&amd8111_driver);
 434 }
 435
 436 static void __exit i2c_amd8111_exit(void)
 437 {
 438         pci_unregister_driver(&amd8111_driver);
 439 }
 440
 441 module_init(i2c_amd8111_init);
 442 module_exit(i2c_amd8111_exit);