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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / net / bnx2x.h
blob3c48a7a683086fecf1b5b3eba52e0de89af7d016
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2010 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
28 #define BCM_CNIC 1
29 #include "cnic_if.h"
30 #endif
31
32 #define BNX2X_MULTI_QUEUE
33
34 #define BNX2X_NEW_NAPI
35
36
37
38 #include <linux/mdio.h>
39 #include "bnx2x_reg.h"
40 #include "bnx2x_fw_defs.h"
41 #include "bnx2x_hsi.h"
42 #include "bnx2x_link.h"
43
44 /* error/debug prints */
45
46 #define DRV_MODULE_NAME "bnx2x"
47
48 /* for messages that are currently off */
49 #define BNX2X_MSG_OFF 0
50 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
51 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
52 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
53 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
54 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
55 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
56
57 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
58
59 /* regular debug print */
60 #define DP(__mask, __fmt, __args...) \
61 do { \
62 if (bp->msg_enable & (__mask)) \
63 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
64 __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", \
66 ##__args); \
67 } while (0)
68
69 /* errors debug print */
70 #define BNX2X_DBG_ERR(__fmt, __args...) \
71 do { \
72 if (netif_msg_probe(bp)) \
73 pr_err("[%s:%d(%s)]" __fmt, \
74 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \
76 ##__args); \
77 } while (0)
78
79 /* for errors (never masked) */
80 #define BNX2X_ERR(__fmt, __args...) \
81 do { \
82 pr_err("[%s:%d(%s)]" __fmt, \
83 __func__, __LINE__, \
84 bp->dev ? (bp->dev->name) : "?", \
85 ##__args); \
86 } while (0)
87
88 /* before we have a dev->name use dev_info() */
89 #define BNX2X_DEV_INFO(__fmt, __args...) \
90 do { \
91 if (netif_msg_probe(bp)) \
92 dev_info(&bp->pdev->dev, __fmt, ##__args); \
93 } while (0)
94
95
96 #ifdef BNX2X_STOP_ON_ERROR
97 #define bnx2x_panic() do { \
98 bp->panic = 1; \
99 BNX2X_ERR("driver assert\n"); \
100 bnx2x_int_disable(bp); \
101 bnx2x_panic_dump(bp); \
102 } while (0)
103 #else
104 #define bnx2x_panic() do { \
105 bp->panic = 1; \
106 BNX2X_ERR("driver assert\n"); \
107 bnx2x_panic_dump(bp); \
108 } while (0)
109 #endif
110
111
112 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
113 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
114 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
115
116
117 #define REG_ADDR(bp, offset) (bp->regview + offset)
118
119 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
120 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
121
122 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
123 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
124 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
125
126 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
127 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
128
129 #define REG_RD_DMAE(bp, offset, valp, len32) \
130 do { \
131 bnx2x_read_dmae(bp, offset, len32);\
132 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
133 } while (0)
134
135 #define REG_WR_DMAE(bp, offset, valp, len32) \
136 do { \
137 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
138 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
139 offset, len32); \
140 } while (0)
141
142 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
143 do { \
144 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
145 bnx2x_write_big_buf_wb(bp, addr, len32); \
146 } while (0)
147
148 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
149 offsetof(struct shmem_region, field))
150 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
151 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
152
153 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
154 offsetof(struct shmem2_region, field))
155 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
156 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
157
158 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
159 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
160
161
162 /* fast path */
163
164 struct sw_rx_bd {
165 struct sk_buff *skb;
166 DECLARE_PCI_UNMAP_ADDR(mapping)
167 };
168
169 struct sw_tx_bd {
170 struct sk_buff *skb;
171 u16 first_bd;
172 u8 flags;
173 /* Set on the first BD descriptor when there is a split BD */
174 #define BNX2X_TSO_SPLIT_BD (1<<0)
175 };
176
177 struct sw_rx_page {
178 struct page *page;
179 DECLARE_PCI_UNMAP_ADDR(mapping)
180 };
181
182 union db_prod {
183 struct doorbell_set_prod data;
184 u32 raw;
185 };
186
187
188 /* MC hsi */
189 #define BCM_PAGE_SHIFT 12
190 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
191 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
192 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
193
194 #define PAGES_PER_SGE_SHIFT 0
195 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
196 #define SGE_PAGE_SIZE PAGE_SIZE
197 #define SGE_PAGE_SHIFT PAGE_SHIFT
198 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
199
200 /* SGE ring related macros */
201 #define NUM_RX_SGE_PAGES 2
202 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
203 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
204 /* RX_SGE_CNT is promised to be a power of 2 */
205 #define RX_SGE_MASK (RX_SGE_CNT - 1)
206 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
207 #define MAX_RX_SGE (NUM_RX_SGE - 1)
208 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
209 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
210 #define RX_SGE(x) ((x) & MAX_RX_SGE)
211
212 /* SGE producer mask related macros */
213 /* Number of bits in one sge_mask array element */
214 #define RX_SGE_MASK_ELEM_SZ 64
215 #define RX_SGE_MASK_ELEM_SHIFT 6
216 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
217
218 /* Creates a bitmask of all ones in less significant bits.
219 idx - index of the most significant bit in the created mask */
220 #define RX_SGE_ONES_MASK(idx) \
221 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
222 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
223
224 /* Number of u64 elements in SGE mask array */
225 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
226 RX_SGE_MASK_ELEM_SZ)
227 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
228 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
229
230
231 struct bnx2x_eth_q_stats {
232 u32 total_bytes_received_hi;
233 u32 total_bytes_received_lo;
234 u32 total_bytes_transmitted_hi;
235 u32 total_bytes_transmitted_lo;
236 u32 total_unicast_packets_received_hi;
237 u32 total_unicast_packets_received_lo;
238 u32 total_multicast_packets_received_hi;
239 u32 total_multicast_packets_received_lo;
240 u32 total_broadcast_packets_received_hi;
241 u32 total_broadcast_packets_received_lo;
242 u32 total_unicast_packets_transmitted_hi;
243 u32 total_unicast_packets_transmitted_lo;
244 u32 total_multicast_packets_transmitted_hi;
245 u32 total_multicast_packets_transmitted_lo;
246 u32 total_broadcast_packets_transmitted_hi;
247 u32 total_broadcast_packets_transmitted_lo;
248 u32 valid_bytes_received_hi;
249 u32 valid_bytes_received_lo;
250
251 u32 error_bytes_received_hi;
252 u32 error_bytes_received_lo;
253 u32 etherstatsoverrsizepkts_hi;
254 u32 etherstatsoverrsizepkts_lo;
255 u32 no_buff_discard_hi;
256 u32 no_buff_discard_lo;
257
258 u32 driver_xoff;
259 u32 rx_err_discard_pkt;
260 u32 rx_skb_alloc_failed;
261 u32 hw_csum_err;
262 };
263
264 #define BNX2X_NUM_Q_STATS 11
265 #define Q_STATS_OFFSET32(stat_name) \
266 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
267
268 struct bnx2x_fastpath {
269
270 struct napi_struct napi;
271 struct host_status_block *status_blk;
272 dma_addr_t status_blk_mapping;
273
274 struct sw_tx_bd *tx_buf_ring;
275
276 union eth_tx_bd_types *tx_desc_ring;
277 dma_addr_t tx_desc_mapping;
278
279 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
280 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
281
282 struct eth_rx_bd *rx_desc_ring;
283 dma_addr_t rx_desc_mapping;
284
285 union eth_rx_cqe *rx_comp_ring;
286 dma_addr_t rx_comp_mapping;
287
288 /* SGE ring */
289 struct eth_rx_sge *rx_sge_ring;
290 dma_addr_t rx_sge_mapping;
291
292 u64 sge_mask[RX_SGE_MASK_LEN];
293
294 int state;
295 #define BNX2X_FP_STATE_CLOSED 0
296 #define BNX2X_FP_STATE_IRQ 0x80000
297 #define BNX2X_FP_STATE_OPENING 0x90000
298 #define BNX2X_FP_STATE_OPEN 0xa0000
299 #define BNX2X_FP_STATE_HALTING 0xb0000
300 #define BNX2X_FP_STATE_HALTED 0xc0000
301
302 u8 index; /* number in fp array */
303 u8 cl_id; /* eth client id */
304 u8 sb_id; /* status block number in HW */
305
306 union db_prod tx_db;
307
308 u16 tx_pkt_prod;
309 u16 tx_pkt_cons;
310 u16 tx_bd_prod;
311 u16 tx_bd_cons;
312 __le16 *tx_cons_sb;
313
314 __le16 fp_c_idx;
315 __le16 fp_u_idx;
316
317 u16 rx_bd_prod;
318 u16 rx_bd_cons;
319 u16 rx_comp_prod;
320 u16 rx_comp_cons;
321 u16 rx_sge_prod;
322 /* The last maximal completed SGE */
323 u16 last_max_sge;
324 __le16 *rx_cons_sb;
325 __le16 *rx_bd_cons_sb;
326
327
328 unsigned long tx_pkt,
329 rx_pkt,
330 rx_calls;
331
332 /* TPA related */
333 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
334 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
335 #define BNX2X_TPA_START 1
336 #define BNX2X_TPA_STOP 2
337 u8 disable_tpa;
338 #ifdef BNX2X_STOP_ON_ERROR
339 u64 tpa_queue_used;
340 #endif
341
342 struct tstorm_per_client_stats old_tclient;
343 struct ustorm_per_client_stats old_uclient;
344 struct xstorm_per_client_stats old_xclient;
345 struct bnx2x_eth_q_stats eth_q_stats;
346
347 /* The size is calculated using the following:
348 sizeof name field from netdev structure +
349 4 ('-Xx-' string) +
350 4 (for the digits and to make it DWORD aligned) */
351 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
352 char name[FP_NAME_SIZE];
353 struct bnx2x *bp; /* parent */
354 };
355
356 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
357
358
359 /* MC hsi */
360 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
361 #define RX_COPY_THRESH 92
362
363 #define NUM_TX_RINGS 16
364 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
365 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
366 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
367 #define MAX_TX_BD (NUM_TX_BD - 1)
368 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
369 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
370 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
371 #define TX_BD(x) ((x) & MAX_TX_BD)
372 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
373
374 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
375 #define NUM_RX_RINGS 8
376 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
377 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
378 #define RX_DESC_MASK (RX_DESC_CNT - 1)
379 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
380 #define MAX_RX_BD (NUM_RX_BD - 1)
381 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
382 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
383 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
384 #define RX_BD(x) ((x) & MAX_RX_BD)
385
386 /* As long as CQE is 4 times bigger than BD entry we have to allocate
387 4 times more pages for CQ ring in order to keep it balanced with
388 BD ring */
389 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
390 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
391 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
392 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
393 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
394 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
395 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
396 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
397 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
398
399
400 /* This is needed for determining of last_max */
401 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
402
403 #define __SGE_MASK_SET_BIT(el, bit) \
404 do { \
405 el = ((el) | ((u64)0x1 << (bit))); \
406 } while (0)
407
408 #define __SGE_MASK_CLEAR_BIT(el, bit) \
409 do { \
410 el = ((el) & (~((u64)0x1 << (bit)))); \
411 } while (0)
412
413 #define SGE_MASK_SET_BIT(fp, idx) \
414 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
415 ((idx) & RX_SGE_MASK_ELEM_MASK))
416
417 #define SGE_MASK_CLEAR_BIT(fp, idx) \
418 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
419 ((idx) & RX_SGE_MASK_ELEM_MASK))
420
421
422 /* used on a CID received from the HW */
423 #define SW_CID(x) (le32_to_cpu(x) & \
424 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
425 #define CQE_CMD(x) (le32_to_cpu(x) >> \
426 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
427
428 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
429 le32_to_cpu((bd)->addr_lo))
430 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
431
432
433 #define DPM_TRIGER_TYPE 0x40
434 #define DOORBELL(bp, cid, val) \
435 do { \
436 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
437 DPM_TRIGER_TYPE); \
438 } while (0)
439
440
441 /* TX CSUM helpers */
442 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
443 skb->csum_offset)
444 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
445 skb->csum_offset))
446
447 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
448
449 #define XMIT_PLAIN 0
450 #define XMIT_CSUM_V4 0x1
451 #define XMIT_CSUM_V6 0x2
452 #define XMIT_CSUM_TCP 0x4
453 #define XMIT_GSO_V4 0x8
454 #define XMIT_GSO_V6 0x10
455
456 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
457 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
458
459
460 /* stuff added to make the code fit 80Col */
461
462 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
463
464 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
465 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
466 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
467 (TPA_TYPE_START | TPA_TYPE_END))
468
469 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
470
471 #define BNX2X_IP_CSUM_ERR(cqe) \
472 (!((cqe)->fast_path_cqe.status_flags & \
473 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
474 ((cqe)->fast_path_cqe.type_error_flags & \
475 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
476
477 #define BNX2X_L4_CSUM_ERR(cqe) \
478 (!((cqe)->fast_path_cqe.status_flags & \
479 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
480 ((cqe)->fast_path_cqe.type_error_flags & \
481 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
482
483 #define BNX2X_RX_CSUM_OK(cqe) \
484 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
485
486 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
487 (((le16_to_cpu(flags) & \
488 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
489 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
490 == PRS_FLAG_OVERETH_IPV4)
491 #define BNX2X_RX_SUM_FIX(cqe) \
492 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
493
494
495 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
496 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
497
498 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
499 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
500 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
501
502 #define BNX2X_RX_SB_INDEX \
503 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
504
505 #define BNX2X_RX_SB_BD_INDEX \
506 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
507
508 #define BNX2X_RX_SB_INDEX_NUM \
509 (((U_SB_ETH_RX_CQ_INDEX << \
510 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
511 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
512 ((U_SB_ETH_RX_BD_INDEX << \
513 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
514 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
515
516 #define BNX2X_TX_SB_INDEX \
517 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
518
519
520 /* end of fast path */
521
522 /* common */
523
524 struct bnx2x_common {
525
526 u32 chip_id;
527 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
528 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
529
530 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
531 #define CHIP_NUM_57710 0x164e
532 #define CHIP_NUM_57711 0x164f
533 #define CHIP_NUM_57711E 0x1650
534 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
535 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
536 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
537 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
538 CHIP_IS_57711E(bp))
539 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
540
541 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
542 #define CHIP_REV_Ax 0x00000000
543 /* assume maximum 5 revisions */
544 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
545 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
546 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
547 !(CHIP_REV(bp) & 0x00001000))
548 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
549 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
550 (CHIP_REV(bp) & 0x00001000))
551
552 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
553 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
554
555 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
556 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
557
558 int flash_size;
559 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
560 #define NVRAM_TIMEOUT_COUNT 30000
561 #define NVRAM_PAGE_SIZE 256
562
563 u32 shmem_base;
564 u32 shmem2_base;
565
566 u32 hw_config;
567
568 u32 bc_ver;
569 };
570
571
572 /* end of common */
573
574 /* port */
575
576 struct nig_stats {
577 u32 brb_discard;
578 u32 brb_packet;
579 u32 brb_truncate;
580 u32 flow_ctrl_discard;
581 u32 flow_ctrl_octets;
582 u32 flow_ctrl_packet;
583 u32 mng_discard;
584 u32 mng_octet_inp;
585 u32 mng_octet_out;
586 u32 mng_packet_inp;
587 u32 mng_packet_out;
588 u32 pbf_octets;
589 u32 pbf_packet;
590 u32 safc_inp;
591 u32 egress_mac_pkt0_lo;
592 u32 egress_mac_pkt0_hi;
593 u32 egress_mac_pkt1_lo;
594 u32 egress_mac_pkt1_hi;
595 };
596
597 struct bnx2x_port {
598 u32 pmf;
599
600 u32 link_config;
601
602 u32 supported;
603 /* link settings - missing defines */
604 #define SUPPORTED_2500baseX_Full (1 << 15)
605
606 u32 advertising;
607 /* link settings - missing defines */
608 #define ADVERTISED_2500baseX_Full (1 << 15)
609
610 u32 phy_addr;
611
612 /* used to synchronize phy accesses */
613 struct mutex phy_mutex;
614 int need_hw_lock;
615
616 u32 port_stx;
617
618 struct nig_stats old_nig_stats;
619 };
620
621 /* end of port */
622
623
624 enum bnx2x_stats_event {
625 STATS_EVENT_PMF = 0,
626 STATS_EVENT_LINK_UP,
627 STATS_EVENT_UPDATE,
628 STATS_EVENT_STOP,
629 STATS_EVENT_MAX
630 };
631
632 enum bnx2x_stats_state {
633 STATS_STATE_DISABLED = 0,
634 STATS_STATE_ENABLED,
635 STATS_STATE_MAX
636 };
637
638 struct bnx2x_eth_stats {
639 u32 total_bytes_received_hi;
640 u32 total_bytes_received_lo;
641 u32 total_bytes_transmitted_hi;
642 u32 total_bytes_transmitted_lo;
643 u32 total_unicast_packets_received_hi;
644 u32 total_unicast_packets_received_lo;
645 u32 total_multicast_packets_received_hi;
646 u32 total_multicast_packets_received_lo;
647 u32 total_broadcast_packets_received_hi;
648 u32 total_broadcast_packets_received_lo;
649 u32 total_unicast_packets_transmitted_hi;
650 u32 total_unicast_packets_transmitted_lo;
651 u32 total_multicast_packets_transmitted_hi;
652 u32 total_multicast_packets_transmitted_lo;
653 u32 total_broadcast_packets_transmitted_hi;
654 u32 total_broadcast_packets_transmitted_lo;
655 u32 valid_bytes_received_hi;
656 u32 valid_bytes_received_lo;
657
658 u32 error_bytes_received_hi;
659 u32 error_bytes_received_lo;
660 u32 etherstatsoverrsizepkts_hi;
661 u32 etherstatsoverrsizepkts_lo;
662 u32 no_buff_discard_hi;
663 u32 no_buff_discard_lo;
664
665 u32 rx_stat_ifhcinbadoctets_hi;
666 u32 rx_stat_ifhcinbadoctets_lo;
667 u32 tx_stat_ifhcoutbadoctets_hi;
668 u32 tx_stat_ifhcoutbadoctets_lo;
669 u32 rx_stat_dot3statsfcserrors_hi;
670 u32 rx_stat_dot3statsfcserrors_lo;
671 u32 rx_stat_dot3statsalignmenterrors_hi;
672 u32 rx_stat_dot3statsalignmenterrors_lo;
673 u32 rx_stat_dot3statscarriersenseerrors_hi;
674 u32 rx_stat_dot3statscarriersenseerrors_lo;
675 u32 rx_stat_falsecarriererrors_hi;
676 u32 rx_stat_falsecarriererrors_lo;
677 u32 rx_stat_etherstatsundersizepkts_hi;
678 u32 rx_stat_etherstatsundersizepkts_lo;
679 u32 rx_stat_dot3statsframestoolong_hi;
680 u32 rx_stat_dot3statsframestoolong_lo;
681 u32 rx_stat_etherstatsfragments_hi;
682 u32 rx_stat_etherstatsfragments_lo;
683 u32 rx_stat_etherstatsjabbers_hi;
684 u32 rx_stat_etherstatsjabbers_lo;
685 u32 rx_stat_maccontrolframesreceived_hi;
686 u32 rx_stat_maccontrolframesreceived_lo;
687 u32 rx_stat_bmac_xpf_hi;
688 u32 rx_stat_bmac_xpf_lo;
689 u32 rx_stat_bmac_xcf_hi;
690 u32 rx_stat_bmac_xcf_lo;
691 u32 rx_stat_xoffstateentered_hi;
692 u32 rx_stat_xoffstateentered_lo;
693 u32 rx_stat_xonpauseframesreceived_hi;
694 u32 rx_stat_xonpauseframesreceived_lo;
695 u32 rx_stat_xoffpauseframesreceived_hi;
696 u32 rx_stat_xoffpauseframesreceived_lo;
697 u32 tx_stat_outxonsent_hi;
698 u32 tx_stat_outxonsent_lo;
699 u32 tx_stat_outxoffsent_hi;
700 u32 tx_stat_outxoffsent_lo;
701 u32 tx_stat_flowcontroldone_hi;
702 u32 tx_stat_flowcontroldone_lo;
703 u32 tx_stat_etherstatscollisions_hi;
704 u32 tx_stat_etherstatscollisions_lo;
705 u32 tx_stat_dot3statssinglecollisionframes_hi;
706 u32 tx_stat_dot3statssinglecollisionframes_lo;
707 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
708 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
709 u32 tx_stat_dot3statsdeferredtransmissions_hi;
710 u32 tx_stat_dot3statsdeferredtransmissions_lo;
711 u32 tx_stat_dot3statsexcessivecollisions_hi;
712 u32 tx_stat_dot3statsexcessivecollisions_lo;
713 u32 tx_stat_dot3statslatecollisions_hi;
714 u32 tx_stat_dot3statslatecollisions_lo;
715 u32 tx_stat_etherstatspkts64octets_hi;
716 u32 tx_stat_etherstatspkts64octets_lo;
717 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
718 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
719 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
720 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
721 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
722 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
723 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
724 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
725 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
726 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
727 u32 tx_stat_etherstatspktsover1522octets_hi;
728 u32 tx_stat_etherstatspktsover1522octets_lo;
729 u32 tx_stat_bmac_2047_hi;
730 u32 tx_stat_bmac_2047_lo;
731 u32 tx_stat_bmac_4095_hi;
732 u32 tx_stat_bmac_4095_lo;
733 u32 tx_stat_bmac_9216_hi;
734 u32 tx_stat_bmac_9216_lo;
735 u32 tx_stat_bmac_16383_hi;
736 u32 tx_stat_bmac_16383_lo;
737 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
738 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
739 u32 tx_stat_bmac_ufl_hi;
740 u32 tx_stat_bmac_ufl_lo;
741
742 u32 pause_frames_received_hi;
743 u32 pause_frames_received_lo;
744 u32 pause_frames_sent_hi;
745 u32 pause_frames_sent_lo;
746
747 u32 etherstatspkts1024octetsto1522octets_hi;
748 u32 etherstatspkts1024octetsto1522octets_lo;
749 u32 etherstatspktsover1522octets_hi;
750 u32 etherstatspktsover1522octets_lo;
751
752 u32 brb_drop_hi;
753 u32 brb_drop_lo;
754 u32 brb_truncate_hi;
755 u32 brb_truncate_lo;
756
757 u32 mac_filter_discard;
758 u32 xxoverflow_discard;
759 u32 brb_truncate_discard;
760 u32 mac_discard;
761
762 u32 driver_xoff;
763 u32 rx_err_discard_pkt;
764 u32 rx_skb_alloc_failed;
765 u32 hw_csum_err;
766
767 u32 nig_timer_max;
768 };
769
770 #define BNX2X_NUM_STATS 41
771 #define STATS_OFFSET32(stat_name) \
772 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
773
774
775 #ifdef BCM_CNIC
776 #define MAX_CONTEXT 15
777 #else
778 #define MAX_CONTEXT 16
779 #endif
780
781 union cdu_context {
782 struct eth_context eth;
783 char pad[1024];
784 };
785
786 #define MAX_DMAE_C 8
787
788 /* DMA memory not used in fastpath */
789 struct bnx2x_slowpath {
790 union cdu_context context[MAX_CONTEXT];
791 struct eth_stats_query fw_stats;
792 struct mac_configuration_cmd mac_config;
793 struct mac_configuration_cmd mcast_config;
794
795 /* used by dmae command executer */
796 struct dmae_command dmae[MAX_DMAE_C];
797
798 u32 stats_comp;
799 union mac_stats mac_stats;
800 struct nig_stats nig_stats;
801 struct host_port_stats port_stats;
802 struct host_func_stats func_stats;
803 struct host_func_stats func_stats_base;
804
805 u32 wb_comp;
806 u32 wb_data[4];
807 };
808
809 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
810 #define bnx2x_sp_mapping(bp, var) \
811 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
812
813
814 /* attn group wiring */
815 #define MAX_DYNAMIC_ATTN_GRPS 8
816
817 struct attn_route {
818 u32 sig[4];
819 };
820
821 struct bnx2x {
822 /* Fields used in the tx and intr/napi performance paths
823 * are grouped together in the beginning of the structure
824 */
825 struct bnx2x_fastpath fp[MAX_CONTEXT];
826 void __iomem *regview;
827 void __iomem *doorbells;
828 #ifdef BCM_CNIC
829 #define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE)
830 #else
831 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
832 #endif
833
834 struct net_device *dev;
835 struct pci_dev *pdev;
836
837 atomic_t intr_sem;
838 #ifdef BCM_CNIC
839 struct msix_entry msix_table[MAX_CONTEXT+2];
840 #else
841 struct msix_entry msix_table[MAX_CONTEXT+1];
842 #endif
843 #define INT_MODE_INTx 1
844 #define INT_MODE_MSI 2
845 #define INT_MODE_MSIX 3
846
847 int tx_ring_size;
848
849 #ifdef BCM_VLAN
850 struct vlan_group *vlgrp;
851 #endif
852
853 u32 rx_csum;
854 u32 rx_buf_size;
855 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
856 #define ETH_MIN_PACKET_SIZE 60
857 #define ETH_MAX_PACKET_SIZE 1500
858 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
859
860 /* Max supported alignment is 256 (8 shift) */
861 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
862 L1_CACHE_SHIFT : 8)
863 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
864
865 struct host_def_status_block *def_status_blk;
866 #define DEF_SB_ID 16
867 __le16 def_c_idx;
868 __le16 def_u_idx;
869 __le16 def_x_idx;
870 __le16 def_t_idx;
871 __le16 def_att_idx;
872 u32 attn_state;
873 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
874
875 /* slow path ring */
876 struct eth_spe *spq;
877 dma_addr_t spq_mapping;
878 u16 spq_prod_idx;
879 struct eth_spe *spq_prod_bd;
880 struct eth_spe *spq_last_bd;
881 __le16 *dsb_sp_prod;
882 u16 spq_left; /* serialize spq */
883 /* used to synchronize spq accesses */
884 spinlock_t spq_lock;
885
886 /* Flags for marking that there is a STAT_QUERY or
887 SET_MAC ramrod pending */
888 int stats_pending;
889 int set_mac_pending;
890
891 /* End of fields used in the performance code paths */
892
893 int panic;
894 int msg_enable;
895
896 u32 flags;
897 #define PCIX_FLAG 1
898 #define PCI_32BIT_FLAG 2
899 #define ONE_PORT_FLAG 4
900 #define NO_WOL_FLAG 8
901 #define USING_DAC_FLAG 0x10
902 #define USING_MSIX_FLAG 0x20
903 #define USING_MSI_FLAG 0x40
904 #define TPA_ENABLE_FLAG 0x80
905 #define NO_MCP_FLAG 0x100
906 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
907 #define HW_VLAN_TX_FLAG 0x400
908 #define HW_VLAN_RX_FLAG 0x800
909 #define MF_FUNC_DIS 0x1000
910
911 int func;
912 #define BP_PORT(bp) (bp->func % PORT_MAX)
913 #define BP_FUNC(bp) (bp->func)
914 #define BP_E1HVN(bp) (bp->func >> 1)
915 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
916
917 #ifdef BCM_CNIC
918 #define BCM_CNIC_CID_START 16
919 #define BCM_ISCSI_ETH_CL_ID 17
920 #endif
921
922 int pm_cap;
923 int pcie_cap;
924 int mrrs;
925
926 struct delayed_work sp_task;
927 struct work_struct reset_task;
928
929 struct timer_list timer;
930 int current_interval;
931
932 u16 fw_seq;
933 u16 fw_drv_pulse_wr_seq;
934 u32 func_stx;
935
936 struct link_params link_params;
937 struct link_vars link_vars;
938 struct mdio_if_info mdio;
939
940 struct bnx2x_common common;
941 struct bnx2x_port port;
942
943 struct cmng_struct_per_port cmng;
944 u32 vn_weight_sum;
945
946 u32 mf_config;
947 u16 e1hov;
948 u8 e1hmf;
949 #define IS_E1HMF(bp) (bp->e1hmf != 0)
950
951 u8 wol;
952
953 int rx_ring_size;
954
955 u16 tx_quick_cons_trip_int;
956 u16 tx_quick_cons_trip;
957 u16 tx_ticks_int;
958 u16 tx_ticks;
959
960 u16 rx_quick_cons_trip_int;
961 u16 rx_quick_cons_trip;
962 u16 rx_ticks_int;
963 u16 rx_ticks;
964
965 u32 lin_cnt;
966
967 int state;
968 #define BNX2X_STATE_CLOSED 0
969 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
970 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
971 #define BNX2X_STATE_OPEN 0x3000
972 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
973 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
974 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
975 #define BNX2X_STATE_DIAG 0xe000
976 #define BNX2X_STATE_ERROR 0xf000
977
978 int multi_mode;
979 int num_queues;
980
981 u32 rx_mode;
982 #define BNX2X_RX_MODE_NONE 0
983 #define BNX2X_RX_MODE_NORMAL 1
984 #define BNX2X_RX_MODE_ALLMULTI 2
985 #define BNX2X_RX_MODE_PROMISC 3
986 #define BNX2X_MAX_MULTICAST 64
987 #define BNX2X_MAX_EMUL_MULTI 16
988
989 u32 rx_mode_cl_mask;
990
991 dma_addr_t def_status_blk_mapping;
992
993 struct bnx2x_slowpath *slowpath;
994 dma_addr_t slowpath_mapping;
995
996 int dropless_fc;
997
998 #ifdef BCM_CNIC
999 u32 cnic_flags;
1000 #define BNX2X_CNIC_FLAG_MAC_SET 1
1001
1002 void *t1;
1003 dma_addr_t t1_mapping;
1004 void *t2;
1005 dma_addr_t t2_mapping;
1006 void *timers;
1007 dma_addr_t timers_mapping;
1008 void *qm;
1009 dma_addr_t qm_mapping;
1010 struct cnic_ops *cnic_ops;
1011 void *cnic_data;
1012 u32 cnic_tag;
1013 struct cnic_eth_dev cnic_eth_dev;
1014 struct host_status_block *cnic_sb;
1015 dma_addr_t cnic_sb_mapping;
1016 #define CNIC_SB_ID(bp) BP_L_ID(bp)
1017 struct eth_spe *cnic_kwq;
1018 struct eth_spe *cnic_kwq_prod;
1019 struct eth_spe *cnic_kwq_cons;
1020 struct eth_spe *cnic_kwq_last;
1021 u16 cnic_kwq_pending;
1022 u16 cnic_spq_pending;
1023 struct mutex cnic_mutex;
1024 u8 iscsi_mac[6];
1025 #endif
1026
1027 int dmae_ready;
1028 /* used to synchronize dmae accesses */
1029 struct mutex dmae_mutex;
1030
1031 /* used to protect the FW mail box */
1032 struct mutex fw_mb_mutex;
1033
1034 /* used to synchronize stats collecting */
1035 int stats_state;
1036 /* used by dmae command loader */
1037 struct dmae_command stats_dmae;
1038 int executer_idx;
1039
1040 u16 stats_counter;
1041 struct bnx2x_eth_stats eth_stats;
1042
1043 struct z_stream_s *strm;
1044 void *gunzip_buf;
1045 dma_addr_t gunzip_mapping;
1046 int gunzip_outlen;
1047 #define FW_BUF_SIZE 0x8000
1048 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1049 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1050 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1051
1052 struct raw_op *init_ops;
1053 /* Init blocks offsets inside init_ops */
1054 u16 *init_ops_offsets;
1055 /* Data blob - has 32 bit granularity */
1056 u32 *init_data;
1057 /* Zipped PRAM blobs - raw data */
1058 const u8 *tsem_int_table_data;
1059 const u8 *tsem_pram_data;
1060 const u8 *usem_int_table_data;
1061 const u8 *usem_pram_data;
1062 const u8 *xsem_int_table_data;
1063 const u8 *xsem_pram_data;
1064 const u8 *csem_int_table_data;
1065 const u8 *csem_pram_data;
1066 #define INIT_OPS(bp) (bp->init_ops)
1067 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1068 #define INIT_DATA(bp) (bp->init_data)
1069 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1070 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1071 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1072 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1073 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1074 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1075 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1076 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1077
1078 const struct firmware *firmware;
1079 };
1080
1081
1082 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1083 : MAX_CONTEXT)
1084 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1085 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1086
1087 #define for_each_queue(bp, var) \
1088 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1089 #define for_each_nondefault_queue(bp, var) \
1090 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1091
1092
1093 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1094 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1095 u32 len32);
1096 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1097 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1098 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1099 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1100 void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1101 void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1102 u32 addr, u32 len);
1103
1104 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1105 int wait)
1106 {
1107 u32 val;
1108
1109 do {
1110 val = REG_RD(bp, reg);
1111 if (val == expected)
1112 break;
1113 ms -= wait;
1114 msleep(wait);
1115
1116 } while (ms > 0);
1117
1118 return val;
1119 }
1120
1121
1122 /* load/unload mode */
1123 #define LOAD_NORMAL 0
1124 #define LOAD_OPEN 1
1125 #define LOAD_DIAG 2
1126 #define UNLOAD_NORMAL 0
1127 #define UNLOAD_CLOSE 1
1128
1129
1130 /* DMAE command defines */
1131 #define DMAE_CMD_SRC_PCI 0
1132 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1133
1134 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1135 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1136
1137 #define DMAE_CMD_C_DST_PCI 0
1138 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1139
1140 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1141
1142 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1143 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1144 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1145 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1146
1147 #define DMAE_CMD_PORT_0 0
1148 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1149
1150 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1151 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1152 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1153
1154 #define DMAE_LEN32_RD_MAX 0x80
1155 #define DMAE_LEN32_WR_MAX 0x400
1156
1157 #define DMAE_COMP_VAL 0xe0d0d0ae
1158
1159 #define MAX_DMAE_C_PER_PORT 8
1160 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1161 BP_E1HVN(bp))
1162 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1163 E1HVN_MAX)
1164
1165
1166 /* PCIE link and speed */
1167 #define PCICFG_LINK_WIDTH 0x1f00000
1168 #define PCICFG_LINK_WIDTH_SHIFT 20
1169 #define PCICFG_LINK_SPEED 0xf0000
1170 #define PCICFG_LINK_SPEED_SHIFT 16
1171
1172
1173 #define BNX2X_NUM_TESTS 7
1174
1175 #define BNX2X_PHY_LOOPBACK 0
1176 #define BNX2X_MAC_LOOPBACK 1
1177 #define BNX2X_PHY_LOOPBACK_FAILED 1
1178 #define BNX2X_MAC_LOOPBACK_FAILED 2
1179 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1180 BNX2X_PHY_LOOPBACK_FAILED)
1181
1182
1183 #define STROM_ASSERT_ARRAY_SIZE 50
1184
1185
1186 /* must be used on a CID before placing it on a HW ring */
1187 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1188 (BP_E1HVN(bp) << 17) | (x))
1189
1190 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1191 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1192
1193
1194 #define BNX2X_BTR 1
1195 #define MAX_SPQ_PENDING 8
1196
1197
1198 /* CMNG constants
1199 derived from lab experiments, and not from system spec calculations !!! */
1200 #define DEF_MIN_RATE 100
1201 /* resolution of the rate shaping timer - 100 usec */
1202 #define RS_PERIODIC_TIMEOUT_USEC 100
1203 /* resolution of fairness algorithm in usecs -
1204 coefficient for calculating the actual t fair */
1205 #define T_FAIR_COEF 10000000
1206 /* number of bytes in single QM arbitration cycle -
1207 coefficient for calculating the fairness timer */
1208 #define QM_ARB_BYTES 40000
1209 #define FAIR_MEM 2
1210
1211
1212 #define ATTN_NIG_FOR_FUNC (1L << 8)
1213 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1214 #define GPIO_2_FUNC (1L << 10)
1215 #define GPIO_3_FUNC (1L << 11)
1216 #define GPIO_4_FUNC (1L << 12)
1217 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1218 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1219 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1220 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1221 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1222 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1223
1224 #define ATTN_HARD_WIRED_MASK 0xff00
1225 #define ATTENTION_ID 4
1226
1227
1228 /* stuff added to make the code fit 80Col */
1229
1230 #define BNX2X_PMF_LINK_ASSERT \
1231 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1232
1233 #define BNX2X_MC_ASSERT_BITS \
1234 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1235 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1236 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1237 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1238
1239 #define BNX2X_MCP_ASSERT \
1240 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1241
1242 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1243 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1244 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1245 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1246 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1247 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1248 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1249
1250 #define HW_INTERRUT_ASSERT_SET_0 \
1251 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1252 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1253 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1254 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1255 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1256 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1257 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1258 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1259 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1260 #define HW_INTERRUT_ASSERT_SET_1 \
1261 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1262 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1263 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1264 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1265 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1266 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1267 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1268 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1269 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1270 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1271 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1272 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1273 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1274 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1275 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1276 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1277 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1278 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1279 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1280 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1281 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1282 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1283 #define HW_INTERRUT_ASSERT_SET_2 \
1284 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1285 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1286 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1287 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1288 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1289 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1290 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1291 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1292 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1293 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1294 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1295 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1296
1297
1298 #define MULTI_FLAGS(bp) \
1299 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1300 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1301 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1302 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1303 (bp->multi_mode << \
1304 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1305 #define MULTI_MASK 0x7f
1306
1307
1308 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1309 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1310 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1311 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1312
1313 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1314
1315 #define BNX2X_SP_DSB_INDEX \
1316 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1317
1318
1319 #define CAM_IS_INVALID(x) \
1320 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1321
1322 #define CAM_INVALIDATE(x) \
1323 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1324
1325
1326 /* Number of u32 elements in MC hash array */
1327 #define MC_HASH_SIZE 8
1328 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1329 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1330
1331
1332 #ifndef PXP2_REG_PXP2_INT_STS
1333 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1334 #endif
1335
1336 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1337
1338 #endif /* bnx2x.h */
Linux with added FPC-III support