2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <acpi/acpi_hest.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses
);
21 EXPORT_SYMBOL(pci_root_buses
);
24 static int find_anything(struct device
*dev
, void *data
)
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
32 * is no device to be found on the pci_bus_type.
34 int no_pci_devices(void)
39 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
40 no_devices
= (dev
== NULL
);
44 EXPORT_SYMBOL(no_pci_devices
);
47 * PCI Bus Class Devices
49 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
51 struct device_attribute
*attr
,
55 const struct cpumask
*cpumask
;
57 cpumask
= cpumask_of_pcibus(to_pci_bus(dev
));
59 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
) :
60 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
66 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
67 struct device_attribute
*attr
,
70 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
73 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
74 struct device_attribute
*attr
,
77 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
80 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
81 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
86 static void release_pcibus_dev(struct device
*dev
)
88 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
91 put_device(pci_bus
->bridge
);
92 pci_bus_remove_resources(pci_bus
);
96 static struct class pcibus_class
= {
98 .dev_release
= &release_pcibus_dev
,
101 static int __init
pcibus_class_init(void)
103 return class_register(&pcibus_class
);
105 postcore_initcall(pcibus_class_init
);
108 * Translate the low bits of the PCI base
109 * to the resource type
111 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
113 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
114 return IORESOURCE_IO
;
116 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
117 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
119 return IORESOURCE_MEM
;
122 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
124 u64 size
= mask
& maxbase
; /* Find the significant bits */
128 /* Get the lowest of them to find the decode size, and
129 from that the extent. */
130 size
= (size
& ~(size
-1)) - 1;
132 /* base == maxbase can be valid only if the BAR has
133 already been programmed with all 1s. */
134 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
140 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
142 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
143 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
147 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
149 if (res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
150 return pci_bar_mem64
;
151 return pci_bar_mem32
;
155 * pci_read_base - read a PCI BAR
156 * @dev: the PCI device
157 * @type: type of the BAR
158 * @res: resource buffer to be filled in
159 * @pos: BAR position in the config space
161 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
163 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
164 struct resource
*res
, unsigned int pos
)
168 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
170 res
->name
= pci_name(dev
);
172 pci_read_config_dword(dev
, pos
, &l
);
173 pci_write_config_dword(dev
, pos
, l
| mask
);
174 pci_read_config_dword(dev
, pos
, &sz
);
175 pci_write_config_dword(dev
, pos
, l
);
178 * All bits set in sz means the device isn't working properly.
179 * If the BAR isn't implemented, all bits must be 0. If it's a
180 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
183 if (!sz
|| sz
== 0xffffffff)
187 * I don't know how l can have all bits set. Copied from old code.
188 * Maybe it fixes a bug on some ancient platform.
193 if (type
== pci_bar_unknown
) {
194 type
= decode_bar(res
, l
);
195 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
196 if (type
== pci_bar_io
) {
197 l
&= PCI_BASE_ADDRESS_IO_MASK
;
198 mask
= PCI_BASE_ADDRESS_IO_MASK
& IO_SPACE_LIMIT
;
200 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
201 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
204 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
205 l
&= PCI_ROM_ADDRESS_MASK
;
206 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
209 if (type
== pci_bar_mem64
) {
212 u64 mask64
= mask
| (u64
)~0 << 32;
214 pci_read_config_dword(dev
, pos
+ 4, &l
);
215 pci_write_config_dword(dev
, pos
+ 4, ~0);
216 pci_read_config_dword(dev
, pos
+ 4, &sz
);
217 pci_write_config_dword(dev
, pos
+ 4, l
);
219 l64
|= ((u64
)l
<< 32);
220 sz64
|= ((u64
)sz
<< 32);
222 sz64
= pci_size(l64
, sz64
, mask64
);
227 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
228 dev_err(&dev
->dev
, "reg %x: can't handle 64-bit BAR\n",
233 res
->flags
|= IORESOURCE_MEM_64
;
234 if ((sizeof(resource_size_t
) < 8) && l
) {
235 /* Address above 32-bit boundary; disable the BAR */
236 pci_write_config_dword(dev
, pos
, 0);
237 pci_write_config_dword(dev
, pos
+ 4, 0);
242 res
->end
= l64
+ sz64
;
243 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n",
247 sz
= pci_size(l
, sz
, mask
);
255 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n", pos
, res
);
259 return (type
== pci_bar_mem64
) ? 1 : 0;
265 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
267 unsigned int pos
, reg
;
269 for (pos
= 0; pos
< howmany
; pos
++) {
270 struct resource
*res
= &dev
->resource
[pos
];
271 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
272 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
276 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
277 dev
->rom_base_reg
= rom
;
278 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
279 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
280 IORESOURCE_SIZEALIGN
;
281 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
285 static void __devinit
pci_read_bridge_io(struct pci_bus
*child
)
287 struct pci_dev
*dev
= child
->self
;
288 u8 io_base_lo
, io_limit_lo
;
289 unsigned long base
, limit
;
290 struct resource
*res
;
292 res
= child
->resource
[0];
293 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
294 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
295 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
296 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
298 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
299 u16 io_base_hi
, io_limit_hi
;
300 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
301 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
302 base
|= (io_base_hi
<< 16);
303 limit
|= (io_limit_hi
<< 16);
306 if (base
&& base
<= limit
) {
307 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
311 res
->end
= limit
+ 0xfff;
312 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
314 dev_printk(KERN_DEBUG
, &dev
->dev
,
315 " bridge window [io %#06lx-%#06lx] (disabled)\n",
320 static void __devinit
pci_read_bridge_mmio(struct pci_bus
*child
)
322 struct pci_dev
*dev
= child
->self
;
323 u16 mem_base_lo
, mem_limit_lo
;
324 unsigned long base
, limit
;
325 struct resource
*res
;
327 res
= child
->resource
[1];
328 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
329 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
330 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
331 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
332 if (base
&& base
<= limit
) {
333 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
335 res
->end
= limit
+ 0xfffff;
336 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
338 dev_printk(KERN_DEBUG
, &dev
->dev
,
339 " bridge window [mem %#010lx-%#010lx] (disabled)\n",
340 base
, limit
+ 0xfffff);
344 static void __devinit
pci_read_bridge_mmio_pref(struct pci_bus
*child
)
346 struct pci_dev
*dev
= child
->self
;
347 u16 mem_base_lo
, mem_limit_lo
;
348 unsigned long base
, limit
;
349 struct resource
*res
;
351 res
= child
->resource
[2];
352 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
353 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
354 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
355 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
357 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
358 u32 mem_base_hi
, mem_limit_hi
;
359 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
360 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
363 * Some bridges set the base > limit by default, and some
364 * (broken) BIOSes do not initialize them. If we find
365 * this, just assume they are not being used.
367 if (mem_base_hi
<= mem_limit_hi
) {
368 #if BITS_PER_LONG == 64
369 base
|= ((long) mem_base_hi
) << 32;
370 limit
|= ((long) mem_limit_hi
) << 32;
372 if (mem_base_hi
|| mem_limit_hi
) {
373 dev_err(&dev
->dev
, "can't handle 64-bit "
374 "address space for bridge\n");
380 if (base
&& base
<= limit
) {
381 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
382 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
383 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
384 res
->flags
|= IORESOURCE_MEM_64
;
386 res
->end
= limit
+ 0xfffff;
387 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
389 dev_printk(KERN_DEBUG
, &dev
->dev
,
390 " bridge window [mem %#010lx-%#010lx pref] (disabled)\n",
391 base
, limit
+ 0xfffff);
395 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
397 struct pci_dev
*dev
= child
->self
;
398 struct resource
*res
;
401 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
404 dev_info(&dev
->dev
, "PCI bridge to [bus %02x-%02x]%s\n",
405 child
->secondary
, child
->subordinate
,
406 dev
->transparent
? " (subtractive decode)" : "");
408 pci_bus_remove_resources(child
);
409 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
410 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
412 pci_read_bridge_io(child
);
413 pci_read_bridge_mmio(child
);
414 pci_read_bridge_mmio_pref(child
);
416 if (dev
->transparent
) {
417 pci_bus_for_each_resource(child
->parent
, res
, i
) {
419 pci_bus_add_resource(child
, res
,
420 PCI_SUBTRACTIVE_DECODE
);
421 dev_printk(KERN_DEBUG
, &dev
->dev
,
422 " bridge window %pR (subtractive decode)\n",
429 static struct pci_bus
* pci_alloc_bus(void)
433 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
435 INIT_LIST_HEAD(&b
->node
);
436 INIT_LIST_HEAD(&b
->children
);
437 INIT_LIST_HEAD(&b
->devices
);
438 INIT_LIST_HEAD(&b
->slots
);
439 INIT_LIST_HEAD(&b
->resources
);
440 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
441 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
446 static unsigned char pcix_bus_speed
[] = {
447 PCI_SPEED_UNKNOWN
, /* 0 */
448 PCI_SPEED_66MHz_PCIX
, /* 1 */
449 PCI_SPEED_100MHz_PCIX
, /* 2 */
450 PCI_SPEED_133MHz_PCIX
, /* 3 */
451 PCI_SPEED_UNKNOWN
, /* 4 */
452 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
453 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
454 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
455 PCI_SPEED_UNKNOWN
, /* 8 */
456 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
457 PCI_SPEED_100MHz_PCIX_266
, /* A */
458 PCI_SPEED_133MHz_PCIX_266
, /* B */
459 PCI_SPEED_UNKNOWN
, /* C */
460 PCI_SPEED_66MHz_PCIX_533
, /* D */
461 PCI_SPEED_100MHz_PCIX_533
, /* E */
462 PCI_SPEED_133MHz_PCIX_533
/* F */
465 static unsigned char pcie_link_speed
[] = {
466 PCI_SPEED_UNKNOWN
, /* 0 */
467 PCIE_SPEED_2_5GT
, /* 1 */
468 PCIE_SPEED_5_0GT
, /* 2 */
469 PCIE_SPEED_8_0GT
, /* 3 */
470 PCI_SPEED_UNKNOWN
, /* 4 */
471 PCI_SPEED_UNKNOWN
, /* 5 */
472 PCI_SPEED_UNKNOWN
, /* 6 */
473 PCI_SPEED_UNKNOWN
, /* 7 */
474 PCI_SPEED_UNKNOWN
, /* 8 */
475 PCI_SPEED_UNKNOWN
, /* 9 */
476 PCI_SPEED_UNKNOWN
, /* A */
477 PCI_SPEED_UNKNOWN
, /* B */
478 PCI_SPEED_UNKNOWN
, /* C */
479 PCI_SPEED_UNKNOWN
, /* D */
480 PCI_SPEED_UNKNOWN
, /* E */
481 PCI_SPEED_UNKNOWN
/* F */
484 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
486 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& 0xf];
488 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
490 static unsigned char agp_speeds
[] = {
498 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
504 else if (agpstat
& 2)
506 else if (agpstat
& 1)
518 return agp_speeds
[index
];
522 static void pci_set_bus_speed(struct pci_bus
*bus
)
524 struct pci_dev
*bridge
= bus
->self
;
527 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
529 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
533 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
534 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
536 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
537 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
540 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
543 enum pci_bus_speed max
;
544 pci_read_config_word(bridge
, pos
+ 2, &status
);
546 if (status
& 0x8000) {
547 max
= PCI_SPEED_133MHz_PCIX_533
;
548 } else if (status
& 0x4000) {
549 max
= PCI_SPEED_133MHz_PCIX_266
;
550 } else if (status
& 0x0002) {
551 if (((status
>> 12) & 0x3) == 2) {
552 max
= PCI_SPEED_133MHz_PCIX_ECC
;
554 max
= PCI_SPEED_133MHz_PCIX
;
557 max
= PCI_SPEED_66MHz_PCIX
;
560 bus
->max_bus_speed
= max
;
561 bus
->cur_bus_speed
= pcix_bus_speed
[(status
>> 6) & 0xf];
566 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
571 pci_read_config_dword(bridge
, pos
+ PCI_EXP_LNKCAP
, &linkcap
);
572 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& 0xf];
574 pci_read_config_word(bridge
, pos
+ PCI_EXP_LNKSTA
, &linksta
);
575 pcie_update_link_speed(bus
, linksta
);
580 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
581 struct pci_dev
*bridge
, int busnr
)
583 struct pci_bus
*child
;
587 * Allocate a new bus, and inherit stuff from the parent..
589 child
= pci_alloc_bus();
593 child
->parent
= parent
;
594 child
->ops
= parent
->ops
;
595 child
->sysdata
= parent
->sysdata
;
596 child
->bus_flags
= parent
->bus_flags
;
598 /* initialize some portions of the bus device, but don't register it
599 * now as the parent is not properly set up yet. This device will get
600 * registered later in pci_bus_add_devices()
602 child
->dev
.class = &pcibus_class
;
603 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
606 * Set up the primary, secondary and subordinate
609 child
->number
= child
->secondary
= busnr
;
610 child
->primary
= parent
->secondary
;
611 child
->subordinate
= 0xff;
616 child
->self
= bridge
;
617 child
->bridge
= get_device(&bridge
->dev
);
619 pci_set_bus_speed(child
);
621 /* Set up default resource pointers and names.. */
622 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
623 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
624 child
->resource
[i
]->name
= child
->name
;
626 bridge
->subordinate
= child
;
631 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
633 struct pci_bus
*child
;
635 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
637 down_write(&pci_bus_sem
);
638 list_add_tail(&child
->node
, &parent
->children
);
639 up_write(&pci_bus_sem
);
644 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
646 struct pci_bus
*parent
= child
->parent
;
648 /* Attempts to fix that up are really dangerous unless
649 we're going to re-assign all bus numbers. */
650 if (!pcibios_assign_all_busses())
653 while (parent
->parent
&& parent
->subordinate
< max
) {
654 parent
->subordinate
= max
;
655 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
656 parent
= parent
->parent
;
661 * If it's a bridge, configure it and scan the bus behind it.
662 * For CardBus bridges, we don't scan behind as the devices will
663 * be handled by the bridge driver itself.
665 * We need to process bridges in two passes -- first we scan those
666 * already configured by the BIOS and after we are done with all of
667 * them, we proceed to assigning numbers to the remaining buses in
668 * order to avoid overlaps between old and new bus numbers.
670 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
672 struct pci_bus
*child
;
673 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
676 u8 primary
, secondary
, subordinate
;
679 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
680 primary
= buses
& 0xFF;
681 secondary
= (buses
>> 8) & 0xFF;
682 subordinate
= (buses
>> 16) & 0xFF;
684 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
685 secondary
, subordinate
, pass
);
687 /* Check if setup is sensible at all */
689 (primary
!= bus
->number
|| secondary
<= bus
->number
)) {
690 dev_dbg(&dev
->dev
, "bus configuration invalid, reconfiguring\n");
694 /* Disable MasterAbortMode during probing to avoid reporting
695 of bus errors (in some architectures) */
696 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
697 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
698 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
700 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
701 !is_cardbus
&& !broken
) {
704 * Bus already configured by firmware, process it in the first
705 * pass and just note the configuration.
711 * If we already got to this bus through a different bridge,
712 * don't re-add it. This can happen with the i450NX chipset.
714 * However, we continue to descend down the hierarchy and
715 * scan remaining child buses.
717 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
719 child
= pci_add_new_bus(bus
, dev
, secondary
);
722 child
->primary
= primary
;
723 child
->subordinate
= subordinate
;
724 child
->bridge_ctl
= bctl
;
727 cmax
= pci_scan_child_bus(child
);
730 if (child
->subordinate
> max
)
731 max
= child
->subordinate
;
734 * We need to assign a number to this bus which we always
735 * do in the second pass.
738 if (pcibios_assign_all_busses() || broken
)
739 /* Temporarily disable forwarding of the
740 configuration cycles on all bridges in
741 this bus segment to avoid possible
742 conflicts in the second pass between two
743 bridges programmed with overlapping
745 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
751 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
753 /* Prevent assigning a bus number that already exists.
754 * This can happen when a bridge is hot-plugged */
755 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
757 child
= pci_add_new_bus(bus
, dev
, ++max
);
758 buses
= (buses
& 0xff000000)
759 | ((unsigned int)(child
->primary
) << 0)
760 | ((unsigned int)(child
->secondary
) << 8)
761 | ((unsigned int)(child
->subordinate
) << 16);
764 * yenta.c forces a secondary latency timer of 176.
765 * Copy that behaviour here.
768 buses
&= ~0xff000000;
769 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
773 * We need to blast all three values with a single write.
775 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
778 child
->bridge_ctl
= bctl
;
780 * Adjust subordinate busnr in parent buses.
781 * We do this before scanning for children because
782 * some devices may not be detected if the bios
785 pci_fixup_parent_subordinate_busnr(child
, max
);
786 /* Now we can scan all subordinate buses... */
787 max
= pci_scan_child_bus(child
);
789 * now fix it up again since we have found
790 * the real value of max.
792 pci_fixup_parent_subordinate_busnr(child
, max
);
795 * For CardBus bridges, we leave 4 bus numbers
796 * as cards with a PCI-to-PCI bridge can be
799 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
800 struct pci_bus
*parent
= bus
;
801 if (pci_find_bus(pci_domain_nr(bus
),
804 while (parent
->parent
) {
805 if ((!pcibios_assign_all_busses()) &&
806 (parent
->subordinate
> max
) &&
807 (parent
->subordinate
<= max
+i
)) {
810 parent
= parent
->parent
;
814 * Often, there are two cardbus bridges
815 * -- try to leave one valid bus number
823 pci_fixup_parent_subordinate_busnr(child
, max
);
826 * Set the subordinate bus number to its real value.
828 child
->subordinate
= max
;
829 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
833 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
834 pci_domain_nr(bus
), child
->number
);
836 /* Has only triggered on CardBus, fixup is in yenta_socket */
837 while (bus
->parent
) {
838 if ((child
->subordinate
> bus
->subordinate
) ||
839 (child
->number
> bus
->subordinate
) ||
840 (child
->number
< bus
->number
) ||
841 (child
->subordinate
< bus
->number
)) {
842 dev_info(&child
->dev
, "[bus %02x-%02x] %s "
843 "hidden behind%s bridge %s [bus %02x-%02x]\n",
844 child
->number
, child
->subordinate
,
845 (bus
->number
> child
->subordinate
&&
846 bus
->subordinate
< child
->number
) ?
847 "wholly" : "partially",
848 bus
->self
->transparent
? " transparent" : "",
850 bus
->number
, bus
->subordinate
);
856 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
862 * Read interrupt line and base address registers.
863 * The architecture-dependent code can tweak these, of course.
865 static void pci_read_irq(struct pci_dev
*dev
)
869 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
872 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
876 void set_pcie_port_type(struct pci_dev
*pdev
)
881 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
885 pdev
->pcie_cap
= pos
;
886 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
887 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
890 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
896 pos
= pci_pcie_cap(pdev
);
899 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
900 if (!(reg16
& PCI_EXP_FLAGS_SLOT
))
902 pci_read_config_dword(pdev
, pos
+ PCI_EXP_SLTCAP
, ®32
);
903 if (reg32
& PCI_EXP_SLTCAP_HPC
)
904 pdev
->is_hotplug_bridge
= 1;
907 static void set_pci_aer_firmware_first(struct pci_dev
*pdev
)
909 if (acpi_hest_firmware_first_pci(pdev
))
910 pdev
->aer_firmware_first
= 1;
913 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
916 * pci_setup_device - fill in class and map information of a device
917 * @dev: the device structure to fill
919 * Initialize the device structure with information about the device's
920 * vendor,class,memory and IO-space addresses,IRQ lines etc.
921 * Called at initialisation of the PCI subsystem and by CardBus services.
922 * Returns 0 on success and negative if unknown type of device (not normal,
923 * bridge or CardBus).
925 int pci_setup_device(struct pci_dev
*dev
)
929 struct pci_slot
*slot
;
932 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
935 dev
->sysdata
= dev
->bus
->sysdata
;
936 dev
->dev
.parent
= dev
->bus
->bridge
;
937 dev
->dev
.bus
= &pci_bus_type
;
938 dev
->hdr_type
= hdr_type
& 0x7f;
939 dev
->multifunction
= !!(hdr_type
& 0x80);
940 dev
->error_state
= pci_channel_io_normal
;
941 set_pcie_port_type(dev
);
942 set_pci_aer_firmware_first(dev
);
944 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
945 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
948 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
949 set this higher, assuming the system even supports it. */
950 dev
->dma_mask
= 0xffffffff;
952 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
953 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
954 PCI_FUNC(dev
->devfn
));
956 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
957 dev
->revision
= class & 0xff;
958 class >>= 8; /* upper 3 bytes */
962 dev_dbg(&dev
->dev
, "found [%04x:%04x] class %06x header type %02x\n",
963 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
965 /* need to have dev->class ready */
966 dev
->cfg_size
= pci_cfg_space_size(dev
);
968 /* "Unknown power state" */
969 dev
->current_state
= PCI_UNKNOWN
;
971 /* Early fixups, before probing the BARs */
972 pci_fixup_device(pci_fixup_early
, dev
);
973 /* device class may be changed after fixup */
974 class = dev
->class >> 8;
976 switch (dev
->hdr_type
) { /* header type */
977 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
978 if (class == PCI_CLASS_BRIDGE_PCI
)
981 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
982 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
983 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
986 * Do the ugly legacy mode stuff here rather than broken chip
987 * quirk code. Legacy mode ATA controllers have fixed
988 * addresses. These are not always echoed in BAR0-3, and
989 * BAR0-3 in a few cases contain junk!
991 if (class == PCI_CLASS_STORAGE_IDE
) {
993 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
994 if ((progif
& 1) == 0) {
995 dev
->resource
[0].start
= 0x1F0;
996 dev
->resource
[0].end
= 0x1F7;
997 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
998 dev
->resource
[1].start
= 0x3F6;
999 dev
->resource
[1].end
= 0x3F6;
1000 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
1002 if ((progif
& 4) == 0) {
1003 dev
->resource
[2].start
= 0x170;
1004 dev
->resource
[2].end
= 0x177;
1005 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
1006 dev
->resource
[3].start
= 0x376;
1007 dev
->resource
[3].end
= 0x376;
1008 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
1013 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1014 if (class != PCI_CLASS_BRIDGE_PCI
)
1016 /* The PCI-to-PCI bridge spec requires that subtractive
1017 decoding (i.e. transparent) bridge must have programming
1018 interface code of 0x01. */
1020 dev
->transparent
= ((dev
->class & 0xff) == 1);
1021 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1022 set_pcie_hotplug_bridge(dev
);
1023 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1025 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1026 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1030 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1031 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1034 pci_read_bases(dev
, 1, 0);
1035 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1036 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1039 default: /* unknown header */
1040 dev_err(&dev
->dev
, "unknown header type %02x, "
1041 "ignoring device\n", dev
->hdr_type
);
1045 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
1046 "type %02x)\n", class, dev
->hdr_type
);
1047 dev
->class = PCI_CLASS_NOT_DEFINED
;
1050 /* We found a fine healthy device, go go go... */
1054 static void pci_release_capabilities(struct pci_dev
*dev
)
1056 pci_vpd_release(dev
);
1057 pci_iov_release(dev
);
1061 * pci_release_dev - free a pci device structure when all users of it are finished.
1062 * @dev: device that's been disconnected
1064 * Will be called only by the device core when all users of this pci device are
1067 static void pci_release_dev(struct device
*dev
)
1069 struct pci_dev
*pci_dev
;
1071 pci_dev
= to_pci_dev(dev
);
1072 pci_release_capabilities(pci_dev
);
1077 * pci_cfg_space_size - get the configuration space size of the PCI device.
1080 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1081 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1082 * access it. Maybe we don't have a way to generate extended config space
1083 * accesses, or the device is behind a reverse Express bridge. So we try
1084 * reading the dword at 0x100 which must either be 0 or a valid extended
1085 * capability header.
1087 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1090 int pos
= PCI_CFG_SPACE_SIZE
;
1092 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1094 if (status
== 0xffffffff)
1097 return PCI_CFG_SPACE_EXP_SIZE
;
1100 return PCI_CFG_SPACE_SIZE
;
1103 int pci_cfg_space_size(struct pci_dev
*dev
)
1109 class = dev
->class >> 8;
1110 if (class == PCI_CLASS_BRIDGE_HOST
)
1111 return pci_cfg_space_size_ext(dev
);
1113 pos
= pci_pcie_cap(dev
);
1115 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1119 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1120 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1124 return pci_cfg_space_size_ext(dev
);
1127 return PCI_CFG_SPACE_SIZE
;
1130 static void pci_release_bus_bridge_dev(struct device
*dev
)
1135 struct pci_dev
*alloc_pci_dev(void)
1137 struct pci_dev
*dev
;
1139 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1143 INIT_LIST_HEAD(&dev
->bus_list
);
1147 EXPORT_SYMBOL(alloc_pci_dev
);
1150 * Read the config data for a PCI device, sanity-check it
1151 * and fill in the dev structure...
1153 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1155 struct pci_dev
*dev
;
1159 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
1162 /* some broken boards return 0 or ~0 if a slot is empty: */
1163 if (l
== 0xffffffff || l
== 0x00000000 ||
1164 l
== 0x0000ffff || l
== 0xffff0000)
1167 /* Configuration request Retry Status */
1168 while (l
== 0xffff0001) {
1171 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
1173 /* Card hasn't responded in 60 seconds? Must be stuck. */
1174 if (delay
> 60 * 1000) {
1175 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
1176 "responding\n", pci_domain_nr(bus
),
1177 bus
->number
, PCI_SLOT(devfn
),
1183 dev
= alloc_pci_dev();
1189 dev
->vendor
= l
& 0xffff;
1190 dev
->device
= (l
>> 16) & 0xffff;
1192 if (pci_setup_device(dev
)) {
1200 static void pci_init_capabilities(struct pci_dev
*dev
)
1202 /* MSI/MSI-X list */
1203 pci_msi_init_pci_dev(dev
);
1205 /* Buffers for saving PCIe and PCI-X capabilities */
1206 pci_allocate_cap_save_buffers(dev
);
1208 /* Power Management */
1210 platform_pci_wakeup_init(dev
);
1212 /* Vital Product Data */
1213 pci_vpd_pci22_init(dev
);
1215 /* Alternative Routing-ID Forwarding */
1216 pci_enable_ari(dev
);
1218 /* Single Root I/O Virtualization */
1221 /* Enable ACS P2P upstream forwarding */
1222 pci_enable_acs(dev
);
1225 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1227 device_initialize(&dev
->dev
);
1228 dev
->dev
.release
= pci_release_dev
;
1231 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1232 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1233 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1235 pci_set_dma_max_seg_size(dev
, 65536);
1236 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1238 /* Fix up broken headers */
1239 pci_fixup_device(pci_fixup_header
, dev
);
1241 /* Clear the state_saved flag. */
1242 dev
->state_saved
= false;
1244 /* Initialize various capabilities */
1245 pci_init_capabilities(dev
);
1248 * Add the device to our list of discovered devices
1249 * and the bus list for fixup functions, etc.
1251 down_write(&pci_bus_sem
);
1252 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1253 up_write(&pci_bus_sem
);
1256 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1258 struct pci_dev
*dev
;
1260 dev
= pci_get_slot(bus
, devfn
);
1266 dev
= pci_scan_device(bus
, devfn
);
1270 pci_device_add(dev
, bus
);
1274 EXPORT_SYMBOL(pci_scan_single_device
);
1276 static unsigned next_ari_fn(struct pci_dev
*dev
, unsigned fn
)
1279 unsigned pos
, next_fn
;
1284 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1287 pci_read_config_word(dev
, pos
+ 4, &cap
);
1294 static unsigned next_trad_fn(struct pci_dev
*dev
, unsigned fn
)
1296 return (fn
+ 1) % 8;
1299 static unsigned no_next_fn(struct pci_dev
*dev
, unsigned fn
)
1304 static int only_one_child(struct pci_bus
*bus
)
1306 struct pci_dev
*parent
= bus
->self
;
1307 if (!parent
|| !pci_is_pcie(parent
))
1309 if (parent
->pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
1310 parent
->pcie_type
== PCI_EXP_TYPE_DOWNSTREAM
)
1316 * pci_scan_slot - scan a PCI slot on a bus for devices.
1317 * @bus: PCI bus to scan
1318 * @devfn: slot number to scan (must have zero function.)
1320 * Scan a PCI slot on the specified PCI bus for devices, adding
1321 * discovered devices to the @bus->devices list. New devices
1322 * will not have is_added set.
1324 * Returns the number of new devices found.
1326 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1328 unsigned fn
, nr
= 0;
1329 struct pci_dev
*dev
;
1330 unsigned (*next_fn
)(struct pci_dev
*, unsigned) = no_next_fn
;
1332 if (only_one_child(bus
) && (devfn
> 0))
1333 return 0; /* Already scanned the entire slot */
1335 dev
= pci_scan_single_device(bus
, devfn
);
1341 if (pci_ari_enabled(bus
))
1342 next_fn
= next_ari_fn
;
1343 else if (dev
->multifunction
)
1344 next_fn
= next_trad_fn
;
1346 for (fn
= next_fn(dev
, 0); fn
> 0; fn
= next_fn(dev
, fn
)) {
1347 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1351 dev
->multifunction
= 1;
1355 /* only one slot has pcie device */
1356 if (bus
->self
&& nr
)
1357 pcie_aspm_init_link_state(bus
->self
);
1362 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1364 unsigned int devfn
, pass
, max
= bus
->secondary
;
1365 struct pci_dev
*dev
;
1367 dev_dbg(&bus
->dev
, "scanning bus\n");
1369 /* Go find them, Rover! */
1370 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1371 pci_scan_slot(bus
, devfn
);
1373 /* Reserve buses for SR-IOV capability. */
1374 max
+= pci_iov_bus_range(bus
);
1377 * After performing arch-dependent fixup of the bus, look behind
1378 * all PCI-to-PCI bridges on this bus.
1380 if (!bus
->is_added
) {
1381 dev_dbg(&bus
->dev
, "fixups for bus\n");
1382 pcibios_fixup_bus(bus
);
1383 if (pci_is_root_bus(bus
))
1387 for (pass
=0; pass
< 2; pass
++)
1388 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1389 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1390 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1391 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1395 * We've scanned the bus and so we know all about what's on
1396 * the other side of any bridges that may be on this bus plus
1399 * Return how far we've got finding sub-buses.
1401 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1405 struct pci_bus
* pci_create_bus(struct device
*parent
,
1406 int bus
, struct pci_ops
*ops
, void *sysdata
)
1409 struct pci_bus
*b
, *b2
;
1412 b
= pci_alloc_bus();
1416 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1422 b
->sysdata
= sysdata
;
1425 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1427 /* If we already got to this bus through a different bridge, ignore it */
1428 dev_dbg(&b2
->dev
, "bus already known\n");
1432 down_write(&pci_bus_sem
);
1433 list_add_tail(&b
->node
, &pci_root_buses
);
1434 up_write(&pci_bus_sem
);
1436 dev
->parent
= parent
;
1437 dev
->release
= pci_release_bus_bridge_dev
;
1438 dev_set_name(dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1439 error
= device_register(dev
);
1442 b
->bridge
= get_device(dev
);
1443 device_enable_async_suspend(b
->bridge
);
1446 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1448 b
->dev
.class = &pcibus_class
;
1449 b
->dev
.parent
= b
->bridge
;
1450 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1451 error
= device_register(&b
->dev
);
1453 goto class_dev_reg_err
;
1454 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1456 goto dev_create_file_err
;
1458 /* Create legacy_io and legacy_mem files for this bus */
1459 pci_create_legacy_files(b
);
1461 b
->number
= b
->secondary
= bus
;
1462 b
->resource
[0] = &ioport_resource
;
1463 b
->resource
[1] = &iomem_resource
;
1467 dev_create_file_err
:
1468 device_unregister(&b
->dev
);
1470 device_unregister(dev
);
1472 down_write(&pci_bus_sem
);
1474 up_write(&pci_bus_sem
);
1481 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1482 int bus
, struct pci_ops
*ops
, void *sysdata
)
1486 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1488 b
->subordinate
= pci_scan_child_bus(b
);
1491 EXPORT_SYMBOL(pci_scan_bus_parented
);
1493 #ifdef CONFIG_HOTPLUG
1495 * pci_rescan_bus - scan a PCI bus for devices.
1496 * @bus: PCI bus to scan
1498 * Scan a PCI bus and child buses for new devices, adds them,
1501 * Returns the max number of subordinate bus discovered.
1503 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1506 struct pci_dev
*dev
;
1508 max
= pci_scan_child_bus(bus
);
1510 down_read(&pci_bus_sem
);
1511 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1512 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1513 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1514 if (dev
->subordinate
)
1515 pci_bus_size_bridges(dev
->subordinate
);
1516 up_read(&pci_bus_sem
);
1518 pci_bus_assign_resources(bus
);
1519 pci_enable_bridges(bus
);
1520 pci_bus_add_devices(bus
);
1524 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1526 EXPORT_SYMBOL(pci_add_new_bus
);
1527 EXPORT_SYMBOL(pci_scan_slot
);
1528 EXPORT_SYMBOL(pci_scan_bridge
);
1529 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1532 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1534 const struct pci_dev
*a
= to_pci_dev(d_a
);
1535 const struct pci_dev
*b
= to_pci_dev(d_b
);
1537 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1538 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1540 if (a
->bus
->number
< b
->bus
->number
) return -1;
1541 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1543 if (a
->devfn
< b
->devfn
) return -1;
1544 else if (a
->devfn
> b
->devfn
) return 1;
1549 void __init
pci_sort_breadthfirst(void)
1551 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);