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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / scsi / be2iscsi / be_cmds.h
blob49fcc787ee8bd5516c7eea10cd93cb7fff1800d3
1 /**
2 * Copyright (C) 2005 - 2010 ServerEngines
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@serverengines.com
12 *
13 * ServerEngines
14 * 209 N. Fair Oaks Ave
15 * Sunnyvale, CA 94085
16 */
17
18 #ifndef BEISCSI_CMDS_H
19 #define BEISCSI_CMDS_H
20
21 /**
22 * The driver sends configuration and managements command requests to the
23 * firmware in the BE. These requests are communicated to the processor
24 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
25 * WRB inside a MAILBOX.
26 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
27 */
28 struct be_sge {
29 u32 pa_lo;
30 u32 pa_hi;
31 u32 len;
32 };
33
34 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
35 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 struct be_mcc_wrb {
37 u32 embedded; /* dword 0 */
38 u32 payload_length; /* dword 1 */
39 u32 tag0; /* dword 2 */
40 u32 tag1; /* dword 3 */
41 u32 rsvd; /* dword 4 */
42 union {
43 u8 embedded_payload[236]; /* used by embedded cmds */
44 struct be_sge sgl[19]; /* used by non-embedded cmds */
45 } payload;
46 };
47
48 #define CQE_FLAGS_VALID_MASK (1 << 31)
49 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
50 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
51 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52
53 /* Completion Status */
54 #define MCC_STATUS_SUCCESS 0x0
55
56 #define CQE_STATUS_COMPL_MASK 0xFFFF
57 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
58 #define CQE_STATUS_EXTD_MASK 0xFFFF
59 #define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */
60
61 struct be_mcc_compl {
62 u32 status; /* dword 0 */
63 u32 tag0; /* dword 1 */
64 u32 tag1; /* dword 2 */
65 u32 flags; /* dword 3 */
66 };
67
68 /********* Mailbox door bell *************/
69 /**
70 * Used for driver communication with the FW.
71 * The software must write this register twice to post any command. First,
72 * it writes the register with hi=1 and the upper bits of the physical address
73 * for the MAILBOX structure. Software must poll the ready bit until this
74 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
75 * bits in the address. It must poll the ready bit until the command is
76 * complete. Upon completion, the MAILBOX will contain a valid completion
77 * queue entry.
78 */
79 #define MPU_MAILBOX_DB_OFFSET 0x160
80 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
81 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
82
83 /********** MPU semphore ******************/
84 #define MPU_EP_SEMAPHORE_OFFSET 0xac
85 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
86 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
87 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
88
89 /********** MCC door bell ************/
90 #define DB_MCCQ_OFFSET 0x140
91 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
92 /* Number of entries posted */
93 #define DB_MCCQ_NUM_POSTED_SHIFT 16 /* bits 16 - 29 */
94
95 /* MPU semphore POST stage values */
96 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
97
98 /**
99 * When the async bit of mcc_compl is set, the last 4 bytes of
100 * mcc_compl is interpreted as follows:
101 */
102 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
103 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
104 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
105 struct be_async_event_trailer {
106 u32 code;
107 };
108
109 enum {
110 ASYNC_EVENT_LINK_DOWN = 0x0,
111 ASYNC_EVENT_LINK_UP = 0x1
112 };
113
114 /**
115 * When the event code of an async trailer is link-state, the mcc_compl
116 * must be interpreted as follows
117 */
118 struct be_async_event_link_state {
119 u8 physical_port;
120 u8 port_link_status;
121 u8 port_duplex;
122 u8 port_speed;
123 u8 port_fault;
124 u8 rsvd0[7];
125 struct be_async_event_trailer trailer;
126 } __packed;
127
128 struct be_mcc_mailbox {
129 struct be_mcc_wrb wrb;
130 struct be_mcc_compl compl;
131 };
132
133 /* Type of subsystems supported by FW */
134 #define CMD_SUBSYSTEM_COMMON 0x1
135 #define CMD_SUBSYSTEM_ISCSI 0x2
136 #define CMD_SUBSYSTEM_ETH 0x3
137 #define CMD_SUBSYSTEM_ISCSI_INI 0x6
138 #define CMD_COMMON_TCP_UPLOAD 0x1
139
140 /**
141 * List of common opcodes subsystem CMD_SUBSYSTEM_COMMON
142 * These opcodes are unique for each subsystem defined above
143 */
144 #define OPCODE_COMMON_CQ_CREATE 12
145 #define OPCODE_COMMON_EQ_CREATE 13
146 #define OPCODE_COMMON_MCC_CREATE 21
147 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
148 #define OPCODE_COMMON_GET_FW_VERSION 35
149 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
150 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
151 #define OPCODE_COMMON_MCC_DESTROY 53
152 #define OPCODE_COMMON_CQ_DESTROY 54
153 #define OPCODE_COMMON_EQ_DESTROY 55
154 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
155 #define OPCODE_COMMON_FUNCTION_RESET 61
156
157 /**
158 * LIST of opcodes that are common between Initiator and Target
159 * used by CMD_SUBSYSTEM_ISCSI
160 * These opcodes are unique for each subsystem defined above
161 */
162 #define OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES 2
163 #define OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES 3
164 #define OPCODE_COMMON_ISCSI_NTWK_GET_NIC_CONFIG 7
165 #define OPCODE_COMMON_ISCSI_SET_FRAGNUM_BITS_FOR_SGL_CRA 61
166 #define OPCODE_COMMON_ISCSI_DEFQ_CREATE 64
167 #define OPCODE_COMMON_ISCSI_DEFQ_DESTROY 65
168 #define OPCODE_COMMON_ISCSI_WRBQ_CREATE 66
169 #define OPCODE_COMMON_ISCSI_WRBQ_DESTROY 67
170
171 struct be_cmd_req_hdr {
172 u8 opcode; /* dword 0 */
173 u8 subsystem; /* dword 0 */
174 u8 port_number; /* dword 0 */
175 u8 domain; /* dword 0 */
176 u32 timeout; /* dword 1 */
177 u32 request_length; /* dword 2 */
178 u32 rsvd0; /* dword 3 */
179 };
180
181 struct be_cmd_resp_hdr {
182 u32 info; /* dword 0 */
183 u32 status; /* dword 1 */
184 u32 response_length; /* dword 2 */
185 u32 actual_resp_len; /* dword 3 */
186 };
187
188 struct phys_addr {
189 u32 lo;
190 u32 hi;
191 };
192
193 /**************************
194 * BE Command definitions *
195 **************************/
196
197 /**
198 * Pseudo amap definition in which each bit of the actual structure is defined
199 * as a byte - used to calculate offset/shift/mask of each field
200 */
201 struct amap_eq_context {
202 u8 cidx[13]; /* dword 0 */
203 u8 rsvd0[3]; /* dword 0 */
204 u8 epidx[13]; /* dword 0 */
205 u8 valid; /* dword 0 */
206 u8 rsvd1; /* dword 0 */
207 u8 size; /* dword 0 */
208 u8 pidx[13]; /* dword 1 */
209 u8 rsvd2[3]; /* dword 1 */
210 u8 pd[10]; /* dword 1 */
211 u8 count[3]; /* dword 1 */
212 u8 solevent; /* dword 1 */
213 u8 stalled; /* dword 1 */
214 u8 armed; /* dword 1 */
215 u8 rsvd3[4]; /* dword 2 */
216 u8 func[8]; /* dword 2 */
217 u8 rsvd4; /* dword 2 */
218 u8 delaymult[10]; /* dword 2 */
219 u8 rsvd5[2]; /* dword 2 */
220 u8 phase[2]; /* dword 2 */
221 u8 nodelay; /* dword 2 */
222 u8 rsvd6[4]; /* dword 2 */
223 u8 rsvd7[32]; /* dword 3 */
224 } __packed;
225
226 struct be_cmd_req_eq_create {
227 struct be_cmd_req_hdr hdr; /* dw[4] */
228 u16 num_pages; /* sword */
229 u16 rsvd0; /* sword */
230 u8 context[sizeof(struct amap_eq_context) / 8]; /* dw[4] */
231 struct phys_addr pages[8];
232 } __packed;
233
234 struct be_cmd_resp_eq_create {
235 struct be_cmd_resp_hdr resp_hdr;
236 u16 eq_id; /* sword */
237 u16 rsvd0; /* sword */
238 } __packed;
239
240 struct mac_addr {
241 u16 size_of_struct;
242 u8 addr[ETH_ALEN];
243 } __packed;
244
245 struct be_cmd_req_mac_query {
246 struct be_cmd_req_hdr hdr;
247 u8 type;
248 u8 permanent;
249 u16 if_id;
250 } __packed;
251
252 struct be_cmd_resp_mac_query {
253 struct be_cmd_resp_hdr hdr;
254 struct mac_addr mac;
255 };
256
257 /******************** Create CQ ***************************/
258 /**
259 * Pseudo amap definition in which each bit of the actual structure is defined
260 * as a byte - used to calculate offset/shift/mask of each field
261 */
262 struct amap_cq_context {
263 u8 cidx[11]; /* dword 0 */
264 u8 rsvd0; /* dword 0 */
265 u8 coalescwm[2]; /* dword 0 */
266 u8 nodelay; /* dword 0 */
267 u8 epidx[11]; /* dword 0 */
268 u8 rsvd1; /* dword 0 */
269 u8 count[2]; /* dword 0 */
270 u8 valid; /* dword 0 */
271 u8 solevent; /* dword 0 */
272 u8 eventable; /* dword 0 */
273 u8 pidx[11]; /* dword 1 */
274 u8 rsvd2; /* dword 1 */
275 u8 pd[10]; /* dword 1 */
276 u8 eqid[8]; /* dword 1 */
277 u8 stalled; /* dword 1 */
278 u8 armed; /* dword 1 */
279 u8 rsvd3[4]; /* dword 2 */
280 u8 func[8]; /* dword 2 */
281 u8 rsvd4[20]; /* dword 2 */
282 u8 rsvd5[32]; /* dword 3 */
283 } __packed;
284
285 struct be_cmd_req_cq_create {
286 struct be_cmd_req_hdr hdr;
287 u16 num_pages;
288 u16 rsvd0;
289 u8 context[sizeof(struct amap_cq_context) / 8];
290 struct phys_addr pages[4];
291 } __packed;
292
293 struct be_cmd_resp_cq_create {
294 struct be_cmd_resp_hdr hdr;
295 u16 cq_id;
296 u16 rsvd0;
297 } __packed;
298
299 /******************** Create MCCQ ***************************/
300 /**
301 * Pseudo amap definition in which each bit of the actual structure is defined
302 * as a byte - used to calculate offset/shift/mask of each field
303 */
304 struct amap_mcc_context {
305 u8 con_index[14];
306 u8 rsvd0[2];
307 u8 ring_size[4];
308 u8 fetch_wrb;
309 u8 fetch_r2t;
310 u8 cq_id[10];
311 u8 prod_index[14];
312 u8 fid[8];
313 u8 pdid[9];
314 u8 valid;
315 u8 rsvd1[32];
316 u8 rsvd2[32];
317 } __packed;
318
319 struct be_cmd_req_mcc_create {
320 struct be_cmd_req_hdr hdr;
321 u16 num_pages;
322 u16 rsvd0;
323 u8 context[sizeof(struct amap_mcc_context) / 8];
324 struct phys_addr pages[8];
325 } __packed;
326
327 struct be_cmd_resp_mcc_create {
328 struct be_cmd_resp_hdr hdr;
329 u16 id;
330 u16 rsvd0;
331 } __packed;
332
333 /******************** Q Destroy ***************************/
334 /* Type of Queue to be destroyed */
335 enum {
336 QTYPE_EQ = 1,
337 QTYPE_CQ,
338 QTYPE_MCCQ,
339 QTYPE_WRBQ,
340 QTYPE_DPDUQ,
341 QTYPE_SGL
342 };
343
344 struct be_cmd_req_q_destroy {
345 struct be_cmd_req_hdr hdr;
346 u16 id;
347 u16 bypass_flush; /* valid only for rx q destroy */
348 } __packed;
349
350 struct macaddr {
351 u8 byte[ETH_ALEN];
352 };
353
354 struct be_cmd_req_mcast_mac_config {
355 struct be_cmd_req_hdr hdr;
356 u16 num_mac;
357 u8 promiscuous;
358 u8 interface_id;
359 struct macaddr mac[32];
360 } __packed;
361
362 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
363 {
364 return wrb->payload.embedded_payload;
365 }
366
367 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
368 {
369 return &wrb->payload.sgl[0];
370 }
371
372 /******************** Modify EQ Delay *******************/
373 struct be_cmd_req_modify_eq_delay {
374 struct be_cmd_req_hdr hdr;
375 u32 num_eq;
376 struct {
377 u32 eq_id;
378 u32 phase;
379 u32 delay_multiplier;
380 } delay[8];
381 } __packed;
382
383 /******************** Get MAC ADDR *******************/
384
385 #define ETH_ALEN 6
386
387 struct be_cmd_req_get_mac_addr {
388 struct be_cmd_req_hdr hdr;
389 u32 nic_port_count;
390 u32 speed;
391 u32 max_speed;
392 u32 link_state;
393 u32 max_frame_size;
394 u16 size_of_structure;
395 u8 mac_address[ETH_ALEN];
396 u32 rsvd[23];
397 };
398
399 struct be_cmd_resp_get_mac_addr {
400 struct be_cmd_resp_hdr hdr;
401 u32 nic_port_count;
402 u32 speed;
403 u32 max_speed;
404 u32 link_state;
405 u32 max_frame_size;
406 u16 size_of_structure;
407 u8 mac_address[6];
408 u32 rsvd[23];
409 };
410
411 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
412 struct be_queue_info *eq, int eq_delay);
413
414 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
415 struct be_queue_info *cq, struct be_queue_info *eq,
416 bool sol_evts, bool no_delay,
417 int num_cqe_dma_coalesce);
418
419 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
420 int type);
421 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
422 struct be_queue_info *mccq,
423 struct be_queue_info *cq);
424
425 int be_poll_mcc(struct be_ctrl_info *ctrl);
426 unsigned char mgmt_check_supported_fw(struct be_ctrl_info *ctrl,
427 struct beiscsi_hba *phba);
428 unsigned int be_cmd_get_mac_addr(struct beiscsi_hba *phba);
429 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag);
430 /*ISCSI Functuions */
431 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl);
432
433 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem);
434 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba);
435 int be_mcc_notify_wait(struct beiscsi_hba *phba);
436 void be_mcc_notify(struct beiscsi_hba *phba);
437 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba);
438 void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
439 struct be_async_event_link_state *evt);
440 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
441 struct be_mcc_compl *compl);
442
443 int be_mbox_notify(struct be_ctrl_info *ctrl);
444
445 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
446 struct be_queue_info *cq,
447 struct be_queue_info *dq, int length,
448 int entry_size);
449
450 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
451 struct be_dma_mem *q_mem, u32 page_offset,
452 u32 num_pages);
453
454 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
455 struct be_queue_info *wrbq);
456
457 bool is_link_state_evt(u32 trailer);
458
459 struct be_default_pdu_context {
460 u32 dw[4];
461 } __packed;
462
463 struct amap_be_default_pdu_context {
464 u8 dbuf_cindex[13]; /* dword 0 */
465 u8 rsvd0[3]; /* dword 0 */
466 u8 ring_size[4]; /* dword 0 */
467 u8 ring_state[4]; /* dword 0 */
468 u8 rsvd1[8]; /* dword 0 */
469 u8 dbuf_pindex[13]; /* dword 1 */
470 u8 rsvd2; /* dword 1 */
471 u8 pci_func_id[8]; /* dword 1 */
472 u8 rx_pdid[9]; /* dword 1 */
473 u8 rx_pdid_valid; /* dword 1 */
474 u8 default_buffer_size[16]; /* dword 2 */
475 u8 cq_id_recv[10]; /* dword 2 */
476 u8 rx_pdid_not_valid; /* dword 2 */
477 u8 rsvd3[5]; /* dword 2 */
478 u8 rsvd4[32]; /* dword 3 */
479 } __packed;
480
481 struct be_defq_create_req {
482 struct be_cmd_req_hdr hdr;
483 u16 num_pages;
484 u8 ulp_num;
485 u8 rsvd0;
486 struct be_default_pdu_context context;
487 struct phys_addr pages[8];
488 } __packed;
489
490 struct be_defq_create_resp {
491 struct be_cmd_req_hdr hdr;
492 u16 id;
493 u16 rsvd0;
494 } __packed;
495
496 struct be_post_sgl_pages_req {
497 struct be_cmd_req_hdr hdr;
498 u16 num_pages;
499 u16 page_offset;
500 u32 rsvd0;
501 struct phys_addr pages[26];
502 u32 rsvd1;
503 } __packed;
504
505 struct be_wrbq_create_req {
506 struct be_cmd_req_hdr hdr;
507 u16 num_pages;
508 u8 ulp_num;
509 u8 rsvd0;
510 struct phys_addr pages[8];
511 } __packed;
512
513 struct be_wrbq_create_resp {
514 struct be_cmd_resp_hdr resp_hdr;
515 u16 cid;
516 u16 rsvd0;
517 } __packed;
518
519 #define SOL_CID_MASK 0x0000FFC0
520 #define SOL_CODE_MASK 0x0000003F
521 #define SOL_WRB_INDEX_MASK 0x00FF0000
522 #define SOL_CMD_WND_MASK 0xFF000000
523 #define SOL_RES_CNT_MASK 0x7FFFFFFF
524 #define SOL_EXP_CMD_SN_MASK 0xFFFFFFFF
525 #define SOL_HW_STS_MASK 0x000000FF
526 #define SOL_STS_MASK 0x0000FF00
527 #define SOL_RESP_MASK 0x00FF0000
528 #define SOL_FLAGS_MASK 0x7F000000
529 #define SOL_S_MASK 0x80000000
530
531 struct sol_cqe {
532 u32 dw[4];
533 };
534
535 struct amap_sol_cqe {
536 u8 hw_sts[8]; /* dword 0 */
537 u8 i_sts[8]; /* dword 0 */
538 u8 i_resp[8]; /* dword 0 */
539 u8 i_flags[7]; /* dword 0 */
540 u8 s; /* dword 0 */
541 u8 i_exp_cmd_sn[32]; /* dword 1 */
542 u8 code[6]; /* dword 2 */
543 u8 cid[10]; /* dword 2 */
544 u8 wrb_index[8]; /* dword 2 */
545 u8 i_cmd_wnd[8]; /* dword 2 */
546 u8 i_res_cnt[31]; /* dword 3 */
547 u8 valid; /* dword 3 */
548 } __packed;
549
550 #define SOL_ICD_INDEX_MASK 0x0003FFC0
551 struct amap_sol_cqe_ring {
552 u8 hw_sts[8]; /* dword 0 */
553 u8 i_sts[8]; /* dword 0 */
554 u8 i_resp[8]; /* dword 0 */
555 u8 i_flags[7]; /* dword 0 */
556 u8 s; /* dword 0 */
557 u8 i_exp_cmd_sn[32]; /* dword 1 */
558 u8 code[6]; /* dword 2 */
559 u8 icd_index[12]; /* dword 2 */
560 u8 rsvd[6]; /* dword 2 */
561 u8 i_cmd_wnd[8]; /* dword 2 */
562 u8 i_res_cnt[31]; /* dword 3 */
563 u8 valid; /* dword 3 */
564 } __packed;
565
566
567
568 /**
569 * Post WRB Queue Doorbell Register used by the host Storage
570 * stack to notify the
571 * controller of a posted Work Request Block
572 */
573 #define DB_WRB_POST_CID_MASK 0x3FF /* bits 0 - 9 */
574 #define DB_DEF_PDU_WRB_INDEX_MASK 0xFF /* bits 0 - 9 */
575
576 #define DB_DEF_PDU_WRB_INDEX_SHIFT 16
577 #define DB_DEF_PDU_NUM_POSTED_SHIFT 24
578
579 struct fragnum_bits_for_sgl_cra_in {
580 struct be_cmd_req_hdr hdr;
581 u32 num_bits;
582 } __packed;
583
584 struct iscsi_cleanup_req {
585 struct be_cmd_req_hdr hdr;
586 u16 chute;
587 u8 hdr_ring_id;
588 u8 data_ring_id;
589
590 } __packed;
591
592 struct eq_delay {
593 u32 eq_id;
594 u32 phase;
595 u32 delay_multiplier;
596 } __packed;
597
598 struct be_eq_delay_params_in {
599 struct be_cmd_req_hdr hdr;
600 u32 num_eq;
601 struct eq_delay delay[8];
602 } __packed;
603
604 struct ip_address_format {
605 u16 size_of_structure;
606 u8 reserved;
607 u8 ip_type;
608 u8 ip_address[16];
609 u32 rsvd0;
610 } __packed;
611
612 struct tcp_connect_and_offload_in {
613 struct be_cmd_req_hdr hdr;
614 struct ip_address_format ip_address;
615 u16 tcp_port;
616 u16 cid;
617 u16 cq_id;
618 u16 defq_id;
619 struct phys_addr dataout_template_pa;
620 u16 hdr_ring_id;
621 u16 data_ring_id;
622 u8 do_offload;
623 u8 rsvd0[3];
624 } __packed;
625
626 struct tcp_connect_and_offload_out {
627 struct be_cmd_resp_hdr hdr;
628 u32 connection_handle;
629 u16 cid;
630 u16 rsvd0;
631
632 } __packed;
633
634 struct be_mcc_wrb_context {
635 struct MCC_WRB *wrb;
636 int *users_final_status;
637 } __packed;
638
639 #define DB_DEF_PDU_RING_ID_MASK 0x3FF /* bits 0 - 9 */
640 #define DB_DEF_PDU_CQPROC_MASK 0x3FFF /* bits 0 - 9 */
641 #define DB_DEF_PDU_REARM_SHIFT 14
642 #define DB_DEF_PDU_EVENT_SHIFT 15
643 #define DB_DEF_PDU_CQPROC_SHIFT 16
644
645 struct dmsg_cqe {
646 u32 dw[4];
647 } __packed;
648
649 struct tcp_upload_params_in {
650 struct be_cmd_req_hdr hdr;
651 u16 id;
652 u16 upload_type;
653 u32 reset_seq;
654 } __packed;
655
656 struct tcp_upload_params_out {
657 u32 dw[32];
658 } __packed;
659
660 union tcp_upload_params {
661 struct tcp_upload_params_in request;
662 struct tcp_upload_params_out response;
663 } __packed;
664
665 struct be_ulp_fw_cfg {
666 u32 ulp_mode;
667 u32 etx_base;
668 u32 etx_count;
669 u32 sq_base;
670 u32 sq_count;
671 u32 rq_base;
672 u32 rq_count;
673 u32 dq_base;
674 u32 dq_count;
675 u32 lro_base;
676 u32 lro_count;
677 u32 icd_base;
678 u32 icd_count;
679 };
680
681 struct be_fw_cfg {
682 struct be_cmd_req_hdr hdr;
683 u32 be_config_number;
684 u32 asic_revision;
685 u32 phys_port;
686 u32 function_mode;
687 struct be_ulp_fw_cfg ulp[2];
688 u32 function_caps;
689 } __packed;
690
691 #define CMD_ISCSI_COMMAND_INVALIDATE 1
692 #define ISCSI_OPCODE_SCSI_DATA_OUT 5
693 #define OPCODE_COMMON_ISCSI_TCP_CONNECT_AND_OFFLOAD 70
694 #define OPCODE_ISCSI_INI_DRIVER_OFFLOAD_SESSION 41
695 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
696 #define OPCODE_COMMON_ISCSI_CLEANUP 59
697 #define OPCODE_COMMON_TCP_UPLOAD 56
698 #define OPCODE_COMMON_ISCSI_ERROR_RECOVERY_INVALIDATE_COMMANDS 1
699 /* --- CMD_ISCSI_INVALIDATE_CONNECTION_TYPE --- */
700 #define CMD_ISCSI_CONNECTION_INVALIDATE 0x8001
701 #define CMD_ISCSI_CONNECTION_ISSUE_TCP_RST 0x8002
702 #define OPCODE_ISCSI_INI_DRIVER_INVALIDATE_CONNECTION 42
703
704 #define INI_WR_CMD 1 /* Initiator write command */
705 #define INI_TMF_CMD 2 /* Initiator TMF command */
706 #define INI_NOPOUT_CMD 3 /* Initiator; Send a NOP-OUT */
707 #define INI_RD_CMD 5 /* Initiator requesting to send
708 * a read command
709 */
710 #define TGT_CTX_UPDT_CMD 7 /* Target context update */
711 #define TGT_STS_CMD 8 /* Target R2T and other BHS
712 * where only the status number
713 * need to be updated
714 */
715 #define TGT_DATAIN_CMD 9 /* Target Data-Ins in response
716 * to read command
717 */
718 #define TGT_SOS_PDU 10 /* Target:standalone status
719 * response
720 */
721 #define TGT_DM_CMD 11 /* Indicates that the bhs
722 * preparedby
723 * driver should not be touched
724 */
725 /* --- CMD_CHUTE_TYPE --- */
726 #define CMD_CONNECTION_CHUTE_0 1
727 #define CMD_CONNECTION_CHUTE_1 2
728 #define CMD_CONNECTION_CHUTE_2 3
729
730 #define EQ_MAJOR_CODE_COMPLETION 0
731
732 #define CMD_ISCSI_SESSION_DEL_CFG_FROM_FLASH 0
733 #define CMD_ISCSI_SESSION_SAVE_CFG_ON_FLASH 1
734
735 /* --- CONNECTION_UPLOAD_PARAMS --- */
736 /* These parameters are used to define the type of upload desired. */
737 #define CONNECTION_UPLOAD_GRACEFUL 1 /* Graceful upload */
738 #define CONNECTION_UPLOAD_ABORT_RESET 2 /* Abortive upload with
739 * reset
740 */
741 #define CONNECTION_UPLOAD_ABORT 3 /* Abortive upload without
742 * reset
743 */
744 #define CONNECTION_UPLOAD_ABORT_WITH_SEQ 4 /* Abortive upload with reset,
745 * sequence number by driver */
746
747 /* Returns byte size of given field with a structure. */
748
749 /* Returns the number of items in the field array. */
750 #define BE_NUMBER_OF_FIELD(_type_, _field_) \
751 (FIELD_SIZEOF(_type_, _field_)/sizeof((((_type_ *)0)->_field_[0])))\
752
753 /**
754 * Different types of iSCSI completions to host driver for both initiator
755 * and taget mode
756 * of operation.
757 */
758 #define SOL_CMD_COMPLETE 1 /* Solicited command completed
759 * normally
760 */
761 #define SOL_CMD_KILLED_DATA_DIGEST_ERR 2 /* Solicited command got
762 * invalidated internally due
763 * to Data Digest error
764 */
765 #define CXN_KILLED_PDU_SIZE_EXCEEDS_DSL 3 /* Connection got invalidated
766 * internally
767 * due to a recieved PDU
768 * size > DSL
769 */
770 #define CXN_KILLED_BURST_LEN_MISMATCH 4 /* Connection got invalidated
771 * internally due ti received
772 * PDU sequence size >
773 * FBL/MBL.
774 */
775 #define CXN_KILLED_AHS_RCVD 5 /* Connection got invalidated
776 * internally due to a recieved
777 * PDU Hdr that has
778 * AHS */
779 #define CXN_KILLED_HDR_DIGEST_ERR 6 /* Connection got invalidated
780 * internally due to Hdr Digest
781 * error
782 */
783 #define CXN_KILLED_UNKNOWN_HDR 7 /* Connection got invalidated
784 * internally
785 * due to a bad opcode in the
786 * pdu hdr
787 */
788 #define CXN_KILLED_STALE_ITT_TTT_RCVD 8 /* Connection got invalidated
789 * internally due to a recieved
790 * ITT/TTT that does not belong
791 * to this Connection
792 */
793 #define CXN_KILLED_INVALID_ITT_TTT_RCVD 9 /* Connection got invalidated
794 * internally due to recieved
795 * ITT/TTT value > Max
796 * Supported ITTs/TTTs
797 */
798 #define CXN_KILLED_RST_RCVD 10 /* Connection got invalidated
799 * internally due to an
800 * incoming TCP RST
801 */
802 #define CXN_KILLED_TIMED_OUT 11 /* Connection got invalidated
803 * internally due to timeout on
804 * tcp segment 12 retransmit
805 * attempts failed
806 */
807 #define CXN_KILLED_RST_SENT 12 /* Connection got invalidated
808 * internally due to TCP RST
809 * sent by the Tx side
810 */
811 #define CXN_KILLED_FIN_RCVD 13 /* Connection got invalidated
812 * internally due to an
813 * incoming TCP FIN.
814 */
815 #define CXN_KILLED_BAD_UNSOL_PDU_RCVD 14 /* Connection got invalidated
816 * internally due to bad
817 * unsolicited PDU Unsolicited
818 * PDUs are PDUs with
819 * ITT=0xffffffff
820 */
821 #define CXN_KILLED_BAD_WRB_INDEX_ERROR 15 /* Connection got invalidated
822 * internally due to bad WRB
823 * index.
824 */
825 #define CXN_KILLED_OVER_RUN_RESIDUAL 16 /* Command got invalidated
826 * internally due to recived
827 * command has residual
828 * over run bytes.
829 */
830 #define CXN_KILLED_UNDER_RUN_RESIDUAL 17 /* Command got invalidated
831 * internally due to recived
832 * command has residual under
833 * run bytes.
834 */
835 #define CMD_KILLED_INVALID_STATSN_RCVD 18 /* Command got invalidated
836 * internally due to a recieved
837 * PDU has an invalid StatusSN
838 */
839 #define CMD_KILLED_INVALID_R2T_RCVD 19 /* Command got invalidated
840 * internally due to a recieved
841 * an R2T with some invalid
842 * fields in it
843 */
844 #define CMD_CXN_KILLED_LUN_INVALID 20 /* Command got invalidated
845 * internally due to received
846 * PDU has an invalid LUN.
847 */
848 #define CMD_CXN_KILLED_ICD_INVALID 21 /* Command got invalidated
849 * internally due to the
850 * corresponding ICD not in a
851 * valid state
852 */
853 #define CMD_CXN_KILLED_ITT_INVALID 22 /* Command got invalidated due
854 * to received PDU has an
855 * invalid ITT.
856 */
857 #define CMD_CXN_KILLED_SEQ_OUTOFORDER 23 /* Command got invalidated due
858 * to received sequence buffer
859 * offset is out of order.
860 */
861 #define CMD_CXN_KILLED_INVALID_DATASN_RCVD 24 /* Command got invalidated
862 * internally due to a
863 * recieved PDU has an invalid
864 * DataSN
865 */
866 #define CXN_INVALIDATE_NOTIFY 25 /* Connection invalidation
867 * completion notify.
868 */
869 #define CXN_INVALIDATE_INDEX_NOTIFY 26 /* Connection invalidation
870 * completion
871 * with data PDU index.
872 */
873 #define CMD_INVALIDATED_NOTIFY 27 /* Command invalidation
874 * completionnotifify.
875 */
876 #define UNSOL_HDR_NOTIFY 28 /* Unsolicited header notify.*/
877 #define UNSOL_DATA_NOTIFY 29 /* Unsolicited data notify.*/
878 #define UNSOL_DATA_DIGEST_ERROR_NOTIFY 30 /* Unsolicited data digest
879 * error notify.
880 */
881 #define DRIVERMSG_NOTIFY 31 /* TCP acknowledge based
882 * notification.
883 */
884 #define CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN 32 /* Connection got invalidated
885 * internally due to command
886 * and data are not on same
887 * connection.
888 */
889 #define SOL_CMD_KILLED_DIF_ERR 33 /* Solicited command got
890 * invalidated internally due
891 * to DIF error
892 */
893 #define CXN_KILLED_SYN_RCVD 34 /* Connection got invalidated
894 * internally due to incoming
895 * TCP SYN
896 */
897 #define CXN_KILLED_IMM_DATA_RCVD 35 /* Connection got invalidated
898 * internally due to an
899 * incoming Unsolicited PDU
900 * that has immediate data on
901 * the cxn
902 */
903
904 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
905 bool embedded, u8 sge_cnt);
906
907 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
908 u8 subsystem, u8 opcode, int cmd_len);
909
910 #endif /* !BEISCSI_CMDS_H */
Linux with added FPC-III support