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Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / staging / cxt1e1 / musycc.c
blobd3f5a5b52dc36d1dcd17a4751786beaee201df47
1 /*
2 * $Id: musycc.c,v 2.1 2007/08/15 23:32:17 rickd PMCC4_3_1B $
3 */
4
5 unsigned int max_intcnt = 0;
6 unsigned int max_bh = 0;
7
8 /*-----------------------------------------------------------------------------
9 * musycc.c -
10 *
11 * Copyright (C) 2007 One Stop Systems, Inc.
12 * Copyright (C) 2003-2006 SBE, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * For further information, contact via email: support@onestopsystems.com
25 * One Stop Systems, Inc. Escondido, California U.S.A.
26 *-----------------------------------------------------------------------------
27 * RCS info:
28 * RCS revision: $Revision: 2.1 $
29 * Last changed on $Date: 2007/08/15 23:32:17 $
30 * Changed by $Author: rickd $
31 *-----------------------------------------------------------------------------
32 * $Log: musycc.c,v $
33 * Revision 2.1 2007/08/15 23:32:17 rickd
34 * Use 'if 0' instead of GNU comment delimeter to avoid line wrap induced compiler errors.
35 *
36 * Revision 2.0 2007/08/15 22:13:20 rickd
37 * Update to printf pointer %p usage and correct some UINT to ULONG for
38 * 64bit comptibility.
39 *
40 * Revision 1.7 2006/04/21 00:56:40 rickd
41 * workqueue files now prefixed with <sbecom> prefix.
42 *
43 * Revision 1.6 2005/10/27 18:54:19 rickd
44 * Clean out old code. Default to HDLC_FCS16, not TRANS.
45 *
46 * Revision 1.5 2005/10/17 23:55:28 rickd
47 * Initial port of NCOMM support patches from original work found
48 * in pmc_c4t1e1 as updated by NCOMM. Ref: CONFIG_SBE_PMCC4_NCOMM.
49 *
50 * Revision 1.4 2005/10/13 20:35:25 rickd
51 * Cleanup warning for unused <flags> variable.
52 *
53 * Revision 1.3 2005/10/13 19:19:22 rickd
54 * Disable redundant driver removal cleanup code.
55 *
56 * Revision 1.2 2005/10/11 18:36:16 rickd
57 * Clean up warning messages caused by de-implemented some <flags> associated
58 * with spin_lock() removals.
59 *
60 * Revision 1.1 2005/10/05 00:45:28 rickd
61 * Re-enable xmit on flow-controlled and full channel to fix restart hang.
62 * Add some temp spin-lock debug code (rld_spin_owner).
63 *
64 * Revision 1.0 2005/09/28 00:10:06 rickd
65 * Initial release for C4T1E1 support. Lots of transparent
66 * mode updates.
67 *
68 *-----------------------------------------------------------------------------
69 */
70
71 char SBEid_pmcc4_musyccc[] =
72 "@(#)musycc.c - $Revision: 2.1 $ (c) Copyright 2004-2006 SBE, Inc.";
73
74 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
75
76 #include <linux/types.h>
77 #include "pmcc4_sysdep.h"
78 #include <linux/kernel.h>
79 #include <linux/errno.h>
80 #include <linux/init.h>
81 #include "sbecom_inline_linux.h"
82 #include "libsbew.h"
83 #include "pmcc4_private.h"
84 #include "pmcc4.h"
85 #include "musycc.h"
86
87 #ifdef SBE_INCLUDE_SYMBOLS
88 #define STATIC
89 #else
90 #define STATIC static
91 #endif
92
93 #define sd_find_chan(ci,ch) c4_find_chan(ch)
94
95
96 /*******************************************************************/
97 /* global driver variables */
98 extern ci_t *c4_list;
99 extern int drvr_state;
100 extern int log_level;
101
102 extern int max_mru;
103 extern int max_mtu;
104 extern int max_rxdesc_used;
105 extern int max_txdesc_used;
106 extern ci_t *CI; /* dummy pointr to board ZEROE's data - DEBUG
107 * USAGE */
108
109
110 /*******************************************************************/
111 /* forward references */
112 void c4_fifo_free (mpi_t *, int);
113 void c4_wk_chan_restart (mch_t *);
114 void musycc_bh_tx_eom (mpi_t *, int);
115 int musycc_chan_up (ci_t *, int);
116 status_t __init musycc_init (ci_t *);
117 STATIC void __init musycc_init_port (mpi_t *);
118 void musycc_intr_bh_tasklet (ci_t *);
119 void musycc_serv_req (mpi_t *, u_int32_t);
120 void musycc_update_timeslots (mpi_t *);
121
122 /*******************************************************************/
123
124 #if 1
125 STATIC int
126 musycc_dump_rxbuffer_ring (mch_t * ch, int lockit)
127 {
128 struct mdesc *m;
129 unsigned long flags = 0;
130
131 u_int32_t status;
132 int n;
133
134 if (lockit)
135 {
136 spin_lock_irqsave (&ch->ch_rxlock, flags);
137 }
138 if (ch->rxd_num == 0)
139 {
140 pr_info(" ZERO receive buffers allocated for this channel.");
141 } else
142 {
143 FLUSH_MEM_READ ();
144 m = &ch->mdr[ch->rxix_irq_srv];
145 for (n = ch->rxd_num; n; n--)
146 {
147 status = le32_to_cpu (m->status);
148 {
149 pr_info("%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
150 (m == &ch->mdr[ch->rxix_irq_srv]) ? 'F' : ' ',
151 (unsigned long) m, n,
152 status,
153 m->data ? (status & HOST_RX_OWNED ? 'H' : 'M') : '-',
154 status & POLL_DISABLED ? 'P' : '-',
155 status & EOBIRQ_ENABLE ? 'b' : '-',
156 status & EOMIRQ_ENABLE ? 'm' : '-',
157 status & LENGTH_MASK,
158 le32_to_cpu (m->data), le32_to_cpu (m->next));
159 #ifdef RLD_DUMP_BUFDATA
160 {
161 u_int32_t *dp;
162 int len = status & LENGTH_MASK;
163
164 #if 1
165 if (m->data && (status & HOST_RX_OWNED))
166 #else
167 if (m->data) /* always dump regardless of valid RX
168 * data */
169 #endif
170 {
171 dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
172 if (len >= 0x10)
173 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
174 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
175 else if (len >= 0x08)
176 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
177 *dp, *(dp + 1));
178 else
179 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
180 }
181 }
182 #endif
183 }
184 m = m->snext;
185 }
186 } /* -for- */
187 pr_info("\n");
188
189 if (lockit)
190 {
191 spin_unlock_irqrestore (&ch->ch_rxlock, flags);
192 }
193 return 0;
194 }
195 #endif
196
197 #if 1
198 STATIC int
199 musycc_dump_txbuffer_ring (mch_t * ch, int lockit)
200 {
201 struct mdesc *m;
202 unsigned long flags = 0;
203 u_int32_t status;
204 int n;
205
206 if (lockit)
207 {
208 spin_lock_irqsave (&ch->ch_txlock, flags);
209 }
210 if (ch->txd_num == 0)
211 {
212 pr_info(" ZERO transmit buffers allocated for this channel.");
213 } else
214 {
215 FLUSH_MEM_READ ();
216 m = ch->txd_irq_srv;
217 for (n = ch->txd_num; n; n--)
218 {
219 status = le32_to_cpu (m->status);
220 {
221 pr_info("%c%c %08lx[%2d]: sts %08x (%c%c%c%c:%d.) Data [%08x] Next [%08x]\n",
222 (m == ch->txd_usr_add) ? 'F' : ' ',
223 (m == ch->txd_irq_srv) ? 'L' : ' ',
224 (unsigned long) m, n,
225 status,
226 m->data ? (status & MUSYCC_TX_OWNED ? 'M' : 'H') : '-',
227 status & POLL_DISABLED ? 'P' : '-',
228 status & EOBIRQ_ENABLE ? 'b' : '-',
229 status & EOMIRQ_ENABLE ? 'm' : '-',
230 status & LENGTH_MASK,
231 le32_to_cpu (m->data), le32_to_cpu (m->next));
232 #ifdef RLD_DUMP_BUFDATA
233 {
234 u_int32_t *dp;
235 int len = status & LENGTH_MASK;
236
237 if (m->data)
238 {
239 dp = (u_int32_t *) OS_phystov ((void *) (le32_to_cpu (m->data)));
240 if (len >= 0x10)
241 pr_info(" %x[%x]: %08X %08X %08X %08x\n", (u_int32_t) dp, len,
242 *dp, *(dp + 1), *(dp + 2), *(dp + 3));
243 else if (len >= 0x08)
244 pr_info(" %x[%x]: %08X %08X\n", (u_int32_t) dp, len,
245 *dp, *(dp + 1));
246 else
247 pr_info(" %x[%x]: %08X\n", (u_int32_t) dp, len, *dp);
248 }
249 }
250 #endif
251 }
252 m = m->snext;
253 }
254 } /* -for- */
255 pr_info("\n");
256
257 if (lockit)
258 {
259 spin_unlock_irqrestore (&ch->ch_txlock, flags);
260 }
261 return 0;
262 }
263 #endif
264
265
266 /*
267 * The following supports a backdoor debug facility which can be used to
268 * display the state of a board's channel.
269 */
270
271 status_t
272 musycc_dump_ring (ci_t * ci, unsigned int chan)
273 {
274 mch_t *ch;
275
276 if (chan >= MAX_CHANS_USED)
277 {
278 return SBE_DRVR_FAIL; /* E2BIG */
279 }
280 {
281 int bh;
282
283 bh = atomic_read (&ci->bh_pending);
284 pr_info(">> bh_pend %d [%d] ihead %d itail %d [%d] th_cnt %d bh_cnt %d wdcnt %d note %d\n",
285 bh, max_bh, ci->iqp_headx, ci->iqp_tailx, max_intcnt,
286 ci->intlog.drvr_intr_thcount,
287 ci->intlog.drvr_intr_bhcount,
288 ci->wdcount, ci->wd_notify);
289 max_bh = 0; /* reset counter */
290 max_intcnt = 0; /* reset counter */
291 }
292
293 if (!(ch = sd_find_chan (dummy, chan)))
294 {
295 pr_info(">> musycc_dump_ring: channel %d not up.\n", chan);
296 return ENOENT;
297 }
298 pr_info(">> CI %p CHANNEL %3d @ %p: state %x status/p %x/%x\n", ci, chan, ch, ch->state,
299 ch->status, ch->p.status);
300 pr_info("--------------------------------\nTX Buffer Ring - Channel %d, txd_num %d. (bd/ch pend %d %d), TXD required %d, txpkt %lu\n",
301 chan, ch->txd_num,
302 (u_int32_t) atomic_read (&ci->tx_pending), (u_int32_t) atomic_read (&ch->tx_pending), ch->txd_required, ch->s.tx_packets);
303 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
304 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
305 sd_queue_stopped (ch->user),
306 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
307 musycc_dump_txbuffer_ring (ch, 1);
308 pr_info("RX Buffer Ring - Channel %d, rxd_num %d. IRQ_SRV[%d] 0x%p, start_rx %x rxpkt %lu\n",
309 chan, ch->rxd_num, ch->rxix_irq_srv,
310 &ch->mdr[ch->rxix_irq_srv], ch->ch_start_rx, ch->s.rx_packets);
311 musycc_dump_rxbuffer_ring (ch, 1);
312
313 return SBE_DRVR_SUCCESS;
314 }
315
316
317 status_t
318 musycc_dump_rings (ci_t * ci, unsigned int start_chan)
319 {
320 unsigned int chan;
321
322 for (chan = start_chan; chan < (start_chan + 5); chan++)
323 musycc_dump_ring (ci, chan);
324 return SBE_DRVR_SUCCESS;
325 }
326
327
328 /*
329 * NOTE on musycc_init_mdt(): These MUSYCC writes are only operational after
330 * a MUSYCC GROUP_INIT command has been issued.
331 */
332
333 void
334 musycc_init_mdt (mpi_t * pi)
335 {
336 u_int32_t *addr, cfg;
337 int i;
338
339 /*
340 * This Idle Code insertion takes effect prior to channel's first
341 * transmitted message. After that, each message contains its own Idle
342 * Code information which is to be issued after the message is
343 * transmitted (Ref.MUSYCC 5.2.2.3: MCENBL bit in Group Configuration
344 * Descriptor).
345 */
346
347 addr = (u_int32_t *) ((u_long) pi->reg + MUSYCC_MDT_BASE03_ADDR);
348 cfg = CFG_CH_FLAG_7E << IDLE_CODE;
349
350 for (i = 0; i < 32; addr++, i++)
351 {
352 pci_write_32 (addr, cfg);
353 }
354 }
355
356
357 /* Set TX thp to the next unprocessed md */
358
359 void
360 musycc_update_tx_thp (mch_t * ch)
361 {
362 struct mdesc *md;
363 unsigned long flags;
364
365 spin_lock_irqsave (&ch->ch_txlock, flags);
366 while (1)
367 {
368 md = ch->txd_irq_srv;
369 FLUSH_MEM_READ ();
370 if (!md->data)
371 {
372 /* No MDs with buffers to process */
373 spin_unlock_irqrestore (&ch->ch_txlock, flags);
374 return;
375 }
376 if ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED)
377 {
378 /* this is the MD to restart TX with */
379 break;
380 }
381 /*
382 * Otherwise, we have a valid, host-owned message descriptor which
383 * has been successfully transmitted and whose buffer can be freed,
384 * so... process this MD, it's owned by the host. (This might give
385 * as a new, updated txd_irq_srv.)
386 */
387 musycc_bh_tx_eom (ch->up, ch->gchan);
388 }
389 md = ch->txd_irq_srv;
390 ch->up->regram->thp[ch->gchan] = cpu_to_le32 (OS_vtophys (md));
391 FLUSH_MEM_WRITE ();
392
393 if (ch->tx_full)
394 {
395 ch->tx_full = 0;
396 ch->txd_required = 0;
397 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
398 * channel */
399 }
400 spin_unlock_irqrestore (&ch->ch_txlock, flags);
401
402 #ifdef RLD_TRANS_DEBUG
403 pr_info("++ musycc_update_tx_thp[%d]: setting thp = %p, sts %x\n", ch->channum, md, md->status);
404 #endif
405 }
406
407
408 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
409 /*
410 * This is the workq task executed by the OS when our queue_work() is
411 * scheduled and run. It can fire off either RX or TX ACTIVATION depending
412 * upon the channel's ch_start_tx and ch_start_rx variables. This routine
413 * is implemented as a work queue so that the call to the service request is
414 * able to sleep, awaiting an interrupt acknowledgment response (SACK) from
415 * the hardware.
416 */
417
418 void
419 musycc_wq_chan_restart (void *arg) /* channel private structure */
420 {
421 mch_t *ch;
422 mpi_t *pi;
423 struct mdesc *md;
424 #if 0
425 unsigned long flags;
426 #endif
427
428 ch = container_of(arg, struct c4_chan_info, ch_work);
429 pi = ch->up;
430
431 #ifdef RLD_TRANS_DEBUG
432 pr_info("wq_chan_restart[%d]: start_RT[%d/%d] status %x\n",
433 ch->channum, ch->ch_start_rx, ch->ch_start_tx, ch->status);
434
435 #endif
436
437 /**********************************/
438 /** check for RX restart request **/
439 /**********************************/
440
441 if ((ch->ch_start_rx) && (ch->status & RX_ENABLED))
442 {
443
444 ch->ch_start_rx = 0;
445 #if defined(RLD_TRANS_DEBUG) || defined(RLD_RXACT_DEBUG)
446 {
447 static int hereb4 = 7;
448
449 if (hereb4) /* RLD DEBUG */
450 {
451 hereb4--;
452 #ifdef RLD_TRANS_DEBUG
453 md = &ch->mdr[ch->rxix_irq_srv];
454 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
455 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
456 ch->s.rx_packets);
457 #elif defined(RLD_RXACT_DEBUG)
458 md = &ch->mdr[ch->rxix_irq_srv];
459 pr_info("++ musycc_wq_chan_restart[%d] CHAN RX ACTIVATE: rxix_irq_srv %d, md %p sts %x, rxpkt %lu\n",
460 ch->channum, ch->rxix_irq_srv, md, le32_to_cpu (md->status),
461 ch->s.rx_packets);
462 musycc_dump_rxbuffer_ring (ch, 1); /* RLD DEBUG */
463 #endif
464 }
465 }
466 #endif
467 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | ch->gchan);
468 }
469 /**********************************/
470 /** check for TX restart request **/
471 /**********************************/
472
473 if ((ch->ch_start_tx) && (ch->status & TX_ENABLED))
474 {
475 /* find next unprocessed message, then set TX thp to it */
476 musycc_update_tx_thp (ch);
477
478 #if 0
479 spin_lock_irqsave (&ch->ch_txlock, flags);
480 #endif
481 md = ch->txd_irq_srv;
482 if (!md)
483 {
484 #ifdef RLD_TRANS_DEBUG
485 pr_info("-- musycc_wq_chan_restart[%d]: WARNING, starting NULL md\n", ch->channum);
486 #endif
487 #if 0
488 spin_unlock_irqrestore (&ch->ch_txlock, flags);
489 #endif
490 } else if (md->data && ((le32_to_cpu (md->status)) & MUSYCC_TX_OWNED))
491 {
492 ch->ch_start_tx = 0;
493 #if 0
494 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
495 #endif
496 #ifdef RLD_TRANS_DEBUG
497 pr_info("++ musycc_wq_chan_restart() CHAN TX ACTIVATE: chan %d txd_irq_srv %p = sts %x, txpkt %lu\n",
498 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status, ch->s.tx_packets);
499 #endif
500 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION | ch->gchan);
501 }
502 #ifdef RLD_RESTART_DEBUG
503 else
504 {
505 /* retain request to start until retried and we have data to xmit */
506 pr_info("-- musycc_wq_chan_restart[%d]: DELAYED due to md %p sts %x data %x, start_tx %x\n",
507 ch->channum, md,
508 le32_to_cpu (md->status),
509 le32_to_cpu (md->data), ch->ch_start_tx);
510 musycc_dump_txbuffer_ring (ch, 0);
511 #if 0
512 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow interrupts for service request */
513 #endif
514 }
515 #endif
516 }
517 }
518 #endif
519
520
521 /*
522 * Channel restart either fires of a workqueue request (2.6) or lodges a
523 * watchdog activation sequence (2.4).
524 */
525
526 void
527 musycc_chan_restart (mch_t * ch)
528 {
529 #ifdef RLD_RESTART_DEBUG
530 pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
531 ch->channum, ch->txd_irq_srv, ch->txd_irq_srv->status);
532 #endif
533
534 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
535 /* 2.6 - find next unprocessed message, then set TX thp to it */
536 #ifdef RLD_RESTART_DEBUG
537 pr_info(">> musycc_chan_restart: scheduling Chan %x workQ @ %p\n", ch->channum, &ch->ch_work);
538 #endif
539 c4_wk_chan_restart (ch); /* work queue mechanism fires off: Ref:
540 * musycc_wq_chan_restart () */
541
542 #else
543
544
545 /* 2.4 - find next unprocessed message, then set TX thp to it */
546 #ifdef RLD_RESTART_DEBUG
547 pr_info(">> musycc_chan_restart: scheduling Chan %x start_tx %x\n", ch->channum, ch->ch_start_tx);
548 #endif
549 /* restart transmission from background loop */
550 ch->up->up->wd_notify = WD_NOTIFY_1TX;
551 #endif
552 }
553
554
555 #if 0
556 void
557 musycc_cleanup (ci_t * ci)
558 {
559 mpi_t *pi;
560 int i, j;
561
562 /* free up driver resources */
563 ci->state = C_INIT; /* mark as hardware not available */
564
565 for (i = 0; i < ci->max_ports; i++)
566 {
567 pi = &ci->port[i];
568 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)
569 c4_wq_port_cleanup (pi);
570 #endif
571 for (j = 0; j < MUSYCC_NCHANS; j++)
572 {
573 if (pi->chan[j])
574 OS_kfree (pi->chan[j]); /* free mch_t struct */
575 }
576 OS_kfree (pi->regram_saved);
577 }
578 #if 0
579 /* obsolete - watchdog is now static w/in ci_t */
580 OS_free_watchdog (ci->wd);
581 #endif
582 OS_kfree (ci->iqd_p_saved);
583 OS_kfree (ci);
584 }
585 #endif
586
587 void
588 rld_put_led (mpi_t * pi, u_int32_t ledval)
589 {
590 static u_int32_t led = 0;
591
592 if (ledval == 0)
593 led = 0;
594 else
595 led |= ledval;
596
597 pci_write_32 ((u_int32_t *) &pi->up->cpldbase->leds, led); /* RLD DEBUG TRANHANG */
598 }
599
600
601 #define MUSYCC_SR_RETRY_CNT 9
602
603 void
604 musycc_serv_req (mpi_t * pi, u_int32_t req)
605 {
606 volatile u_int32_t r;
607 int rcnt;
608
609 /*
610 * PORT NOTE: Semaphore protect service loop guarantees only a single
611 * operation at a time. Per MUSYCC Manual - "Issuing service requests to
612 * the same channel group without first receiving ACK from each request
613 * may cause the host to lose track of which service request has been
614 * acknowledged."
615 */
616
617 SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* only 1 thru here, per
618 * group */
619
620 if (pi->sr_last == req)
621 {
622 #ifdef RLD_TRANS_DEBUG
623 pr_info(">> same SR, Port %d Req %x\n", pi->portnum, req);
624 #endif
625
626 /*
627 * The most likely repeated request is the channel activation command
628 * which follows the occurrence of a Transparent mode TX ONR or a
629 * BUFF error. If the previous command was a CHANNEL ACTIVATE,
630 * precede it with a NOOP command in order maintain coherent control
631 * of this current (re)ACTIVATE.
632 */
633
634 r = (pi->sr_last & ~SR_GCHANNEL_MASK);
635 if ((r == (SR_CHANNEL_ACTIVATE | SR_TX_DIRECTION)) ||
636 (r == (SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION)))
637 {
638 #ifdef RLD_TRANS_DEBUG
639 pr_info(">> same CHAN ACT SR, Port %d Req %x => issue SR_NOOP CMD\n", pi->portnum, req);
640 #endif
641 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
642 musycc_serv_req (pi, SR_NOOP);
643 SD_SEM_TAKE (&pi->sr_sem_busy, "serv"); /* relock & continue w/
644 * original req */
645 } else if (req == SR_NOOP)
646 {
647 /* no need to issue back-to-back SR_NOOP commands at this time */
648 #ifdef RLD_TRANS_DEBUG
649 pr_info(">> same Port SR_NOOP skipped, Port %d\n", pi->portnum);
650 #endif
651 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow this next request */
652 return;
653 }
654 }
655 rcnt = 0;
656 pi->sr_last = req;
657 rewrite:
658 pci_write_32 ((u_int32_t *) &pi->reg->srd, req);
659 FLUSH_MEM_WRITE ();
660
661 /*
662 * Per MUSYCC Manual, Section 6.1,2 - "When writing an SCR service
663 * request, the host must ensure at least one PCI bus clock cycle has
664 * elapsed before writing another service request. To meet this minimum
665 * elapsed service request write timing interval, it is recommended that
666 * the host follow any SCR write with another operation which reads from
667 * the same address."
668 */
669 r = pci_read_32 ((u_int32_t *) &pi->reg->srd); /* adhere to write
670 * timing imposition */
671
672
673 if ((r != req) && (req != SR_CHIP_RESET) && (++rcnt <= MUSYCC_SR_RETRY_CNT))
674 {
675 if (log_level >= LOG_MONITOR)
676 pr_info("%s: %d - reissue srv req/last %x/%x (hdw reads %x), Chan %d.\n",
677 pi->up->devname, rcnt, req, pi->sr_last, r,
678 (pi->portnum * MUSYCC_NCHANS) + (req & 0x1f));
679 OS_uwait_dummy (); /* this delay helps reduce reissue counts
680 * (reason not yet researched) */
681 goto rewrite;
682 }
683 if (rcnt > MUSYCC_SR_RETRY_CNT)
684 {
685 pr_warning("%s: failed service request (#%d)= %x, group %d.\n",
686 pi->up->devname, MUSYCC_SR_RETRY_CNT, req, pi->portnum);
687 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
688 return;
689 }
690 if (req == SR_CHIP_RESET)
691 {
692 /*
693 * PORT NOTE: the CHIP_RESET command is NOT ack'd by the MUSYCC, thus
694 * the upcoming delay is used. Though the MUSYCC documentation
695 * suggests a read-after-write would supply the required delay, it's
696 * unclear what CPU/BUS clock speeds might have been assumed when
697 * suggesting this 'lack of ACK' workaround. Thus the use of uwait.
698 */
699 OS_uwait (100000, "icard"); /* 100ms */
700 } else
701 {
702 FLUSH_MEM_READ ();
703 SD_SEM_TAKE (&pi->sr_sem_wait, "sakack"); /* sleep until SACK
704 * interrupt occurs */
705 }
706 SD_SEM_GIVE (&pi->sr_sem_busy); /* allow any next request */
707 }
708
709
710 #ifdef SBE_PMCC4_ENABLE
711 void
712 musycc_update_timeslots (mpi_t * pi)
713 {
714 int i, ch;
715 char e1mode = IS_FRAME_ANY_E1 (pi->p.port_mode);
716
717 for (i = 0; i < 32; i++)
718 {
719 int usedby = 0, last = 0, ts, j, bits[8];
720
721 u_int8_t lastval = 0;
722
723 if (((i == 0) && e1mode) || /* disable if E1 mode */
724 ((i == 16) && ((pi->p.port_mode == CFG_FRAME_E1CRC_CAS) || (pi->p.port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
725 || ((i > 23) && (!e1mode))) /* disable if T1 mode */
726 {
727 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
728 } else
729 {
730 pi->tsm[i] = 0x00; /* make tslot available for assignment */
731 }
732 for (j = 0; j < 8; j++)
733 bits[j] = -1;
734 for (ch = 0; ch < MUSYCC_NCHANS; ch++)
735 {
736 if ((pi->chan[ch]->state == UP) && (pi->chan[ch]->p.bitmask[i]))
737 {
738 usedby++;
739 last = ch;
740 lastval = pi->chan[ch]->p.bitmask[i];
741 for (j = 0; j < 8; j++)
742 if (lastval & (1 << j))
743 bits[j] = ch;
744 pi->tsm[i] |= lastval;
745 }
746 }
747 if (!usedby)
748 ts = 0;
749 else if ((usedby == 1) && (lastval == 0xff))
750 ts = (4 << 5) | last;
751 else if ((usedby == 1) && (lastval == 0x7f))
752 ts = (5 << 5) | last;
753 else
754 {
755 int idx;
756
757 if (bits[0] < 0)
758 ts = (6 << 5) | (idx = last);
759 else
760 ts = (7 << 5) | (idx = bits[0]);
761 for (j = 1; j < 8; j++)
762 {
763 pi->regram->rscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
764 pi->regram->tscm[idx * 8 + j] = (bits[j] < 0) ? 0 : (0x80 | bits[j]);
765 }
766 }
767 pi->regram->rtsm[i] = ts;
768 pi->regram->ttsm[i] = ts;
769 }
770 FLUSH_MEM_WRITE ();
771
772 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
773 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
774 musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_RX_DIRECTION);
775 musycc_serv_req (pi, SR_SUBCHANNEL_MAP | SR_TX_DIRECTION);
776 }
777 #endif
778
779
780 #ifdef SBE_WAN256T3_ENABLE
781 void
782 musycc_update_timeslots (mpi_t * pi)
783 {
784 mch_t *ch;
785
786 u_int8_t ts, hmask, tsen;
787 int gchan;
788 int i;
789
790 #ifdef SBE_PMCC4_ENABLE
791 hmask = (0x1f << pi->up->p.hypersize) & 0x1f;
792 #endif
793 #ifdef SBE_WAN256T3_ENABLE
794 hmask = (0x1f << hyperdummy) & 0x1f;
795 #endif
796 for (i = 0; i < 128; i++)
797 {
798 gchan = ((pi->portnum * MUSYCC_NCHANS) + (i & hmask)) % MUSYCC_NCHANS;
799 ch = pi->chan[gchan];
800 if (ch->p.mode_56k)
801 tsen = MODE_56KBPS;
802 else
803 tsen = MODE_64KBPS; /* also the default */
804 ts = ((pi->portnum % 4) == (i / 32)) ? (tsen << 5) | (i & hmask) : 0;
805 pi->regram->rtsm[i] = ts;
806 pi->regram->ttsm[i] = ts;
807 }
808 FLUSH_MEM_WRITE ();
809 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_RX_DIRECTION);
810 musycc_serv_req (pi, SR_TIMESLOT_MAP | SR_TX_DIRECTION);
811 }
812 #endif
813
814
815 /*
816 * This routine converts a generic library channel configuration parameter
817 * into a hardware specific register value (IE. MUSYCC CCD Register).
818 */
819 u_int32_t
820 musycc_chan_proto (int proto)
821 {
822 int reg;
823
824 switch (proto)
825 {
826 case CFG_CH_PROTO_TRANS: /* 0 */
827 reg = MUSYCC_CCD_TRANS;
828 break;
829 case CFG_CH_PROTO_SS7: /* 1 */
830 reg = MUSYCC_CCD_SS7;
831 break;
832 default:
833 case CFG_CH_PROTO_ISLP_MODE: /* 4 */
834 case CFG_CH_PROTO_HDLC_FCS16: /* 2 */
835 reg = MUSYCC_CCD_HDLC_FCS16;
836 break;
837 case CFG_CH_PROTO_HDLC_FCS32: /* 3 */
838 reg = MUSYCC_CCD_HDLC_FCS32;
839 break;
840 }
841
842 return reg;
843 }
844
845 #ifdef SBE_WAN256T3_ENABLE
846 STATIC void __init
847 musycc_init_port (mpi_t * pi)
848 {
849 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
850
851 pi->regram->grcd =
852 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
853 MUSYCC_GRCD_TX_ENABLE |
854 MUSYCC_GRCD_SF_ALIGN |
855 MUSYCC_GRCD_SUBCHAN_DISABLE |
856 MUSYCC_GRCD_OOFMP_DISABLE |
857 MUSYCC_GRCD_COFAIRQ_DISABLE |
858 MUSYCC_GRCD_MC_ENABLE |
859 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
860
861 pi->regram->pcd =
862 __constant_cpu_to_le32 (MUSYCC_PCD_E1X4_MODE |
863 MUSYCC_PCD_TXDATA_RISING |
864 MUSYCC_PCD_TX_DRIVEN);
865
866 /* Message length descriptor */
867 pi->regram->mld = __constant_cpu_to_le32 (max_mru | (max_mru << 16));
868 FLUSH_MEM_WRITE ();
869
870 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
871 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
872
873 musycc_init_mdt (pi);
874
875 musycc_update_timeslots (pi);
876 }
877 #endif
878
879
880 status_t __init
881 musycc_init (ci_t * ci)
882 {
883 char *regaddr; /* temp for address boundary calculations */
884 int i, gchan;
885
886 OS_sem_init (&ci->sem_wdbusy, SEM_AVAILABLE); /* watchdog exclusion */
887
888 /*
889 * Per MUSYCC manual, Section 6.3.4 - "The host must allocate a dword
890 * aligned memory segment for interrupt queue pointers."
891 */
892
893 #define INT_QUEUE_BOUNDARY 4
894
895 regaddr = OS_kmalloc ((INT_QUEUE_SIZE + 1) * sizeof (u_int32_t));
896 if (regaddr == 0)
897 return ENOMEM;
898 ci->iqd_p_saved = regaddr; /* save orig value for free's usage */
899 ci->iqd_p = (u_int32_t *) ((unsigned long) (regaddr + INT_QUEUE_BOUNDARY - 1) &
900 (~(INT_QUEUE_BOUNDARY - 1))); /* this calculates
901 * closest boundary */
902
903 for (i = 0; i < INT_QUEUE_SIZE; i++)
904 {
905 ci->iqd_p[i] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
906 }
907
908 for (i = 0; i < ci->max_port; i++)
909 {
910 mpi_t *pi = &ci->port[i];
911
912 /*
913 * Per MUSYCC manual, Section 6.3.2 - "The host must allocate a 2KB
914 * bound memory segment for Channel Group 0."
915 */
916
917 #define GROUP_BOUNDARY 0x800
918
919 regaddr = OS_kmalloc (sizeof (struct musycc_groupr) + GROUP_BOUNDARY);
920 if (regaddr == 0)
921 {
922 for (gchan = 0; gchan < i; gchan++)
923 {
924 pi = &ci->port[gchan];
925 OS_kfree (pi->reg);
926 pi->reg = 0;
927 }
928 return ENOMEM;
929 }
930 pi->regram_saved = regaddr; /* save orig value for free's usage */
931 pi->regram = (struct musycc_groupr *) ((unsigned long) (regaddr + GROUP_BOUNDARY - 1) &
932 (~(GROUP_BOUNDARY - 1))); /* this calculates
933 * closest boundary */
934 }
935
936 /* any board centric MUSYCC commands will use group ZERO as its "home" */
937 ci->regram = ci->port[0].regram;
938 musycc_serv_req (&ci->port[0], SR_CHIP_RESET);
939
940 pci_write_32 ((u_int32_t *) &ci->reg->gbp, OS_vtophys (ci->regram));
941 pci_flush_write (ci);
942 #ifdef CONFIG_SBE_PMCC4_NCOMM
943 ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC);
944 #else
945 /* standard driver POLLS for INTB via CPLD register */
946 ci->regram->__glcd = __constant_cpu_to_le32 (GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
947 #endif
948
949 ci->regram->__iqp = cpu_to_le32 (OS_vtophys (&ci->iqd_p[0]));
950 ci->regram->__iql = __constant_cpu_to_le32 (INT_QUEUE_SIZE - 1);
951 pci_write_32 ((u_int32_t *) &ci->reg->dacbp, 0);
952 FLUSH_MEM_WRITE ();
953
954 ci->state = C_RUNNING; /* mark as full interrupt processing
955 * available */
956
957 musycc_serv_req (&ci->port[0], SR_GLOBAL_INIT); /* FIRST INTERRUPT ! */
958
959 /* sanity check settable parameters */
960
961 if (max_mru > 0xffe)
962 {
963 pr_warning("Maximum allowed MRU exceeded, resetting %d to %d.\n",
964 max_mru, 0xffe);
965 max_mru = 0xffe;
966 }
967 if (max_mtu > 0xffe)
968 {
969 pr_warning("Maximum allowed MTU exceeded, resetting %d to %d.\n",
970 max_mtu, 0xffe);
971 max_mtu = 0xffe;
972 }
973 #ifdef SBE_WAN256T3_ENABLE
974 for (i = 0; i < MUSYCC_NPORTS; i++)
975 musycc_init_port (&ci->port[i]);
976 #endif
977
978 return SBE_DRVR_SUCCESS; /* no error */
979 }
980
981
982 void
983 musycc_bh_tx_eom (mpi_t * pi, int gchan)
984 {
985 mch_t *ch;
986 struct mdesc *md;
987
988 #if 0
989 #ifndef SBE_ISR_INLINE
990 unsigned long flags;
991
992 #endif
993 #endif
994 volatile u_int32_t status;
995
996 ch = pi->chan[gchan];
997 if (ch == 0 || ch->state != UP)
998 {
999 if (log_level >= LOG_ERROR)
1000 pr_info("%s: intr: xmit EOM on uninitialized channel %d\n",
1001 pi->up->devname, gchan);
1002 }
1003 if (ch == 0 || ch->mdt == 0)
1004 return; /* note: mdt==0 implies a malloc()
1005 * failure w/in chan_up() routine */
1006
1007 #if 0
1008 #ifdef SBE_ISR_INLINE
1009 spin_lock_irq (&ch->ch_txlock);
1010 #else
1011 spin_lock_irqsave (&ch->ch_txlock, flags);
1012 #endif
1013 #endif
1014 do
1015 {
1016 FLUSH_MEM_READ ();
1017 md = ch->txd_irq_srv;
1018 status = le32_to_cpu (md->status);
1019
1020 /*
1021 * Note: Per MUSYCC Ref 6.4.9, the host does not poll a host-owned
1022 * Transmit Buffer Descriptor during Transparent Mode.
1023 */
1024 if (status & MUSYCC_TX_OWNED)
1025 {
1026 int readCount, loopCount;
1027
1028 /***********************************************************/
1029 /* HW Bug Fix */
1030 /* ---------- */
1031 /* Under certain PCI Bus loading conditions, the data */
1032 /* associated with an update of Shared Memory is delayed */
1033 /* relative to its PCI Interrupt. This is caught when */
1034 /* the host determines it does not yet OWN the descriptor. */
1035 /***********************************************************/
1036
1037 readCount = 0;
1038 while (status & MUSYCC_TX_OWNED)
1039 {
1040 for (loopCount = 0; loopCount < 0x30; loopCount++)
1041 OS_uwait_dummy (); /* use call to avoid optimization
1042 * removal of dummy delay */
1043 FLUSH_MEM_READ ();
1044 status = le32_to_cpu (md->status);
1045 if (readCount++ > 40)
1046 break; /* don't wait any longer */
1047 }
1048 if (status & MUSYCC_TX_OWNED)
1049 {
1050 if (log_level >= LOG_MONITOR)
1051 {
1052 pr_info("%s: Port %d Chan %2d - unexpected TX msg ownership intr (md %p sts %x)\n",
1053 pi->up->devname, pi->portnum, ch->channum,
1054 md, status);
1055 pr_info("++ User 0x%p IRQ_SRV 0x%p USR_ADD 0x%p QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1056 ch->user, ch->txd_irq_srv, ch->txd_usr_add,
1057 sd_queue_stopped (ch->user),
1058 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
1059 musycc_dump_txbuffer_ring (ch, 0);
1060 }
1061 break; /* Not our mdesc, done */
1062 } else
1063 {
1064 if (log_level >= LOG_MONITOR)
1065 pr_info("%s: Port %d Chan %2d - recovered TX msg ownership [%d] (md %p sts %x)\n",
1066 pi->up->devname, pi->portnum, ch->channum, readCount, md, status);
1067 }
1068 }
1069 ch->txd_irq_srv = md->snext;
1070
1071 md->data = 0;
1072 if (md->mem_token != 0)
1073 {
1074 /* upcount channel */
1075 atomic_sub (OS_mem_token_tlen (md->mem_token), &ch->tx_pending);
1076 /* upcount card */
1077 atomic_sub (OS_mem_token_tlen (md->mem_token), &pi->up->tx_pending);
1078 #ifdef SBE_WAN256T3_ENABLE
1079 if (!atomic_read (&pi->up->tx_pending))
1080 wan256t3_led (pi->up, LED_TX, 0);
1081 #endif
1082
1083 #ifdef CONFIG_SBE_WAN256T3_NCOMM
1084 /* callback that our packet was sent */
1085 {
1086 int hdlcnum = (pi->portnum * 32 + gchan);
1087
1088 if (hdlcnum >= 228)
1089 {
1090 if (nciProcess_TX_complete)
1091 (*nciProcess_TX_complete) (hdlcnum,
1092 getuserbychan (gchan));
1093 }
1094 }
1095 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
1096
1097 OS_mem_token_free_irq (md->mem_token);
1098 md->mem_token = 0;
1099 }
1100 md->status = 0;
1101 #ifdef RLD_TXFULL_DEBUG
1102 if (log_level >= LOG_MONITOR2)
1103 pr_info("~~ tx_eom: tx_full %x txd_free %d -> %d\n",
1104 ch->tx_full, ch->txd_free, ch->txd_free + 1);
1105 #endif
1106 ++ch->txd_free;
1107 FLUSH_MEM_WRITE ();
1108
1109 if ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && (status & EOBIRQ_ENABLE))
1110 {
1111 if (log_level >= LOG_MONITOR)
1112 pr_info("%s: Mode (%x) incorrect EOB status (%x)\n",
1113 pi->up->devname, ch->p.chan_mode, status);
1114 if ((status & EOMIRQ_ENABLE) == 0)
1115 break;
1116 }
1117 }
1118 while ((ch->p.chan_mode != CFG_CH_PROTO_TRANS) && ((status & EOMIRQ_ENABLE) == 0));
1119 /*
1120 * NOTE: (The above 'while' is coupled w/ previous 'do', way above.) Each
1121 * Transparent data buffer has the EOB bit, and NOT the EOM bit, set and
1122 * will furthermore have a separate IQD associated with each messages
1123 * buffer.
1124 */
1125
1126 FLUSH_MEM_READ ();
1127 /*
1128 * Smooth flow control hysterisis by maintaining task stoppage until half
1129 * the available write buffers are available.
1130 */
1131 if (ch->tx_full && (ch->txd_free >= (ch->txd_num / 2)))
1132 {
1133 /*
1134 * Then, only releave task stoppage if we actually have enough
1135 * buffers to service the last requested packet. It may require MORE
1136 * than half the available!
1137 */
1138 if (ch->txd_free >= ch->txd_required)
1139 {
1140
1141 #ifdef RLD_TXFULL_DEBUG
1142 if (log_level >= LOG_MONITOR2)
1143 pr_info("tx_eom[%d]: enable xmit tx_full no more, txd_free %d txd_num/2 %d\n",
1144 ch->channum,
1145 ch->txd_free, ch->txd_num / 2);
1146 #endif
1147 ch->tx_full = 0;
1148 ch->txd_required = 0;
1149 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1150 * channel */
1151 }
1152 }
1153 #ifdef RLD_TXFULL_DEBUG
1154 else if (ch->tx_full)
1155 {
1156 if (log_level >= LOG_MONITOR2)
1157 pr_info("tx_eom[%d]: bypass TX enable though room available? (txd_free %d txd_num/2 %d)\n",
1158 ch->channum,
1159 ch->txd_free, ch->txd_num / 2);
1160 }
1161 #endif
1162
1163 FLUSH_MEM_WRITE ();
1164 #if 0
1165 #ifdef SBE_ISR_INLINE
1166 spin_unlock_irq (&ch->ch_txlock);
1167 #else
1168 spin_unlock_irqrestore (&ch->ch_txlock, flags);
1169 #endif
1170 #endif
1171 }
1172
1173
1174 STATIC void
1175 musycc_bh_rx_eom (mpi_t * pi, int gchan)
1176 {
1177 mch_t *ch;
1178 void *m, *m2;
1179 struct mdesc *md;
1180 volatile u_int32_t status;
1181 u_int32_t error;
1182
1183 ch = pi->chan[gchan];
1184 if (ch == 0 || ch->state != UP)
1185 {
1186 if (log_level > LOG_ERROR)
1187 pr_info("%s: intr: receive EOM on uninitialized channel %d\n",
1188 pi->up->devname, gchan);
1189 return;
1190 }
1191 if (ch->mdr == 0)
1192 return; /* can this happen ? */
1193
1194 for (;;)
1195 {
1196 FLUSH_MEM_READ ();
1197 md = &ch->mdr[ch->rxix_irq_srv];
1198 status = le32_to_cpu (md->status);
1199 if (!(status & HOST_RX_OWNED))
1200 break; /* Not our mdesc, done */
1201 m = md->mem_token;
1202 error = (status >> 16) & 0xf;
1203 if (error == 0)
1204 {
1205 #ifdef CONFIG_SBE_WAN256T3_NCOMM
1206 int hdlcnum = (pi->portnum * 32 + gchan);
1207
1208 /*
1209 * if the packet number belongs to NCOMM, then send it to the TMS
1210 * driver
1211 */
1212 if (hdlcnum >= 228)
1213 {
1214 if (nciProcess_RX_packet)
1215 (*nciProcess_RX_packet) (hdlcnum, status & 0x3fff, m, ch->user);
1216 } else
1217 #endif /*** CONFIG_SBE_WAN256T3_NCOMM ***/
1218
1219 {
1220 if ((m2 = OS_mem_token_alloc (max_mru)))
1221 {
1222 /* substitute the mbuf+cluster */
1223 md->mem_token = m2;
1224 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
1225
1226 /* pass the received mbuf upward */
1227 sd_recv_consume (m, status & LENGTH_MASK, ch->user);
1228 ch->s.rx_packets++;
1229 ch->s.rx_bytes += status & LENGTH_MASK;
1230 } else
1231 {
1232 ch->s.rx_dropped++;
1233 }
1234 }
1235 } else if (error == ERR_FCS)
1236 {
1237 ch->s.rx_crc_errors++;
1238 } else if (error == ERR_ALIGN)
1239 {
1240 ch->s.rx_missed_errors++;
1241 } else if (error == ERR_ABT)
1242 {
1243 ch->s.rx_missed_errors++;
1244 } else if (error == ERR_LNG)
1245 {
1246 ch->s.rx_length_errors++;
1247 } else if (error == ERR_SHT)
1248 {
1249 ch->s.rx_length_errors++;
1250 }
1251 FLUSH_MEM_WRITE ();
1252 status = max_mru;
1253 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1254 status |= EOBIRQ_ENABLE;
1255 md->status = cpu_to_le32 (status);
1256
1257 /* Check next mdesc in the ring */
1258 if (++ch->rxix_irq_srv >= ch->rxd_num)
1259 ch->rxix_irq_srv = 0;
1260 FLUSH_MEM_WRITE ();
1261 }
1262 }
1263
1264
1265 irqreturn_t
1266 musycc_intr_th_handler (void *devp)
1267 {
1268 ci_t *ci = (ci_t *) devp;
1269 volatile u_int32_t status, currInt = 0;
1270 u_int32_t nextInt, intCnt;
1271
1272 /*
1273 * Hardware not available, potential interrupt hang. But since interrupt
1274 * might be shared, just return.
1275 */
1276 if (ci->state == C_INIT)
1277 {
1278 return IRQ_NONE;
1279 }
1280 /*
1281 * Marked as hardware available. Don't service interrupts, just clear the
1282 * event.
1283 */
1284
1285 if (ci->state == C_IDLE)
1286 {
1287 status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
1288
1289 /* clear the interrupt but process nothing else */
1290 pci_write_32 ((u_int32_t *) &ci->reg->isd, status);
1291 return IRQ_HANDLED;
1292 }
1293 FLUSH_PCI_READ ();
1294 FLUSH_MEM_READ ();
1295
1296 status = pci_read_32 ((u_int32_t *) &ci->reg->isd);
1297 nextInt = INTRPTS_NEXTINT (status);
1298 intCnt = INTRPTS_INTCNT (status);
1299 ci->intlog.drvr_intr_thcount++;
1300
1301 /*********************************************************/
1302 /* HW Bug Fix */
1303 /* ---------- */
1304 /* Under certain PCI Bus loading conditions, the */
1305 /* MUSYCC looses the data associated with an update */
1306 /* of its ISD and erroneously returns the immediately */
1307 /* preceding 'nextInt' value. However, the 'intCnt' */
1308 /* value appears to be correct. By not starting service */
1309 /* where the 'missing' 'nextInt' SHOULD point causes */
1310 /* the IQD not to be serviced - the 'not serviced' */
1311 /* entries then remain and continue to increase as more */
1312 /* incorrect ISD's are encountered. */
1313 /*********************************************************/
1314
1315 if (nextInt != INTRPTS_NEXTINT (ci->intlog.this_status_new))
1316 {
1317 if (log_level >= LOG_MONITOR)
1318 {
1319 pr_info("%s: note - updated ISD from %08x to %08x\n",
1320 ci->devname, status,
1321 (status & (~INTRPTS_NEXTINT_M)) | ci->intlog.this_status_new);
1322 }
1323 /*
1324 * Replace bogus status with software corrected value.
1325 *
1326 * It's not known whether, during this problem occurrence, if the
1327 * INTFULL bit is correctly reported or not.
1328 */
1329 status = (status & (~INTRPTS_NEXTINT_M)) | (ci->intlog.this_status_new);
1330 nextInt = INTRPTS_NEXTINT (status);
1331 }
1332 /**********************************************/
1333 /* Cn847x Bug Fix */
1334 /* -------------- */
1335 /* Fix for inability to write back same index */
1336 /* as read for a full interrupt queue. */
1337 /**********************************************/
1338
1339 if (intCnt == INT_QUEUE_SIZE)
1340 {
1341 currInt = ((intCnt - 1) + nextInt) & (INT_QUEUE_SIZE - 1);
1342 } else
1343 /************************************************/
1344 /* Interrupt Write Location Issues */
1345 /* ------------------------------- */
1346 /* When the interrupt status descriptor is */
1347 /* written, the interrupt line is de-asserted */
1348 /* by the Cn847x. In the case of MIPS */
1349 /* microprocessors, this must occur at the */
1350 /* beginning of the interrupt handler so that */
1351 /* the interrupt handle is not re-entered due */
1352 /* to interrupt dis-assertion latency. */
1353 /* In the case of all other processors, this */
1354 /* action should occur at the end of the */
1355 /* interrupt handler to avoid overwriting the */
1356 /* interrupt queue. */
1357 /************************************************/
1358
1359 if (intCnt)
1360 {
1361 currInt = (intCnt + nextInt) & (INT_QUEUE_SIZE - 1);
1362 } else
1363 {
1364 /*
1365 * NOTE: Servicing an interrupt whose ISD contains a count of ZERO
1366 * can be indicative of a Shared Interrupt chain. Our driver can be
1367 * called from the system's interrupt handler as a matter of the OS
1368 * walking the chain. As the chain is walked, the interrupt will
1369 * eventually be serviced by the correct driver/handler.
1370 */
1371 #if 0
1372 /* chained interrupt = not ours */
1373 pr_info(">> %s: intCnt NULL, sts %x, possibly a chained interrupt!\n",
1374 ci->devname, status);
1375 #endif
1376 return IRQ_NONE;
1377 }
1378
1379 ci->iqp_tailx = currInt;
1380
1381 currInt <<= INTRPTS_NEXTINT_S;
1382 ci->intlog.last_status_new = ci->intlog.this_status_new;
1383 ci->intlog.this_status_new = currInt;
1384
1385 if ((log_level >= LOG_WARN) && (status & INTRPTS_INTFULL_M))
1386 {
1387 pr_info("%s: Interrupt queue full condition occurred\n", ci->devname);
1388 }
1389 if (log_level >= LOG_DEBUG)
1390 pr_info("%s: interrupts pending, isd @ 0x%p: %x curr %d cnt %d NEXT %d\n",
1391 ci->devname, &ci->reg->isd,
1392 status, nextInt, intCnt, (intCnt + nextInt) & (INT_QUEUE_SIZE - 1));
1393
1394 FLUSH_MEM_WRITE ();
1395 #if defined(SBE_ISR_TASKLET)
1396 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1397 atomic_inc (&ci->bh_pending);
1398 tasklet_schedule (&ci->ci_musycc_isr_tasklet);
1399 #elif defined(SBE_ISR_IMMEDIATE)
1400 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1401 atomic_inc (&ci->bh_pending);
1402 queue_task (&ci->ci_musycc_isr_tq, &tq_immediate);
1403 mark_bh (IMMEDIATE_BH);
1404 #elif defined(SBE_ISR_INLINE)
1405 (void) musycc_intr_bh_tasklet (ci);
1406 pci_write_32 ((u_int32_t *) &ci->reg->isd, currInt);
1407 #endif
1408 return IRQ_HANDLED;
1409 }
1410
1411
1412 #if defined(SBE_ISR_IMMEDIATE)
1413 unsigned long
1414 #else
1415 void
1416 #endif
1417 musycc_intr_bh_tasklet (ci_t * ci)
1418 {
1419 mpi_t *pi;
1420 mch_t *ch;
1421 unsigned int intCnt;
1422 volatile u_int32_t currInt = 0;
1423 volatile unsigned int headx, tailx;
1424 int readCount, loopCount;
1425 int group, gchan, event, err, tx;
1426 u_int32_t badInt = INT_EMPTY_ENTRY;
1427 u_int32_t badInt2 = INT_EMPTY_ENTRY2;
1428
1429 /*
1430 * Hardware not available, potential interrupt hang. But since interrupt
1431 * might be shared, just return.
1432 */
1433 if ((drvr_state != SBE_DRVR_AVAILABLE) || (ci->state == C_INIT))
1434 {
1435 #if defined(SBE_ISR_IMMEDIATE)
1436 return 0L;
1437 #else
1438 return;
1439 #endif
1440 }
1441 #if defined(SBE_ISR_TASKLET) || defined(SBE_ISR_IMMEDIATE)
1442 if (drvr_state != SBE_DRVR_AVAILABLE)
1443 {
1444 #if defined(SBE_ISR_TASKLET)
1445 return;
1446 #elif defined(SBE_ISR_IMMEDIATE)
1447 return 0L;
1448 #endif
1449 }
1450 #elif defined(SBE_ISR_INLINE)
1451 /* no semaphore taken, no double checks */
1452 #endif
1453
1454 ci->intlog.drvr_intr_bhcount++;
1455 FLUSH_MEM_READ ();
1456 {
1457 unsigned int bh = atomic_read (&ci->bh_pending);
1458
1459 max_bh = max (bh, max_bh);
1460 }
1461 atomic_set (&ci->bh_pending, 0);/* if here, no longer pending */
1462 while ((headx = ci->iqp_headx) != (tailx = ci->iqp_tailx))
1463 {
1464 intCnt = (tailx >= headx) ? (tailx - headx) : (tailx - headx + INT_QUEUE_SIZE);
1465 currInt = le32_to_cpu (ci->iqd_p[headx]);
1466
1467 max_intcnt = max (intCnt, max_intcnt); /* RLD DEBUG */
1468
1469 /**************************************************/
1470 /* HW Bug Fix */
1471 /* ---------- */
1472 /* The following code checks for the condition */
1473 /* of interrupt assertion before interrupt */
1474 /* queue update. This is a problem on several */
1475 /* PCI-Local bridge chips found on some products. */
1476 /**************************************************/
1477
1478 readCount = 0;
1479 if ((currInt == badInt) || (currInt == badInt2))
1480 ci->intlog.drvr_int_failure++;
1481
1482 while ((currInt == badInt) || (currInt == badInt2))
1483 {
1484 for (loopCount = 0; loopCount < 0x30; loopCount++)
1485 OS_uwait_dummy (); /* use call to avoid optimization removal
1486 * of dummy delay */
1487 FLUSH_MEM_READ ();
1488 currInt = le32_to_cpu (ci->iqd_p[headx]);
1489 if (readCount++ > 20)
1490 break;
1491 }
1492
1493 if ((currInt == badInt) || (currInt == badInt2)) /* catch failure of Bug
1494 * Fix checking */
1495 {
1496 if (log_level >= LOG_WARN)
1497 pr_info("%s: Illegal Interrupt Detected @ 0x%p, mod %d.)\n",
1498 ci->devname, &ci->iqd_p[headx], headx);
1499
1500 /*
1501 * If the descriptor has not recovered, then leaving the EMPTY
1502 * entry set will not signal to the MUSYCC that this descriptor
1503 * has been serviced. The Interrupt Queue can then start loosing
1504 * available descriptors and MUSYCC eventually encounters and
1505 * reports the INTFULL condition. Per manual, changing any bit
1506 * marks descriptor as available, thus the use of different
1507 * EMPTY_ENTRY values.
1508 */
1509
1510 if (currInt == badInt)
1511 {
1512 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY2);
1513 } else
1514 {
1515 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
1516 }
1517 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1518 FLUSH_MEM_WRITE ();
1519 FLUSH_MEM_READ ();
1520 continue;
1521 }
1522 group = INTRPT_GRP (currInt);
1523 gchan = INTRPT_CH (currInt);
1524 event = INTRPT_EVENT (currInt);
1525 err = INTRPT_ERROR (currInt);
1526 tx = currInt & INTRPT_DIR_M;
1527
1528 ci->iqd_p[headx] = __constant_cpu_to_le32 (INT_EMPTY_ENTRY);
1529 FLUSH_MEM_WRITE ();
1530
1531 if (log_level >= LOG_DEBUG)
1532 {
1533 if (err != 0)
1534 pr_info(" %08x -> err: %2d,", currInt, err);
1535
1536 pr_info("+ interrupt event: %d, grp: %d, chan: %2d, side: %cX\n",
1537 event, group, gchan, tx ? 'T' : 'R');
1538 }
1539 pi = &ci->port[group]; /* notice that here we assume 1-1 group -
1540 * port mapping */
1541 ch = pi->chan[gchan];
1542 switch (event)
1543 {
1544 case EVE_SACK: /* Service Request Acknowledge */
1545 if (log_level >= LOG_DEBUG)
1546 {
1547 volatile u_int32_t r;
1548
1549 r = pci_read_32 ((u_int32_t *) &pi->reg->srd);
1550 pr_info("- SACK cmd: %08x (hdw= %08x)\n", pi->sr_last, r);
1551 }
1552 SD_SEM_GIVE (&pi->sr_sem_wait); /* wake up waiting process */
1553 break;
1554 case EVE_CHABT: /* Change To Abort Code (0x7e -> 0xff) */
1555 case EVE_CHIC: /* Change To Idle Code (0xff -> 0x7e) */
1556 break;
1557 case EVE_EOM: /* End Of Message */
1558 case EVE_EOB: /* End Of Buffer (Transparent mode) */
1559 if (tx)
1560 {
1561 musycc_bh_tx_eom (pi, gchan);
1562 } else
1563 {
1564 musycc_bh_rx_eom (pi, gchan);
1565 }
1566 #if 0
1567 break;
1568 #else
1569 /*
1570 * MUSYCC Interrupt Descriptor section states that EOB and EOM
1571 * can be combined with the NONE error (as well as others). So
1572 * drop thru to catch this...
1573 */
1574 #endif
1575 case EVE_NONE:
1576 if (err == ERR_SHT)
1577 {
1578 ch->s.rx_length_errors++;
1579 }
1580 break;
1581 default:
1582 if (log_level >= LOG_WARN)
1583 pr_info("%s: unexpected interrupt event: %d, iqd[%d]: %08x, port: %d\n", ci->devname,
1584 event, headx, currInt, group);
1585 break;
1586 } /* switch on event */
1587
1588
1589 /*
1590 * Per MUSYCC Manual, Section 6.4.8.3 [Transmit Errors], TX errors
1591 * are service-affecting and require action to resume normal
1592 * bit-level processing.
1593 */
1594
1595 switch (err)
1596 {
1597 case ERR_ONR:
1598 /*
1599 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors], this
1600 * error requires Transmit channel reactivation.
1601 *
1602 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], this error
1603 * requires Receive channel reactivation.
1604 */
1605 if (tx)
1606 {
1607
1608 /*
1609 * TX ONR Error only occurs when channel is configured for
1610 * Transparent Mode. However, this code will catch and
1611 * re-activate on ANY TX ONR error.
1612 */
1613
1614 /*
1615 * Set flag to re-enable on any next transmit attempt.
1616 */
1617 ch->ch_start_tx = CH_START_TX_ONR;
1618
1619 {
1620 #ifdef RLD_TRANS_DEBUG
1621 if (1 || log_level >= LOG_MONITOR)
1622 #else
1623 if (log_level >= LOG_MONITOR)
1624 #endif
1625 {
1626 pr_info("%s: TX buffer underflow [ONR] on channel %d, mode %x QStopped %x free %d\n",
1627 ci->devname, ch->channum, ch->p.chan_mode, sd_queue_stopped (ch->user), ch->txd_free);
1628 #ifdef RLD_DEBUG
1629 if (ch->p.chan_mode == 2) /* problem = ONR on HDLC
1630 * mode */
1631 {
1632 pr_info("++ Failed Last %x Next %x QStopped %x, start_tx %x tx_full %d txd_free %d mode %x\n",
1633 (u_int32_t) ch->txd_irq_srv, (u_int32_t) ch->txd_usr_add,
1634 sd_queue_stopped (ch->user),
1635 ch->ch_start_tx, ch->tx_full, ch->txd_free, ch->p.chan_mode);
1636 musycc_dump_txbuffer_ring (ch, 0);
1637 }
1638 #endif
1639 }
1640 }
1641 } else /* RX buffer overrun */
1642 {
1643 /*
1644 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors],
1645 * channel recovery for this RX ONR error IS required. It is
1646 * also suggested to increase the number of receive buffers
1647 * for this channel. Receive channel reactivation IS
1648 * required, and data has been lost.
1649 */
1650 ch->s.rx_over_errors++;
1651 ch->ch_start_rx = CH_START_RX_ONR;
1652
1653 if (log_level >= LOG_WARN)
1654 {
1655 pr_info("%s: RX buffer overflow [ONR] on channel %d, mode %x\n",
1656 ci->devname, ch->channum, ch->p.chan_mode);
1657 //musycc_dump_rxbuffer_ring (ch, 0); /* RLD DEBUG */
1658 }
1659 }
1660 musycc_chan_restart (ch);
1661 break;
1662 case ERR_BUF:
1663 if (tx)
1664 {
1665 ch->s.tx_fifo_errors++;
1666 ch->ch_start_tx = CH_START_TX_BUF;
1667 /*
1668 * Per MUSYCC manual, Section 6.4.8.3 [Transmit Errors],
1669 * this BUFF error requires Transmit channel reactivation.
1670 */
1671 if (log_level >= LOG_MONITOR)
1672 pr_info("%s: TX buffer underrun [BUFF] on channel %d, mode %x\n",
1673 ci->devname, ch->channum, ch->p.chan_mode);
1674 } else /* RX buffer overrun */
1675 {
1676 ch->s.rx_over_errors++;
1677 /*
1678 * Per MUSYCC manual, Section 6.4.8.4 [Receive Errors], HDLC
1679 * mode requires NO recovery for this RX BUFF error is
1680 * required. It is suggested to increase the FIFO buffer
1681 * space for this channel. Receive channel reactivation is
1682 * not required, but data has been lost.
1683 */
1684 if (log_level >= LOG_WARN)
1685 pr_info("%s: RX buffer overrun [BUFF] on channel %d, mode %x\n",
1686 ci->devname, ch->channum, ch->p.chan_mode);
1687 /*
1688 * Per MUSYCC manual, Section 6.4.9.4 [Receive Errors],
1689 * Transparent mode DOES require recovery for the RX BUFF
1690 * error. It is suggested to increase the FIFO buffer space
1691 * for this channel. Receive channel reactivation IS
1692 * required and data has been lost.
1693 */
1694 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1695 ch->ch_start_rx = CH_START_RX_BUF;
1696 }
1697
1698 if (tx || (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1699 musycc_chan_restart (ch);
1700 break;
1701 default:
1702 break;
1703 } /* switch on err */
1704
1705 /* Check for interrupt lost condition */
1706 if ((currInt & INTRPT_ILOST_M) && (log_level >= LOG_ERROR))
1707 {
1708 pr_info("%s: Interrupt queue overflow - ILOST asserted\n",
1709 ci->devname);
1710 }
1711 ci->iqp_headx = (headx + 1) & (INT_QUEUE_SIZE - 1); /* insure wrapness */
1712 FLUSH_MEM_WRITE ();
1713 FLUSH_MEM_READ ();
1714 } /* while */
1715 if ((log_level >= LOG_MONITOR2) && (ci->iqp_headx != ci->iqp_tailx))
1716 {
1717 int bh;
1718
1719 bh = atomic_read (&CI->bh_pending);
1720 pr_info("_bh_: late arrivals, head %d != tail %d, pending %d\n",
1721 ci->iqp_headx, ci->iqp_tailx, bh);
1722 }
1723 #if defined(SBE_ISR_IMMEDIATE)
1724 return 0L;
1725 #endif
1726 /* else, nothing returned */
1727 }
1728
1729 #if 0
1730 int __init
1731 musycc_new_chan (ci_t * ci, int channum, void *user)
1732 {
1733 mch_t *ch;
1734
1735 ch = ci->port[channum / MUSYCC_NCHANS].chan[channum % MUSYCC_NCHANS];
1736
1737 if (ch->state != UNASSIGNED)
1738 return EEXIST;
1739 /* NOTE: mch_t already cleared during OS_kmalloc() */
1740 ch->state = DOWN;
1741 ch->user = user;
1742 #if 0
1743 ch->status = 0;
1744 ch->p.status = 0;
1745 ch->p.intr_mask = 0;
1746 #endif
1747 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1748 ch->p.idlecode = CFG_CH_FLAG_7E;
1749 ch->p.pad_fill_count = 2;
1750 spin_lock_init (&ch->ch_rxlock);
1751 spin_lock_init (&ch->ch_txlock);
1752
1753 return 0;
1754 }
1755 #endif
1756
1757
1758 #ifdef SBE_PMCC4_ENABLE
1759 status_t
1760 musycc_chan_down (ci_t * dummy, int channum)
1761 {
1762 mpi_t *pi;
1763 mch_t *ch;
1764 int i, gchan;
1765
1766 if (!(ch = sd_find_chan (dummy, channum)))
1767 return EINVAL;
1768 pi = ch->up;
1769 gchan = ch->gchan;
1770
1771 /* Deactivate the channel */
1772 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
1773 ch->ch_start_rx = 0;
1774 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
1775 ch->ch_start_tx = 0;
1776
1777 if (ch->state == DOWN)
1778 return 0;
1779 ch->state = DOWN;
1780
1781 pi->regram->thp[gchan] = 0;
1782 pi->regram->tmp[gchan] = 0;
1783 pi->regram->rhp[gchan] = 0;
1784 pi->regram->rmp[gchan] = 0;
1785 FLUSH_MEM_WRITE ();
1786 for (i = 0; i < ch->txd_num; i++)
1787 {
1788 if (ch->mdt[i].mem_token != 0)
1789 OS_mem_token_free (ch->mdt[i].mem_token);
1790 }
1791
1792 for (i = 0; i < ch->rxd_num; i++)
1793 {
1794 if (ch->mdr[i].mem_token != 0)
1795 OS_mem_token_free (ch->mdr[i].mem_token);
1796 }
1797
1798 OS_kfree (ch->mdr);
1799 ch->mdr = 0;
1800 ch->rxd_num = 0;
1801 OS_kfree (ch->mdt);
1802 ch->mdt = 0;
1803 ch->txd_num = 0;
1804
1805 musycc_update_timeslots (pi);
1806 c4_fifo_free (pi, ch->gchan);
1807
1808 pi->openchans--;
1809 return 0;
1810 }
1811 #endif
1812
1813
1814 int
1815 musycc_del_chan (ci_t * ci, int channum)
1816 {
1817 mch_t *ch;
1818
1819 if ((channum < 0) || (channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS))) /* sanity chk param */
1820 return ECHRNG;
1821 if (!(ch = sd_find_chan (ci, channum)))
1822 return ENOENT;
1823 if (ch->state == UP)
1824 musycc_chan_down (ci, channum);
1825 ch->state = UNASSIGNED;
1826 return 0;
1827 }
1828
1829
1830 int
1831 musycc_del_chan_stats (ci_t * ci, int channum)
1832 {
1833 mch_t *ch;
1834
1835 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
1836 return ECHRNG;
1837 if (!(ch = sd_find_chan (ci, channum)))
1838 return ENOENT;
1839
1840 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1841 return 0;
1842 }
1843
1844
1845 int
1846 musycc_start_xmit (ci_t * ci, int channum, void *mem_token)
1847 {
1848 mch_t *ch;
1849 struct mdesc *md;
1850 void *m2;
1851 #if 0
1852 unsigned long flags;
1853 #endif
1854 int txd_need_cnt;
1855 u_int32_t len;
1856
1857 if (!(ch = sd_find_chan (ci, channum)))
1858 return ENOENT;
1859
1860 if (ci->state != C_RUNNING) /* full interrupt processing available */
1861 return EINVAL;
1862 if (ch->state != UP)
1863 return EINVAL;
1864
1865 if (!(ch->status & TX_ENABLED))
1866 return EROFS; /* how else to flag unwritable state ? */
1867
1868 #ifdef RLD_TRANS_DEBUGx
1869 if (1 || log_level >= LOG_MONITOR2)
1870 #else
1871 if (log_level >= LOG_MONITOR2)
1872 #endif
1873 {
1874 pr_info("++ start_xmt[%d]: state %x start %x full %d free %d required %d stopped %x\n",
1875 channum, ch->state, ch->ch_start_tx, ch->tx_full,
1876 ch->txd_free, ch->txd_required, sd_queue_stopped (ch->user));
1877 }
1878 /***********************************************/
1879 /** Determine total amount of data to be sent **/
1880 /***********************************************/
1881 m2 = mem_token;
1882 txd_need_cnt = 0;
1883 for (len = OS_mem_token_tlen (m2); len > 0;
1884 m2 = (void *) OS_mem_token_next (m2))
1885 {
1886 if (!OS_mem_token_len (m2))
1887 continue;
1888 txd_need_cnt++;
1889 len -= OS_mem_token_len (m2);
1890 }
1891
1892 if (txd_need_cnt == 0)
1893 {
1894 if (log_level >= LOG_MONITOR2)
1895 pr_info("%s channel %d: no TX data in User buffer\n", ci->devname, channum);
1896 OS_mem_token_free (mem_token);
1897 return 0; /* no data to send */
1898 }
1899 /*************************************************/
1900 /** Are there sufficient descriptors available? **/
1901 /*************************************************/
1902 if (txd_need_cnt > ch->txd_num) /* never enough descriptors for this
1903 * large a buffer */
1904 {
1905 if (log_level >= LOG_DEBUG)
1906 {
1907 pr_info("start_xmit: discarding buffer, insufficient descriptor cnt %d, need %d.\n",
1908 ch->txd_num, txd_need_cnt + 1);
1909 }
1910 ch->s.tx_dropped++;
1911 OS_mem_token_free (mem_token);
1912 return 0;
1913 }
1914 #if 0
1915 spin_lock_irqsave (&ch->ch_txlock, flags);
1916 #endif
1917 /************************************************************/
1918 /** flow control the line if not enough descriptors remain **/
1919 /************************************************************/
1920 if (txd_need_cnt > ch->txd_free)
1921 {
1922 if (log_level >= LOG_MONITOR2)
1923 {
1924 pr_info("start_xmit[%d]: EBUSY - need more descriptors, have %d of %d need %d\n",
1925 channum, ch->txd_free, ch->txd_num, txd_need_cnt);
1926 }
1927 ch->tx_full = 1;
1928 ch->txd_required = txd_need_cnt;
1929 sd_disable_xmit (ch->user);
1930 #if 0
1931 spin_unlock_irqrestore (&ch->ch_txlock, flags);
1932 #endif
1933 return EBUSY; /* tell user to try again later */
1934 }
1935 /**************************************************/
1936 /** Put the user data into MUSYCC data buffer(s) **/
1937 /**************************************************/
1938 m2 = mem_token;
1939 md = ch->txd_usr_add; /* get current available descriptor */
1940
1941 for (len = OS_mem_token_tlen (m2); len > 0; m2 = OS_mem_token_next (m2))
1942 {
1943 int u = OS_mem_token_len (m2);
1944
1945 if (!u)
1946 continue;
1947 len -= u;
1948
1949 /*
1950 * Enable following chunks, yet wait to enable the FIRST chunk until
1951 * after ALL subsequent chunks are setup.
1952 */
1953 if (md != ch->txd_usr_add) /* not first chunk */
1954 u |= MUSYCC_TX_OWNED; /* transfer ownership from HOST to MUSYCC */
1955
1956 if (len) /* not last chunk */
1957 u |= EOBIRQ_ENABLE;
1958 else if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1959 {
1960 /*
1961 * Per MUSYCC Ref 6.4.9 for Transparent Mode, the host must
1962 * always clear EOMIRQ_ENABLE in every Transmit Buffer Descriptor
1963 * (IE. don't set herein).
1964 */
1965 u |= EOBIRQ_ENABLE;
1966 } else
1967 u |= EOMIRQ_ENABLE; /* EOM, last HDLC chunk */
1968
1969
1970 /* last chunk in hdlc mode */
1971 u |= (ch->p.idlecode << IDLE_CODE);
1972 if (ch->p.pad_fill_count)
1973 {
1974 #if 0
1975 /* NOOP NOTE: u_int8_t cannot be > 0xFF */
1976 /* sanitize pad_fill_count for maximums allowed by hardware */
1977 if (ch->p.pad_fill_count > EXTRA_FLAGS_MASK)
1978 ch->p.pad_fill_count = EXTRA_FLAGS_MASK;
1979 #endif
1980 u |= (PADFILL_ENABLE | (ch->p.pad_fill_count << EXTRA_FLAGS));
1981 }
1982 md->mem_token = len ? 0 : mem_token; /* Fill in mds on last
1983 * segment, others set ZERO
1984 * so that entire token is
1985 * removed ONLY when ALL
1986 * segments have been
1987 * transmitted. */
1988
1989 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m2)));
1990 FLUSH_MEM_WRITE ();
1991 md->status = cpu_to_le32 (u);
1992 --ch->txd_free;
1993 md = md->snext;
1994 }
1995 FLUSH_MEM_WRITE ();
1996
1997
1998 /*
1999 * Now transfer ownership of first chunk from HOST to MUSYCC in order to
2000 * fire-off this XMIT.
2001 */
2002 ch->txd_usr_add->status |= __constant_cpu_to_le32 (MUSYCC_TX_OWNED);
2003 FLUSH_MEM_WRITE ();
2004 ch->txd_usr_add = md;
2005
2006 len = OS_mem_token_tlen (mem_token);
2007 atomic_add (len, &ch->tx_pending);
2008 atomic_add (len, &ci->tx_pending);
2009 ch->s.tx_packets++;
2010 ch->s.tx_bytes += len;
2011 #if 0
2012 spin_unlock_irqrestore (&ch->ch_txlock, flags); /* allow pending
2013 * interrupt to sneak
2014 * thru */
2015 #endif
2016
2017 /*
2018 * If an ONR was seen, then channel requires poking to restart
2019 * transmission.
2020 */
2021 if (ch->ch_start_tx)
2022 {
2023 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,41)
2024 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
2025 * board */
2026 if ((ch->ch_start_tx == CH_START_TX_ONR) && (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
2027 {
2028 /* ONR restart transmission from background loop */
2029 ci->wd_notify = WD_NOTIFY_ONR; /* enabled global watchdog
2030 * scan-thru */
2031 } else
2032 {
2033 /* start first transmission from background loop */
2034 ci->wd_notify = WD_NOTIFY_1TX; /* enabled global watchdog
2035 * scan-thru */
2036 }
2037 musycc_chan_restart (ch);
2038 SD_SEM_GIVE (&ci->sem_wdbusy);
2039 #else
2040 musycc_chan_restart (ch);
2041 #endif
2042 }
2043 #ifdef SBE_WAN256T3_ENABLE
2044 wan256t3_led (ci, LED_TX, LEDV_G);
2045 #endif
2046 return 0;
2047 }
2048
2049
2050 #if 0
2051 int
2052 musycc_set_chan (ci_t * ci, int channum, struct sbecom_chan_param * p)
2053 {
2054 mch_t *ch;
2055 int rok = 0;
2056 int n = 0;
2057
2058 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
2059 return ECHRNG;
2060 if (!(ch = sd_find_chan (ci, channum)))
2061 return ENOENT;
2062 if (ch->channum != p->channum)
2063 return EINVAL;
2064 if (sd_line_is_ok (ch->user))
2065 {
2066 rok = 1;
2067 sd_line_is_down (ch->user);
2068 }
2069 if (ch->state == UP && /* bring down in current configuration */
2070 (ch->p.status != p->status ||
2071 ch->p.chan_mode != p->chan_mode ||
2072 ch->p.intr_mask != p->intr_mask ||
2073 ch->txd_free < ch->txd_num))
2074 {
2075 if ((n = musycc_chan_down (ci, channum)))
2076 return n;
2077 if (ch->p.mode_56k != p->mode_56k)
2078 {
2079 ch->p = *p; /* copy in new parameters */
2080 musycc_update_timeslots (&ci->port[ch->channum / MUSYCC_NCHANS]);
2081 } else
2082 ch->p = *p; /* copy in new parameters */
2083 if ((n = musycc_chan_up (ci, channum)))
2084 return n;
2085 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
2086 * channel */
2087 } else
2088 {
2089 if (ch->p.mode_56k != p->mode_56k)
2090 {
2091 ch->p = *p; /* copy in new parameters */
2092 musycc_update_timeslots (&ci->port[ch->channum / MUSYCC_NCHANS]);
2093 } else
2094 ch->p = *p; /* copy in new parameters */
2095 }
2096
2097 if (rok)
2098 sd_line_is_up (ch->user);
2099 return 0;
2100 }
2101 #endif
2102
2103
2104 int
2105 musycc_get_chan (ci_t * ci, int channum, struct sbecom_chan_param * p)
2106 {
2107 mch_t *ch;
2108
2109 #if 0
2110 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
2111 return ECHRNG;
2112 #endif
2113 if (!(ch = sd_find_chan (ci, channum)))
2114 return ENOENT;
2115 *p = ch->p;
2116 return 0;
2117 }
2118
2119
2120 int
2121 musycc_get_chan_stats (ci_t * ci, int channum, struct sbecom_chan_stats * p)
2122 {
2123 mch_t *ch;
2124
2125 if (channum < 0 || channum >= (MUSYCC_NPORTS * MUSYCC_NCHANS)) /* sanity chk param */
2126 return ECHRNG;
2127 if (!(ch = sd_find_chan (ci, channum)))
2128 return ENOENT;
2129 *p = ch->s;
2130 p->tx_pending = atomic_read (&ch->tx_pending);
2131 return 0;
2132 }
2133
2134
2135
2136 #ifdef SBE_WAN256T3_ENABLE
2137 int
2138 musycc_chan_down (ci_t * ci, int channum)
2139 {
2140 mch_t *ch;
2141 mpi_t *pi;
2142 int i, gchan;
2143
2144 if (!(ch = sd_find_chan (ci, channum)))
2145 return EINVAL;
2146 pi = ch->up;
2147 gchan = ch->gchan;
2148
2149 /* Deactivate the channel */
2150 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_RX_DIRECTION | gchan);
2151 ch->ch_start_rx = 0;
2152 musycc_serv_req (pi, SR_CHANNEL_DEACTIVATE | SR_TX_DIRECTION | gchan);
2153 ch->ch_start_tx = 0;
2154
2155 if (ch->state == DOWN)
2156 return 0;
2157 ch->state = DOWN;
2158
2159 pi->regram->thp[gchan] = 0;
2160 pi->regram->tmp[gchan] = 0;
2161 pi->regram->rhp[gchan] = 0;
2162 pi->regram->rmp[gchan] = 0;
2163 FLUSH_MEM_WRITE ();
2164 for (i = 0; i < ch->txd_num; i++)
2165 {
2166 if (ch->mdt[i].mem_token != 0)
2167 OS_mem_token_free (ch->mdt[i].mem_token);
2168 }
2169
2170 for (i = 0; i < ch->rxd_num; i++)
2171 {
2172 if (ch->mdr[i].mem_token != 0)
2173 OS_mem_token_free (ch->mdr[i].mem_token);
2174 }
2175
2176 OS_kfree (ch->mdt);
2177 ch->mdt = 0;
2178 OS_kfree (ch->mdr);
2179 ch->mdr = 0;
2180
2181 return 0;
2182 }
2183 #endif
2184
2185 /*** End-of-File ***/
Linux with added FPC-III support