drivers/usb/musb/blackfin.c

   1 /*
   2  * MUSB OTG controller driver for Blackfin Processors
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/list.h>
  16 #include <linux/gpio.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/cacheflush.h>
  20
  21 #include "musb_core.h"
  22 #include "blackfin.h"
  23
  24 /*
  25  * Load an endpoint's FIFO
  26  */
  27 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  28 {
  29         void __iomem *fifo = hw_ep->fifo;
  30         void __iomem *epio = hw_ep->regs;
  31         u8 epnum = hw_ep->epnum;
  32
  33         prefetch((u8 *)src);
  34
  35         musb_writew(epio, MUSB_TXCOUNT, len);
  36
  37         DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  38                         hw_ep->epnum, fifo, len, src, epio);
  39
  40         dump_fifo_data(src, len);
  41
  42         if (!ANOMALY_05000380 && epnum != 0) {
  43                 u16 dma_reg;
  44
  45                 flush_dcache_range((unsigned long)src,
  46                         (unsigned long)(src + len));
  47
  48                 /* Setup DMA address register */
  49                 dma_reg = (u32)src;
  50                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  51                 SSYNC();
  52
  53                 dma_reg = (u32)src >> 16;
  54                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  55                 SSYNC();
  56
  57                 /* Setup DMA count register */
  58                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  59                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  60                 SSYNC();
  61
  62                 /* Enable the DMA */
  63                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  64                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  65                 SSYNC();
  66
  67                 /* Wait for compelete */
  68                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  69                         cpu_relax();
  70
  71                 /* acknowledge dma interrupt */
  72                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  73                 SSYNC();
  74
  75                 /* Reset DMA */
  76                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  77                 SSYNC();
  78         } else {
  79                 SSYNC();
  80
  81                 if (unlikely((unsigned long)src & 0x01))
  82                         outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
  83                 else
  84                         outsw((unsigned long)fifo, src, (len + 1) >> 1);
  85         }
  86 }
  87 /*
  88  * Unload an endpoint's FIFO
  89  */
  90 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  91 {
  92         void __iomem *fifo = hw_ep->fifo;
  93         u8 epnum = hw_ep->epnum;
  94
  95         if (ANOMALY_05000467 && epnum != 0) {
  96                 u16 dma_reg;
  97
  98                 invalidate_dcache_range((unsigned long)dst,
  99                         (unsigned long)(dst + len));
 100
 101                 /* Setup DMA address register */
 102                 dma_reg = (u32)dst;
 103                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
 104                 SSYNC();
 105
 106                 dma_reg = (u32)dst >> 16;
 107                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
 108                 SSYNC();
 109
 110                 /* Setup DMA count register */
 111                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
 112                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
 113                 SSYNC();
 114
 115                 /* Enable the DMA */
 116                 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
 117                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
 118                 SSYNC();
 119
 120                 /* Wait for compelete */
 121                 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
 122                         cpu_relax();
 123
 124                 /* acknowledge dma interrupt */
 125                 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
 126                 SSYNC();
 127
 128                 /* Reset DMA */
 129                 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
 130                 SSYNC();
 131         } else {
 132                 SSYNC();
 133                 /* Read the last byte of packet with odd size from address fifo + 4
 134                  * to trigger 1 byte access to EP0 FIFO.
 135                  */
 136                 if (len == 1)
 137                         *dst = (u8)inw((unsigned long)fifo + 4);
 138                 else {
 139                         if (unlikely((unsigned long)dst & 0x01))
 140                                 insw_8((unsigned long)fifo, dst, len >> 1);
 141                         else
 142                                 insw((unsigned long)fifo, dst, len >> 1);
 143
 144                         if (len & 0x01)
 145                                 *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
 146                 }
 147         }
 148         DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
 149                         'R', hw_ep->epnum, fifo, len, dst);
 150
 151         dump_fifo_data(dst, len);
 152 }
 153
 154 static irqreturn_t blackfin_interrupt(int irq, void *__hci)
 155 {
 156         unsigned long   flags;
 157         irqreturn_t     retval = IRQ_NONE;
 158         struct musb     *musb = __hci;
 159
 160         spin_lock_irqsave(&musb->lock, flags);
 161
 162         musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
 163         musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
 164         musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
 165
 166         if (musb->int_usb || musb->int_tx || musb->int_rx) {
 167                 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
 168                 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
 169                 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
 170                 retval = musb_interrupt(musb);
 171         }
 172
 173         spin_unlock_irqrestore(&musb->lock, flags);
 174
 175         /* REVISIT we sometimes get spurious IRQs on g_ep0
 176          * not clear why... fall in BF54x too.
 177          */
 178         if (retval != IRQ_HANDLED)
 179                 DBG(5, "spurious?\n");
 180
 181         return IRQ_HANDLED;
 182 }
 183
 184 static void musb_conn_timer_handler(unsigned long _musb)
 185 {
 186         struct musb *musb = (void *)_musb;
 187         unsigned long flags;
 188         u16 val;
 189
 190         spin_lock_irqsave(&musb->lock, flags);
 191         switch (musb->xceiv->state) {
 192         case OTG_STATE_A_IDLE:
 193         case OTG_STATE_A_WAIT_BCON:
 194                 /* Start a new session */
 195                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 196                 val |= MUSB_DEVCTL_SESSION;
 197                 musb_writew(musb->mregs, MUSB_DEVCTL, val);
 198
 199                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
 200                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
 201                         gpio_set_value(musb->config->gpio_vrsel, 1);
 202                         musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 203                 } else {
 204                         gpio_set_value(musb->config->gpio_vrsel, 0);
 205
 206                         /* Ignore VBUSERROR and SUSPEND IRQ */
 207                         val = musb_readb(musb->mregs, MUSB_INTRUSBE);
 208                         val &= ~MUSB_INTR_VBUSERROR;
 209                         musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
 210
 211                         val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
 212                         musb_writeb(musb->mregs, MUSB_INTRUSB, val);
 213
 214                         val = MUSB_POWER_HSENAB;
 215                         musb_writeb(musb->mregs, MUSB_POWER, val);
 216                 }
 217                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 218                 break;
 219
 220         default:
 221                 DBG(1, "%s state not handled\n", otg_state_string(musb));
 222                 break;
 223         }
 224         spin_unlock_irqrestore(&musb->lock, flags);
 225
 226         DBG(4, "state is %s\n", otg_state_string(musb));
 227 }
 228
 229 void musb_platform_enable(struct musb *musb)
 230 {
 231         if (is_host_enabled(musb)) {
 232                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 233                 musb->a_wait_bcon = TIMER_DELAY;
 234         }
 235 }
 236
 237 void musb_platform_disable(struct musb *musb)
 238 {
 239 }
 240
 241 static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
 242 {
 243 }
 244
 245 static void bfin_set_vbus(struct musb *musb, int is_on)
 246 {
 247         if (is_on)
 248                 gpio_set_value(musb->config->gpio_vrsel, 1);
 249         else
 250                 gpio_set_value(musb->config->gpio_vrsel, 0);
 251
 252         DBG(1, "VBUS %s, devctl %02x "
 253                 /* otg %3x conf %08x prcm %08x */ "\n",
 254                 otg_state_string(musb),
 255                 musb_readb(musb->mregs, MUSB_DEVCTL));
 256 }
 257
 258 static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
 259 {
 260         return 0;
 261 }
 262
 263 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 264 {
 265         if (is_host_enabled(musb))
 266                 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
 267 }
 268
 269 int musb_platform_get_vbus_status(struct musb *musb)
 270 {
 271         return 0;
 272 }
 273
 274 int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 275 {
 276         return -EIO;
 277 }
 278
 279 int __init musb_platform_init(struct musb *musb)
 280 {
 281
 282         /*
 283          * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
 284          * and OTG HOST modes, while rev 1.1 and greater require PE7 to
 285          * be low for DEVICE mode and high for HOST mode. We set it high
 286          * here because we are in host mode
 287          */
 288
 289         if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
 290                 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
 291                         musb->config->gpio_vrsel);
 292                 return -ENODEV;
 293         }
 294         gpio_direction_output(musb->config->gpio_vrsel, 0);
 295
 296         usb_nop_xceiv_register();
 297         musb->xceiv = otg_get_transceiver();
 298         if (!musb->xceiv)
 299                 return -ENODEV;
 300
 301         if (ANOMALY_05000346) {
 302                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
 303                 SSYNC();
 304         }
 305
 306         if (ANOMALY_05000347) {
 307                 bfin_write_USB_APHY_CNTRL(0x0);
 308                 SSYNC();
 309         }
 310
 311         /* Configure PLL oscillator register */
 312         bfin_write_USB_PLLOSC_CTRL(0x30a8);
 313         SSYNC();
 314
 315         bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
 316         SSYNC();
 317
 318         bfin_write_USB_EP_NI0_RXMAXP(64);
 319         SSYNC();
 320
 321         bfin_write_USB_EP_NI0_TXMAXP(64);
 322         SSYNC();
 323
 324         /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
 325         bfin_write_USB_GLOBINTR(0x7);
 326         SSYNC();
 327
 328         bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
 329                                 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
 330                                 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
 331                                 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
 332                                 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
 333         SSYNC();
 334
 335         if (is_host_enabled(musb)) {
 336                 musb->board_set_vbus = bfin_set_vbus;
 337                 setup_timer(&musb_conn_timer,
 338                         musb_conn_timer_handler, (unsigned long) musb);
 339         }
 340         if (is_peripheral_enabled(musb))
 341                 musb->xceiv->set_power = bfin_set_power;
 342
 343         musb->isr = blackfin_interrupt;
 344
 345         return 0;
 346 }
 347
 348 int musb_platform_suspend(struct musb *musb)
 349 {
 350         return 0;
 351 }
 352
 353 int musb_platform_resume(struct musb *musb)
 354 {
 355         return 0;
 356 }
 357
 358
 359 int musb_platform_exit(struct musb *musb)
 360 {
 361
 362         bfin_vbus_power(musb, 0 /*off*/, 1);
 363         gpio_free(musb->config->gpio_vrsel);
 364         musb_platform_suspend(musb);
 365
 366         return 0;
 367 }