?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Staging: strip: delete the driver
[linux/fpc-iii.git] / drivers / watchdog / iTCO_wdt.c
blob8da8860353748a6fcae9c72cc9e0fd2b1b4deb3c
1 /*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 313056-003, 313057-017: 82801H (ICH8)
30 * document number 316972-004, 316973-012: 82801I (ICH9)
31 * document number 319973-002, 319974-002: 82801J (ICH10)
32 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
33 * document number 320066-003, 320257-008: EP80597 (IICH)
34 * document number TBD : Cougar Point (CPT)
35 */
36
37 /*
38 * Includes, defines, variables, module parameters, ...
39 */
40
41 /* Module and version information */
42 #define DRV_NAME "iTCO_wdt"
43 #define DRV_VERSION "1.05"
44 #define PFX DRV_NAME ": "
45
46 /* Includes */
47 #include <linux/module.h> /* For module specific items */
48 #include <linux/moduleparam.h> /* For new moduleparam's */
49 #include <linux/types.h> /* For standard types (like size_t) */
50 #include <linux/errno.h> /* For the -ENODEV/... values */
51 #include <linux/kernel.h> /* For printk/panic/... */
52 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
53 (WATCHDOG_MINOR) */
54 #include <linux/watchdog.h> /* For the watchdog specific items */
55 #include <linux/init.h> /* For __init/__exit/... */
56 #include <linux/fs.h> /* For file operations */
57 #include <linux/platform_device.h> /* For platform_driver framework */
58 #include <linux/pci.h> /* For pci functions */
59 #include <linux/ioport.h> /* For io-port access */
60 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
61 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
62 #include <linux/io.h> /* For inb/outb/... */
63
64 #include "iTCO_vendor.h"
65
66 /* TCO related info */
67 enum iTCO_chipsets {
68 TCO_ICH = 0, /* ICH */
69 TCO_ICH0, /* ICH0 */
70 TCO_ICH2, /* ICH2 */
71 TCO_ICH2M, /* ICH2-M */
72 TCO_ICH3, /* ICH3-S */
73 TCO_ICH3M, /* ICH3-M */
74 TCO_ICH4, /* ICH4 */
75 TCO_ICH4M, /* ICH4-M */
76 TCO_CICH, /* C-ICH */
77 TCO_ICH5, /* ICH5 & ICH5R */
78 TCO_6300ESB, /* 6300ESB */
79 TCO_ICH6, /* ICH6 & ICH6R */
80 TCO_ICH6M, /* ICH6-M */
81 TCO_ICH6W, /* ICH6W & ICH6RW */
82 TCO_631XESB, /* 631xESB/632xESB */
83 TCO_ICH7, /* ICH7 & ICH7R */
84 TCO_ICH7DH, /* ICH7DH */
85 TCO_ICH7M, /* ICH7-M & ICH7-U */
86 TCO_ICH7MDH, /* ICH7-M DH */
87 TCO_ICH8, /* ICH8 & ICH8R */
88 TCO_ICH8DH, /* ICH8DH */
89 TCO_ICH8DO, /* ICH8DO */
90 TCO_ICH8M, /* ICH8M */
91 TCO_ICH8ME, /* ICH8M-E */
92 TCO_ICH9, /* ICH9 */
93 TCO_ICH9R, /* ICH9R */
94 TCO_ICH9DH, /* ICH9DH */
95 TCO_ICH9DO, /* ICH9DO */
96 TCO_ICH9M, /* ICH9M */
97 TCO_ICH9ME, /* ICH9M-E */
98 TCO_ICH10, /* ICH10 */
99 TCO_ICH10R, /* ICH10R */
100 TCO_ICH10D, /* ICH10D */
101 TCO_ICH10DO, /* ICH10DO */
102 TCO_PCH, /* PCH Desktop Full Featured */
103 TCO_PCHM, /* PCH Mobile Full Featured */
104 TCO_P55, /* P55 */
105 TCO_PM55, /* PM55 */
106 TCO_H55, /* H55 */
107 TCO_QM57, /* QM57 */
108 TCO_H57, /* H57 */
109 TCO_HM55, /* HM55 */
110 TCO_Q57, /* Q57 */
111 TCO_HM57, /* HM57 */
112 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
113 TCO_QS57, /* QS57 */
114 TCO_3400, /* 3400 */
115 TCO_3420, /* 3420 */
116 TCO_3450, /* 3450 */
117 TCO_EP80579, /* EP80579 */
118 TCO_CPT1, /* Cougar Point */
119 TCO_CPT2, /* Cougar Point Desktop */
120 TCO_CPT3, /* Cougar Point Mobile */
121 TCO_CPT4, /* Cougar Point */
122 TCO_CPT5, /* Cougar Point */
123 TCO_CPT6, /* Cougar Point */
124 TCO_CPT7, /* Cougar Point */
125 TCO_CPT8, /* Cougar Point */
126 TCO_CPT9, /* Cougar Point */
127 TCO_CPT10, /* Cougar Point */
128 TCO_CPT11, /* Cougar Point */
129 TCO_CPT12, /* Cougar Point */
130 TCO_CPT13, /* Cougar Point */
131 TCO_CPT14, /* Cougar Point */
132 TCO_CPT15, /* Cougar Point */
133 TCO_CPT16, /* Cougar Point */
134 TCO_CPT17, /* Cougar Point */
135 TCO_CPT18, /* Cougar Point */
136 TCO_CPT19, /* Cougar Point */
137 TCO_CPT20, /* Cougar Point */
138 TCO_CPT21, /* Cougar Point */
139 TCO_CPT22, /* Cougar Point */
140 TCO_CPT23, /* Cougar Point */
141 TCO_CPT24, /* Cougar Point */
142 TCO_CPT25, /* Cougar Point */
143 TCO_CPT26, /* Cougar Point */
144 TCO_CPT27, /* Cougar Point */
145 TCO_CPT28, /* Cougar Point */
146 TCO_CPT29, /* Cougar Point */
147 TCO_CPT30, /* Cougar Point */
148 TCO_CPT31, /* Cougar Point */
149 };
150
151 static struct {
152 char *name;
153 unsigned int iTCO_version;
154 } iTCO_chipset_info[] __devinitdata = {
155 {"ICH", 1},
156 {"ICH0", 1},
157 {"ICH2", 1},
158 {"ICH2-M", 1},
159 {"ICH3-S", 1},
160 {"ICH3-M", 1},
161 {"ICH4", 1},
162 {"ICH4-M", 1},
163 {"C-ICH", 1},
164 {"ICH5 or ICH5R", 1},
165 {"6300ESB", 1},
166 {"ICH6 or ICH6R", 2},
167 {"ICH6-M", 2},
168 {"ICH6W or ICH6RW", 2},
169 {"631xESB/632xESB", 2},
170 {"ICH7 or ICH7R", 2},
171 {"ICH7DH", 2},
172 {"ICH7-M or ICH7-U", 2},
173 {"ICH7-M DH", 2},
174 {"ICH8 or ICH8R", 2},
175 {"ICH8DH", 2},
176 {"ICH8DO", 2},
177 {"ICH8M", 2},
178 {"ICH8M-E", 2},
179 {"ICH9", 2},
180 {"ICH9R", 2},
181 {"ICH9DH", 2},
182 {"ICH9DO", 2},
183 {"ICH9M", 2},
184 {"ICH9M-E", 2},
185 {"ICH10", 2},
186 {"ICH10R", 2},
187 {"ICH10D", 2},
188 {"ICH10DO", 2},
189 {"PCH Desktop Full Featured", 2},
190 {"PCH Mobile Full Featured", 2},
191 {"P55", 2},
192 {"PM55", 2},
193 {"H55", 2},
194 {"QM57", 2},
195 {"H57", 2},
196 {"HM55", 2},
197 {"Q57", 2},
198 {"HM57", 2},
199 {"PCH Mobile SFF Full Featured", 2},
200 {"QS57", 2},
201 {"3400", 2},
202 {"3420", 2},
203 {"3450", 2},
204 {"EP80579", 2},
205 {"Cougar Point", 2},
206 {"Cougar Point", 2},
207 {"Cougar Point", 2},
208 {"Cougar Point", 2},
209 {"Cougar Point", 2},
210 {"Cougar Point", 2},
211 {"Cougar Point", 2},
212 {"Cougar Point", 2},
213 {"Cougar Point", 2},
214 {"Cougar Point", 2},
215 {"Cougar Point", 2},
216 {"Cougar Point", 2},
217 {"Cougar Point", 2},
218 {"Cougar Point", 2},
219 {"Cougar Point", 2},
220 {"Cougar Point", 2},
221 {"Cougar Point", 2},
222 {"Cougar Point", 2},
223 {"Cougar Point", 2},
224 {"Cougar Point", 2},
225 {"Cougar Point", 2},
226 {"Cougar Point", 2},
227 {"Cougar Point", 2},
228 {"Cougar Point", 2},
229 {"Cougar Point", 2},
230 {"Cougar Point", 2},
231 {"Cougar Point", 2},
232 {"Cougar Point", 2},
233 {"Cougar Point", 2},
234 {"Cougar Point", 2},
235 {"Cougar Point", 2},
236 {NULL, 0}
237 };
238
239 #define ITCO_PCI_DEVICE(dev, data) \
240 .vendor = PCI_VENDOR_ID_INTEL, \
241 .device = dev, \
242 .subvendor = PCI_ANY_ID, \
243 .subdevice = PCI_ANY_ID, \
244 .class = 0, \
245 .class_mask = 0, \
246 .driver_data = data
247
248 /*
249 * This data only exists for exporting the supported PCI ids
250 * via MODULE_DEVICE_TABLE. We do not actually register a
251 * pci_driver, because the I/O Controller Hub has also other
252 * functions that probably will be registered by other drivers.
253 */
254 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
255 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
256 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
257 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
258 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
259 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
260 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
261 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
262 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
263 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
264 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
265 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
266 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
267 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
268 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
269 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
270 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
271 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
272 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
273 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
274 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
275 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
276 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
277 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
278 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
279 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
280 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
281 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
282 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
283 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
284 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
285 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
286 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)},
287 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
288 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
289 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
290 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
291 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
292 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
293 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
294 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
295 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
296 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
297 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
298 { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)},
299 { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)},
300 { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)},
301 { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)},
302 { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)},
303 { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)},
304 { ITCO_PCI_DEVICE(0x3b00, TCO_PCH)},
305 { ITCO_PCI_DEVICE(0x3b01, TCO_PCHM)},
306 { ITCO_PCI_DEVICE(0x3b02, TCO_P55)},
307 { ITCO_PCI_DEVICE(0x3b03, TCO_PM55)},
308 { ITCO_PCI_DEVICE(0x3b06, TCO_H55)},
309 { ITCO_PCI_DEVICE(0x3b07, TCO_QM57)},
310 { ITCO_PCI_DEVICE(0x3b08, TCO_H57)},
311 { ITCO_PCI_DEVICE(0x3b09, TCO_HM55)},
312 { ITCO_PCI_DEVICE(0x3b0a, TCO_Q57)},
313 { ITCO_PCI_DEVICE(0x3b0b, TCO_HM57)},
314 { ITCO_PCI_DEVICE(0x3b0d, TCO_PCHMSFF)},
315 { ITCO_PCI_DEVICE(0x3b0f, TCO_QS57)},
316 { ITCO_PCI_DEVICE(0x3b12, TCO_3400)},
317 { ITCO_PCI_DEVICE(0x3b14, TCO_3420)},
318 { ITCO_PCI_DEVICE(0x3b16, TCO_3450)},
319 { ITCO_PCI_DEVICE(0x5031, TCO_EP80579)},
320 { ITCO_PCI_DEVICE(0x1c41, TCO_CPT1)},
321 { ITCO_PCI_DEVICE(0x1c42, TCO_CPT2)},
322 { ITCO_PCI_DEVICE(0x1c43, TCO_CPT3)},
323 { ITCO_PCI_DEVICE(0x1c44, TCO_CPT4)},
324 { ITCO_PCI_DEVICE(0x1c45, TCO_CPT5)},
325 { ITCO_PCI_DEVICE(0x1c46, TCO_CPT6)},
326 { ITCO_PCI_DEVICE(0x1c47, TCO_CPT7)},
327 { ITCO_PCI_DEVICE(0x1c48, TCO_CPT8)},
328 { ITCO_PCI_DEVICE(0x1c49, TCO_CPT9)},
329 { ITCO_PCI_DEVICE(0x1c4a, TCO_CPT10)},
330 { ITCO_PCI_DEVICE(0x1c4b, TCO_CPT11)},
331 { ITCO_PCI_DEVICE(0x1c4c, TCO_CPT12)},
332 { ITCO_PCI_DEVICE(0x1c4d, TCO_CPT13)},
333 { ITCO_PCI_DEVICE(0x1c4e, TCO_CPT14)},
334 { ITCO_PCI_DEVICE(0x1c4f, TCO_CPT15)},
335 { ITCO_PCI_DEVICE(0x1c50, TCO_CPT16)},
336 { ITCO_PCI_DEVICE(0x1c51, TCO_CPT17)},
337 { ITCO_PCI_DEVICE(0x1c52, TCO_CPT18)},
338 { ITCO_PCI_DEVICE(0x1c53, TCO_CPT19)},
339 { ITCO_PCI_DEVICE(0x1c54, TCO_CPT20)},
340 { ITCO_PCI_DEVICE(0x1c55, TCO_CPT21)},
341 { ITCO_PCI_DEVICE(0x1c56, TCO_CPT22)},
342 { ITCO_PCI_DEVICE(0x1c57, TCO_CPT23)},
343 { ITCO_PCI_DEVICE(0x1c58, TCO_CPT24)},
344 { ITCO_PCI_DEVICE(0x1c59, TCO_CPT25)},
345 { ITCO_PCI_DEVICE(0x1c5a, TCO_CPT26)},
346 { ITCO_PCI_DEVICE(0x1c5b, TCO_CPT27)},
347 { ITCO_PCI_DEVICE(0x1c5c, TCO_CPT28)},
348 { ITCO_PCI_DEVICE(0x1c5d, TCO_CPT29)},
349 { ITCO_PCI_DEVICE(0x1c5e, TCO_CPT30)},
350 { ITCO_PCI_DEVICE(0x1c5f, TCO_CPT31)},
351 { 0, }, /* End of list */
352 };
353 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
354
355 /* Address definitions for the TCO */
356 /* TCO base address */
357 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
358 /* SMI Control and Enable Register */
359 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
360
361 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
362 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
363 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
364 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
365 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
366 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
367 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
368 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
369 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
370
371 /* internal variables */
372 static unsigned long is_active;
373 static char expect_release;
374 static struct { /* this is private data for the iTCO_wdt device */
375 /* TCO version/generation */
376 unsigned int iTCO_version;
377 /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
378 unsigned long ACPIBASE;
379 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
380 unsigned long __iomem *gcs;
381 /* the lock for io operations */
382 spinlock_t io_lock;
383 /* the PCI-device */
384 struct pci_dev *pdev;
385 } iTCO_wdt_private;
386
387 /* the watchdog platform device */
388 static struct platform_device *iTCO_wdt_platform_device;
389
390 /* module parameters */
391 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
392 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
393 module_param(heartbeat, int, 0);
394 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. "
395 "(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default="
396 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
397
398 static int nowayout = WATCHDOG_NOWAYOUT;
399 module_param(nowayout, int, 0);
400 MODULE_PARM_DESC(nowayout,
401 "Watchdog cannot be stopped once started (default="
402 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
403
404 /*
405 * Some TCO specific functions
406 */
407
408 static inline unsigned int seconds_to_ticks(int seconds)
409 {
410 /* the internal timer is stored as ticks which decrement
411 * every 0.6 seconds */
412 return (seconds * 10) / 6;
413 }
414
415 static void iTCO_wdt_set_NO_REBOOT_bit(void)
416 {
417 u32 val32;
418
419 /* Set the NO_REBOOT bit: this disables reboots */
420 if (iTCO_wdt_private.iTCO_version == 2) {
421 val32 = readl(iTCO_wdt_private.gcs);
422 val32 |= 0x00000020;
423 writel(val32, iTCO_wdt_private.gcs);
424 } else if (iTCO_wdt_private.iTCO_version == 1) {
425 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
426 val32 |= 0x00000002;
427 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
428 }
429 }
430
431 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
432 {
433 int ret = 0;
434 u32 val32;
435
436 /* Unset the NO_REBOOT bit: this enables reboots */
437 if (iTCO_wdt_private.iTCO_version == 2) {
438 val32 = readl(iTCO_wdt_private.gcs);
439 val32 &= 0xffffffdf;
440 writel(val32, iTCO_wdt_private.gcs);
441
442 val32 = readl(iTCO_wdt_private.gcs);
443 if (val32 & 0x00000020)
444 ret = -EIO;
445 } else if (iTCO_wdt_private.iTCO_version == 1) {
446 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
447 val32 &= 0xfffffffd;
448 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
449
450 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
451 if (val32 & 0x00000002)
452 ret = -EIO;
453 }
454
455 return ret; /* returns: 0 = OK, -EIO = Error */
456 }
457
458 static int iTCO_wdt_start(void)
459 {
460 unsigned int val;
461
462 spin_lock(&iTCO_wdt_private.io_lock);
463
464 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
465
466 /* disable chipset's NO_REBOOT bit */
467 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
468 spin_unlock(&iTCO_wdt_private.io_lock);
469 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
470 "reboot disabled by hardware\n");
471 return -EIO;
472 }
473
474 /* Force the timer to its reload value by writing to the TCO_RLD
475 register */
476 if (iTCO_wdt_private.iTCO_version == 2)
477 outw(0x01, TCO_RLD);
478 else if (iTCO_wdt_private.iTCO_version == 1)
479 outb(0x01, TCO_RLD);
480
481 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
482 val = inw(TCO1_CNT);
483 val &= 0xf7ff;
484 outw(val, TCO1_CNT);
485 val = inw(TCO1_CNT);
486 spin_unlock(&iTCO_wdt_private.io_lock);
487
488 if (val & 0x0800)
489 return -1;
490 return 0;
491 }
492
493 static int iTCO_wdt_stop(void)
494 {
495 unsigned int val;
496
497 spin_lock(&iTCO_wdt_private.io_lock);
498
499 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
500
501 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
502 val = inw(TCO1_CNT);
503 val |= 0x0800;
504 outw(val, TCO1_CNT);
505 val = inw(TCO1_CNT);
506
507 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
508 iTCO_wdt_set_NO_REBOOT_bit();
509
510 spin_unlock(&iTCO_wdt_private.io_lock);
511
512 if ((val & 0x0800) == 0)
513 return -1;
514 return 0;
515 }
516
517 static int iTCO_wdt_keepalive(void)
518 {
519 spin_lock(&iTCO_wdt_private.io_lock);
520
521 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
522
523 /* Reload the timer by writing to the TCO Timer Counter register */
524 if (iTCO_wdt_private.iTCO_version == 2)
525 outw(0x01, TCO_RLD);
526 else if (iTCO_wdt_private.iTCO_version == 1)
527 outb(0x01, TCO_RLD);
528
529 spin_unlock(&iTCO_wdt_private.io_lock);
530 return 0;
531 }
532
533 static int iTCO_wdt_set_heartbeat(int t)
534 {
535 unsigned int val16;
536 unsigned char val8;
537 unsigned int tmrval;
538
539 tmrval = seconds_to_ticks(t);
540 /* from the specs: */
541 /* "Values of 0h-3h are ignored and should not be attempted" */
542 if (tmrval < 0x04)
543 return -EINVAL;
544 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
545 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
546 return -EINVAL;
547
548 iTCO_vendor_pre_set_heartbeat(tmrval);
549
550 /* Write new heartbeat to watchdog */
551 if (iTCO_wdt_private.iTCO_version == 2) {
552 spin_lock(&iTCO_wdt_private.io_lock);
553 val16 = inw(TCOv2_TMR);
554 val16 &= 0xfc00;
555 val16 |= tmrval;
556 outw(val16, TCOv2_TMR);
557 val16 = inw(TCOv2_TMR);
558 spin_unlock(&iTCO_wdt_private.io_lock);
559
560 if ((val16 & 0x3ff) != tmrval)
561 return -EINVAL;
562 } else if (iTCO_wdt_private.iTCO_version == 1) {
563 spin_lock(&iTCO_wdt_private.io_lock);
564 val8 = inb(TCOv1_TMR);
565 val8 &= 0xc0;
566 val8 |= (tmrval & 0xff);
567 outb(val8, TCOv1_TMR);
568 val8 = inb(TCOv1_TMR);
569 spin_unlock(&iTCO_wdt_private.io_lock);
570
571 if ((val8 & 0x3f) != tmrval)
572 return -EINVAL;
573 }
574
575 heartbeat = t;
576 return 0;
577 }
578
579 static int iTCO_wdt_get_timeleft(int *time_left)
580 {
581 unsigned int val16;
582 unsigned char val8;
583
584 /* read the TCO Timer */
585 if (iTCO_wdt_private.iTCO_version == 2) {
586 spin_lock(&iTCO_wdt_private.io_lock);
587 val16 = inw(TCO_RLD);
588 val16 &= 0x3ff;
589 spin_unlock(&iTCO_wdt_private.io_lock);
590
591 *time_left = (val16 * 6) / 10;
592 } else if (iTCO_wdt_private.iTCO_version == 1) {
593 spin_lock(&iTCO_wdt_private.io_lock);
594 val8 = inb(TCO_RLD);
595 val8 &= 0x3f;
596 spin_unlock(&iTCO_wdt_private.io_lock);
597
598 *time_left = (val8 * 6) / 10;
599 } else
600 return -EINVAL;
601 return 0;
602 }
603
604 /*
605 * /dev/watchdog handling
606 */
607
608 static int iTCO_wdt_open(struct inode *inode, struct file *file)
609 {
610 /* /dev/watchdog can only be opened once */
611 if (test_and_set_bit(0, &is_active))
612 return -EBUSY;
613
614 /*
615 * Reload and activate timer
616 */
617 iTCO_wdt_start();
618 return nonseekable_open(inode, file);
619 }
620
621 static int iTCO_wdt_release(struct inode *inode, struct file *file)
622 {
623 /*
624 * Shut off the timer.
625 */
626 if (expect_release == 42) {
627 iTCO_wdt_stop();
628 } else {
629 printk(KERN_CRIT PFX
630 "Unexpected close, not stopping watchdog!\n");
631 iTCO_wdt_keepalive();
632 }
633 clear_bit(0, &is_active);
634 expect_release = 0;
635 return 0;
636 }
637
638 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
639 size_t len, loff_t *ppos)
640 {
641 /* See if we got the magic character 'V' and reload the timer */
642 if (len) {
643 if (!nowayout) {
644 size_t i;
645
646 /* note: just in case someone wrote the magic
647 character five months ago... */
648 expect_release = 0;
649
650 /* scan to see whether or not we got the
651 magic character */
652 for (i = 0; i != len; i++) {
653 char c;
654 if (get_user(c, data + i))
655 return -EFAULT;
656 if (c == 'V')
657 expect_release = 42;
658 }
659 }
660
661 /* someone wrote to us, we should reload the timer */
662 iTCO_wdt_keepalive();
663 }
664 return len;
665 }
666
667 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
668 unsigned long arg)
669 {
670 int new_options, retval = -EINVAL;
671 int new_heartbeat;
672 void __user *argp = (void __user *)arg;
673 int __user *p = argp;
674 static const struct watchdog_info ident = {
675 .options = WDIOF_SETTIMEOUT |
676 WDIOF_KEEPALIVEPING |
677 WDIOF_MAGICCLOSE,
678 .firmware_version = 0,
679 .identity = DRV_NAME,
680 };
681
682 switch (cmd) {
683 case WDIOC_GETSUPPORT:
684 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
685 case WDIOC_GETSTATUS:
686 case WDIOC_GETBOOTSTATUS:
687 return put_user(0, p);
688
689 case WDIOC_SETOPTIONS:
690 {
691 if (get_user(new_options, p))
692 return -EFAULT;
693
694 if (new_options & WDIOS_DISABLECARD) {
695 iTCO_wdt_stop();
696 retval = 0;
697 }
698 if (new_options & WDIOS_ENABLECARD) {
699 iTCO_wdt_keepalive();
700 iTCO_wdt_start();
701 retval = 0;
702 }
703 return retval;
704 }
705 case WDIOC_KEEPALIVE:
706 iTCO_wdt_keepalive();
707 return 0;
708
709 case WDIOC_SETTIMEOUT:
710 {
711 if (get_user(new_heartbeat, p))
712 return -EFAULT;
713 if (iTCO_wdt_set_heartbeat(new_heartbeat))
714 return -EINVAL;
715 iTCO_wdt_keepalive();
716 /* Fall */
717 }
718 case WDIOC_GETTIMEOUT:
719 return put_user(heartbeat, p);
720 case WDIOC_GETTIMELEFT:
721 {
722 int time_left;
723 if (iTCO_wdt_get_timeleft(&time_left))
724 return -EINVAL;
725 return put_user(time_left, p);
726 }
727 default:
728 return -ENOTTY;
729 }
730 }
731
732 /*
733 * Kernel Interfaces
734 */
735
736 static const struct file_operations iTCO_wdt_fops = {
737 .owner = THIS_MODULE,
738 .llseek = no_llseek,
739 .write = iTCO_wdt_write,
740 .unlocked_ioctl = iTCO_wdt_ioctl,
741 .open = iTCO_wdt_open,
742 .release = iTCO_wdt_release,
743 };
744
745 static struct miscdevice iTCO_wdt_miscdev = {
746 .minor = WATCHDOG_MINOR,
747 .name = "watchdog",
748 .fops = &iTCO_wdt_fops,
749 };
750
751 /*
752 * Init & exit routines
753 */
754
755 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
756 const struct pci_device_id *ent, struct platform_device *dev)
757 {
758 int ret;
759 u32 base_address;
760 unsigned long RCBA;
761 unsigned long val32;
762
763 /*
764 * Find the ACPI/PM base I/O address which is the base
765 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
766 * ACPIBASE is bits [15:7] from 0x40-0x43
767 */
768 pci_read_config_dword(pdev, 0x40, &base_address);
769 base_address &= 0x0000ff80;
770 if (base_address == 0x00000000) {
771 /* Something's wrong here, ACPIBASE has to be set */
772 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
773 pci_dev_put(pdev);
774 return -ENODEV;
775 }
776 iTCO_wdt_private.iTCO_version =
777 iTCO_chipset_info[ent->driver_data].iTCO_version;
778 iTCO_wdt_private.ACPIBASE = base_address;
779 iTCO_wdt_private.pdev = pdev;
780
781 /* Get the Memory-Mapped GCS register, we need it for the
782 NO_REBOOT flag (TCO v2). To get access to it you have to
783 read RCBA from PCI Config space 0xf0 and use it as base.
784 GCS = RCBA + ICH6_GCS(0x3410). */
785 if (iTCO_wdt_private.iTCO_version == 2) {
786 pci_read_config_dword(pdev, 0xf0, &base_address);
787 if ((base_address & 1) == 0) {
788 printk(KERN_ERR PFX "RCBA is disabled by hardware\n");
789 ret = -ENODEV;
790 goto out;
791 }
792 RCBA = base_address & 0xffffc000;
793 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
794 }
795
796 /* Check chipset's NO_REBOOT bit */
797 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
798 printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, "
799 "platform may have disabled it\n");
800 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
801 goto out_unmap;
802 }
803
804 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
805 iTCO_wdt_set_NO_REBOOT_bit();
806
807 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
808 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
809 printk(KERN_ERR PFX
810 "I/O address 0x%04lx already in use\n", SMI_EN);
811 ret = -EIO;
812 goto out_unmap;
813 }
814 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
815 val32 = inl(SMI_EN);
816 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
817 outl(val32, SMI_EN);
818
819 /* The TCO I/O registers reside in a 32-byte range pointed to
820 by the TCOBASE value */
821 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
822 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
823 TCOBASE);
824 ret = -EIO;
825 goto unreg_smi_en;
826 }
827
828 printk(KERN_INFO PFX
829 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
830 iTCO_chipset_info[ent->driver_data].name,
831 iTCO_chipset_info[ent->driver_data].iTCO_version,
832 TCOBASE);
833
834 /* Clear out the (probably old) status */
835 outb(8, TCO1_STS); /* Clear the Time Out Status bit */
836 outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */
837 outb(4, TCO2_STS); /* Clear BOOT_STS bit */
838
839 /* Make sure the watchdog is not running */
840 iTCO_wdt_stop();
841
842 /* Check that the heartbeat value is within it's range;
843 if not reset to the default */
844 if (iTCO_wdt_set_heartbeat(heartbeat)) {
845 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
846 printk(KERN_INFO PFX
847 "heartbeat value must be 2 < heartbeat < 39 (TCO v1) "
848 "or 613 (TCO v2), using %d\n", heartbeat);
849 }
850
851 ret = misc_register(&iTCO_wdt_miscdev);
852 if (ret != 0) {
853 printk(KERN_ERR PFX
854 "cannot register miscdev on minor=%d (err=%d)\n",
855 WATCHDOG_MINOR, ret);
856 goto unreg_region;
857 }
858
859 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
860 heartbeat, nowayout);
861
862 return 0;
863
864 unreg_region:
865 release_region(TCOBASE, 0x20);
866 unreg_smi_en:
867 release_region(SMI_EN, 4);
868 out_unmap:
869 if (iTCO_wdt_private.iTCO_version == 2)
870 iounmap(iTCO_wdt_private.gcs);
871 out:
872 pci_dev_put(iTCO_wdt_private.pdev);
873 iTCO_wdt_private.ACPIBASE = 0;
874 return ret;
875 }
876
877 static void __devexit iTCO_wdt_cleanup(void)
878 {
879 /* Stop the timer before we leave */
880 if (!nowayout)
881 iTCO_wdt_stop();
882
883 /* Deregister */
884 misc_deregister(&iTCO_wdt_miscdev);
885 release_region(TCOBASE, 0x20);
886 release_region(SMI_EN, 4);
887 if (iTCO_wdt_private.iTCO_version == 2)
888 iounmap(iTCO_wdt_private.gcs);
889 pci_dev_put(iTCO_wdt_private.pdev);
890 iTCO_wdt_private.ACPIBASE = 0;
891 }
892
893 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
894 {
895 int ret = -ENODEV;
896 int found = 0;
897 struct pci_dev *pdev = NULL;
898 const struct pci_device_id *ent;
899
900 spin_lock_init(&iTCO_wdt_private.io_lock);
901
902 for_each_pci_dev(pdev) {
903 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
904 if (ent) {
905 found++;
906 ret = iTCO_wdt_init(pdev, ent, dev);
907 if (!ret)
908 break;
909 }
910 }
911
912 if (!found)
913 printk(KERN_INFO PFX "No card detected\n");
914
915 return ret;
916 }
917
918 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
919 {
920 if (iTCO_wdt_private.ACPIBASE)
921 iTCO_wdt_cleanup();
922
923 return 0;
924 }
925
926 static void iTCO_wdt_shutdown(struct platform_device *dev)
927 {
928 iTCO_wdt_stop();
929 }
930
931 #define iTCO_wdt_suspend NULL
932 #define iTCO_wdt_resume NULL
933
934 static struct platform_driver iTCO_wdt_driver = {
935 .probe = iTCO_wdt_probe,
936 .remove = __devexit_p(iTCO_wdt_remove),
937 .shutdown = iTCO_wdt_shutdown,
938 .suspend = iTCO_wdt_suspend,
939 .resume = iTCO_wdt_resume,
940 .driver = {
941 .owner = THIS_MODULE,
942 .name = DRV_NAME,
943 },
944 };
945
946 static int __init iTCO_wdt_init_module(void)
947 {
948 int err;
949
950 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
951 DRV_VERSION);
952
953 err = platform_driver_register(&iTCO_wdt_driver);
954 if (err)
955 return err;
956
957 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
958 -1, NULL, 0);
959 if (IS_ERR(iTCO_wdt_platform_device)) {
960 err = PTR_ERR(iTCO_wdt_platform_device);
961 goto unreg_platform_driver;
962 }
963
964 return 0;
965
966 unreg_platform_driver:
967 platform_driver_unregister(&iTCO_wdt_driver);
968 return err;
969 }
970
971 static void __exit iTCO_wdt_cleanup_module(void)
972 {
973 platform_device_unregister(iTCO_wdt_platform_device);
974 platform_driver_unregister(&iTCO_wdt_driver);
975 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
976 }
977
978 module_init(iTCO_wdt_init_module);
979 module_exit(iTCO_wdt_cleanup_module);
980
981 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
982 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
983 MODULE_VERSION(DRV_VERSION);
984 MODULE_LICENSE("GPL");
985 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
Linux with added FPC-III support