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platform/x86: intel-vbtn: Report switch events when event wakes device
[linux/fpc-iii.git] / arch / arm / common / sa1111.c
bloba2c878769eaf5a2c616117ff732b1df540778ac8
1 /*
2 * linux/arch/arm/common/sa1111.c
3 *
4 * SA1111 support
5 *
6 * Original code by John Dorsey
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This file contains all generic SA1111 support.
13 *
14 * All initialization functions provided here are intended to be called
15 * from machine specific code with proper arguments when required.
16 */
17 #include <linux/module.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/spinlock.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31
32 #include <mach/hardware.h>
33 #include <asm/mach/irq.h>
34 #include <asm/mach-types.h>
35 #include <asm/sizes.h>
36
37 #include <asm/hardware/sa1111.h>
38
39 /* SA1111 IRQs */
40 #define IRQ_GPAIN0 (0)
41 #define IRQ_GPAIN1 (1)
42 #define IRQ_GPAIN2 (2)
43 #define IRQ_GPAIN3 (3)
44 #define IRQ_GPBIN0 (4)
45 #define IRQ_GPBIN1 (5)
46 #define IRQ_GPBIN2 (6)
47 #define IRQ_GPBIN3 (7)
48 #define IRQ_GPBIN4 (8)
49 #define IRQ_GPBIN5 (9)
50 #define IRQ_GPCIN0 (10)
51 #define IRQ_GPCIN1 (11)
52 #define IRQ_GPCIN2 (12)
53 #define IRQ_GPCIN3 (13)
54 #define IRQ_GPCIN4 (14)
55 #define IRQ_GPCIN5 (15)
56 #define IRQ_GPCIN6 (16)
57 #define IRQ_GPCIN7 (17)
58 #define IRQ_MSTXINT (18)
59 #define IRQ_MSRXINT (19)
60 #define IRQ_MSSTOPERRINT (20)
61 #define IRQ_TPTXINT (21)
62 #define IRQ_TPRXINT (22)
63 #define IRQ_TPSTOPERRINT (23)
64 #define SSPXMTINT (24)
65 #define SSPRCVINT (25)
66 #define SSPROR (26)
67 #define AUDXMTDMADONEA (32)
68 #define AUDRCVDMADONEA (33)
69 #define AUDXMTDMADONEB (34)
70 #define AUDRCVDMADONEB (35)
71 #define AUDTFSR (36)
72 #define AUDRFSR (37)
73 #define AUDTUR (38)
74 #define AUDROR (39)
75 #define AUDDTS (40)
76 #define AUDRDD (41)
77 #define AUDSTO (42)
78 #define IRQ_USBPWR (43)
79 #define IRQ_HCIM (44)
80 #define IRQ_HCIBUFFACC (45)
81 #define IRQ_HCIRMTWKP (46)
82 #define IRQ_NHCIMFCIR (47)
83 #define IRQ_USB_PORT_RESUME (48)
84 #define IRQ_S0_READY_NINT (49)
85 #define IRQ_S1_READY_NINT (50)
86 #define IRQ_S0_CD_VALID (51)
87 #define IRQ_S1_CD_VALID (52)
88 #define IRQ_S0_BVD1_STSCHG (53)
89 #define IRQ_S1_BVD1_STSCHG (54)
90 #define SA1111_IRQ_NR (55)
91
92 extern void sa1110_mb_enable(void);
93 extern void sa1110_mb_disable(void);
94
95 /*
96 * We keep the following data for the overall SA1111. Note that the
97 * struct device and struct resource are "fake"; they should be supplied
98 * by the bus above us. However, in the interests of getting all SA1111
99 * drivers converted over to the device model, we provide this as an
100 * anchor point for all the other drivers.
101 */
102 struct sa1111 {
103 struct device *dev;
104 struct clk *clk;
105 unsigned long phys;
106 int irq;
107 int irq_base; /* base for cascaded on-chip IRQs */
108 spinlock_t lock;
109 void __iomem *base;
110 struct sa1111_platform_data *pdata;
111 struct irq_domain *irqdomain;
112 struct gpio_chip gc;
113 #ifdef CONFIG_PM
114 void *saved_state;
115 #endif
116 };
117
118 /*
119 * We _really_ need to eliminate this. Its only users
120 * are the PWM and DMA checking code.
121 */
122 static struct sa1111 *g_sa1111;
123
124 struct sa1111_dev_info {
125 unsigned long offset;
126 unsigned long skpcr_mask;
127 bool dma;
128 unsigned int devid;
129 unsigned int hwirq[6];
130 };
131
132 static struct sa1111_dev_info sa1111_devices[] = {
133 {
134 .offset = SA1111_USB,
135 .skpcr_mask = SKPCR_UCLKEN,
136 .dma = true,
137 .devid = SA1111_DEVID_USB,
138 .hwirq = {
139 IRQ_USBPWR,
140 IRQ_HCIM,
141 IRQ_HCIBUFFACC,
142 IRQ_HCIRMTWKP,
143 IRQ_NHCIMFCIR,
144 IRQ_USB_PORT_RESUME
145 },
146 },
147 {
148 .offset = 0x0600,
149 .skpcr_mask = SKPCR_I2SCLKEN | SKPCR_L3CLKEN,
150 .dma = true,
151 .devid = SA1111_DEVID_SAC,
152 .hwirq = {
153 AUDXMTDMADONEA,
154 AUDXMTDMADONEB,
155 AUDRCVDMADONEA,
156 AUDRCVDMADONEB
157 },
158 },
159 {
160 .offset = 0x0800,
161 .skpcr_mask = SKPCR_SCLKEN,
162 .devid = SA1111_DEVID_SSP,
163 },
164 {
165 .offset = SA1111_KBD,
166 .skpcr_mask = SKPCR_PTCLKEN,
167 .devid = SA1111_DEVID_PS2_KBD,
168 .hwirq = {
169 IRQ_TPRXINT,
170 IRQ_TPTXINT
171 },
172 },
173 {
174 .offset = SA1111_MSE,
175 .skpcr_mask = SKPCR_PMCLKEN,
176 .devid = SA1111_DEVID_PS2_MSE,
177 .hwirq = {
178 IRQ_MSRXINT,
179 IRQ_MSTXINT
180 },
181 },
182 {
183 .offset = 0x1800,
184 .skpcr_mask = 0,
185 .devid = SA1111_DEVID_PCMCIA,
186 .hwirq = {
187 IRQ_S0_READY_NINT,
188 IRQ_S0_CD_VALID,
189 IRQ_S0_BVD1_STSCHG,
190 IRQ_S1_READY_NINT,
191 IRQ_S1_CD_VALID,
192 IRQ_S1_BVD1_STSCHG,
193 },
194 },
195 };
196
197 static int sa1111_map_irq(struct sa1111 *sachip, irq_hw_number_t hwirq)
198 {
199 return irq_create_mapping(sachip->irqdomain, hwirq);
200 }
201
202 static void sa1111_handle_irqdomain(struct irq_domain *irqdomain, int irq)
203 {
204 struct irq_desc *d = irq_to_desc(irq_linear_revmap(irqdomain, irq));
205
206 if (d)
207 generic_handle_irq_desc(d);
208 }
209
210 /*
211 * SA1111 interrupt support. Since clearing an IRQ while there are
212 * active IRQs causes the interrupt output to pulse, the upper levels
213 * will call us again if there are more interrupts to process.
214 */
215 static void sa1111_irq_handler(struct irq_desc *desc)
216 {
217 unsigned int stat0, stat1, i;
218 struct sa1111 *sachip = irq_desc_get_handler_data(desc);
219 struct irq_domain *irqdomain;
220 void __iomem *mapbase = sachip->base + SA1111_INTC;
221
222 stat0 = readl_relaxed(mapbase + SA1111_INTSTATCLR0);
223 stat1 = readl_relaxed(mapbase + SA1111_INTSTATCLR1);
224
225 writel_relaxed(stat0, mapbase + SA1111_INTSTATCLR0);
226
227 desc->irq_data.chip->irq_ack(&desc->irq_data);
228
229 writel_relaxed(stat1, mapbase + SA1111_INTSTATCLR1);
230
231 if (stat0 == 0 && stat1 == 0) {
232 do_bad_IRQ(desc);
233 return;
234 }
235
236 irqdomain = sachip->irqdomain;
237
238 for (i = 0; stat0; i++, stat0 >>= 1)
239 if (stat0 & 1)
240 sa1111_handle_irqdomain(irqdomain, i);
241
242 for (i = 32; stat1; i++, stat1 >>= 1)
243 if (stat1 & 1)
244 sa1111_handle_irqdomain(irqdomain, i);
245
246 /* For level-based interrupts */
247 desc->irq_data.chip->irq_unmask(&desc->irq_data);
248 }
249
250 static u32 sa1111_irqmask(struct irq_data *d)
251 {
252 return BIT(irqd_to_hwirq(d) & 31);
253 }
254
255 static int sa1111_irqbank(struct irq_data *d)
256 {
257 return (irqd_to_hwirq(d) / 32) * 4;
258 }
259
260 static void sa1111_ack_irq(struct irq_data *d)
261 {
262 }
263
264 static void sa1111_mask_irq(struct irq_data *d)
265 {
266 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
267 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
268 u32 ie;
269
270 ie = readl_relaxed(mapbase + SA1111_INTEN0);
271 ie &= ~sa1111_irqmask(d);
272 writel(ie, mapbase + SA1111_INTEN0);
273 }
274
275 static void sa1111_unmask_irq(struct irq_data *d)
276 {
277 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
278 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
279 u32 ie;
280
281 ie = readl_relaxed(mapbase + SA1111_INTEN0);
282 ie |= sa1111_irqmask(d);
283 writel_relaxed(ie, mapbase + SA1111_INTEN0);
284 }
285
286 /*
287 * Attempt to re-trigger the interrupt. The SA1111 contains a register
288 * (INTSET) which claims to do this. However, in practice no amount of
289 * manipulation of INTEN and INTSET guarantees that the interrupt will
290 * be triggered. In fact, its very difficult, if not impossible to get
291 * INTSET to re-trigger the interrupt.
292 */
293 static int sa1111_retrigger_irq(struct irq_data *d)
294 {
295 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
296 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
297 u32 ip, mask = sa1111_irqmask(d);
298 int i;
299
300 ip = readl_relaxed(mapbase + SA1111_INTPOL0);
301 for (i = 0; i < 8; i++) {
302 writel_relaxed(ip ^ mask, mapbase + SA1111_INTPOL0);
303 writel_relaxed(ip, mapbase + SA1111_INTPOL0);
304 if (readl_relaxed(mapbase + SA1111_INTSTATCLR0) & mask)
305 break;
306 }
307
308 if (i == 8)
309 pr_err("Danger Will Robinson: failed to re-trigger IRQ%d\n",
310 d->irq);
311 return i == 8 ? -1 : 0;
312 }
313
314 static int sa1111_type_irq(struct irq_data *d, unsigned int flags)
315 {
316 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
317 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
318 u32 ip, mask = sa1111_irqmask(d);
319
320 if (flags == IRQ_TYPE_PROBE)
321 return 0;
322
323 if ((!(flags & IRQ_TYPE_EDGE_RISING) ^ !(flags & IRQ_TYPE_EDGE_FALLING)) == 0)
324 return -EINVAL;
325
326 ip = readl_relaxed(mapbase + SA1111_INTPOL0);
327 if (flags & IRQ_TYPE_EDGE_RISING)
328 ip &= ~mask;
329 else
330 ip |= mask;
331 writel_relaxed(ip, mapbase + SA1111_INTPOL0);
332 writel_relaxed(ip, mapbase + SA1111_WAKEPOL0);
333
334 return 0;
335 }
336
337 static int sa1111_wake_irq(struct irq_data *d, unsigned int on)
338 {
339 struct sa1111 *sachip = irq_data_get_irq_chip_data(d);
340 void __iomem *mapbase = sachip->base + SA1111_INTC + sa1111_irqbank(d);
341 u32 we, mask = sa1111_irqmask(d);
342
343 we = readl_relaxed(mapbase + SA1111_WAKEEN0);
344 if (on)
345 we |= mask;
346 else
347 we &= ~mask;
348 writel_relaxed(we, mapbase + SA1111_WAKEEN0);
349
350 return 0;
351 }
352
353 static struct irq_chip sa1111_irq_chip = {
354 .name = "SA1111",
355 .irq_ack = sa1111_ack_irq,
356 .irq_mask = sa1111_mask_irq,
357 .irq_unmask = sa1111_unmask_irq,
358 .irq_retrigger = sa1111_retrigger_irq,
359 .irq_set_type = sa1111_type_irq,
360 .irq_set_wake = sa1111_wake_irq,
361 };
362
363 static int sa1111_irqdomain_map(struct irq_domain *d, unsigned int irq,
364 irq_hw_number_t hwirq)
365 {
366 struct sa1111 *sachip = d->host_data;
367
368 /* Disallow unavailable interrupts */
369 if (hwirq > SSPROR && hwirq < AUDXMTDMADONEA)
370 return -EINVAL;
371
372 irq_set_chip_data(irq, sachip);
373 irq_set_chip_and_handler(irq, &sa1111_irq_chip, handle_edge_irq);
374 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
375
376 return 0;
377 }
378
379 static const struct irq_domain_ops sa1111_irqdomain_ops = {
380 .map = sa1111_irqdomain_map,
381 .xlate = irq_domain_xlate_twocell,
382 };
383
384 static int sa1111_setup_irq(struct sa1111 *sachip, unsigned irq_base)
385 {
386 void __iomem *irqbase = sachip->base + SA1111_INTC;
387 int ret;
388
389 /*
390 * We're guaranteed that this region hasn't been taken.
391 */
392 request_mem_region(sachip->phys + SA1111_INTC, 512, "irq");
393
394 ret = irq_alloc_descs(-1, irq_base, SA1111_IRQ_NR, -1);
395 if (ret <= 0) {
396 dev_err(sachip->dev, "unable to allocate %u irqs: %d\n",
397 SA1111_IRQ_NR, ret);
398 if (ret == 0)
399 ret = -EINVAL;
400 return ret;
401 }
402
403 sachip->irq_base = ret;
404
405 /* disable all IRQs */
406 writel_relaxed(0, irqbase + SA1111_INTEN0);
407 writel_relaxed(0, irqbase + SA1111_INTEN1);
408 writel_relaxed(0, irqbase + SA1111_WAKEEN0);
409 writel_relaxed(0, irqbase + SA1111_WAKEEN1);
410
411 /*
412 * detect on rising edge. Note: Feb 2001 Errata for SA1111
413 * specifies that S0ReadyInt and S1ReadyInt should be '1'.
414 */
415 writel_relaxed(0, irqbase + SA1111_INTPOL0);
416 writel_relaxed(BIT(IRQ_S0_READY_NINT & 31) |
417 BIT(IRQ_S1_READY_NINT & 31),
418 irqbase + SA1111_INTPOL1);
419
420 /* clear all IRQs */
421 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR0);
422 writel_relaxed(~0, irqbase + SA1111_INTSTATCLR1);
423
424 sachip->irqdomain = irq_domain_add_linear(NULL, SA1111_IRQ_NR,
425 &sa1111_irqdomain_ops,
426 sachip);
427 if (!sachip->irqdomain) {
428 irq_free_descs(sachip->irq_base, SA1111_IRQ_NR);
429 return -ENOMEM;
430 }
431
432 irq_domain_associate_many(sachip->irqdomain,
433 sachip->irq_base + IRQ_GPAIN0,
434 IRQ_GPAIN0, SSPROR + 1 - IRQ_GPAIN0);
435 irq_domain_associate_many(sachip->irqdomain,
436 sachip->irq_base + AUDXMTDMADONEA,
437 AUDXMTDMADONEA,
438 IRQ_S1_BVD1_STSCHG + 1 - AUDXMTDMADONEA);
439
440 /*
441 * Register SA1111 interrupt
442 */
443 irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
444 irq_set_chained_handler_and_data(sachip->irq, sa1111_irq_handler,
445 sachip);
446
447 dev_info(sachip->dev, "Providing IRQ%u-%u\n",
448 sachip->irq_base, sachip->irq_base + SA1111_IRQ_NR - 1);
449
450 return 0;
451 }
452
453 static void sa1111_remove_irq(struct sa1111 *sachip)
454 {
455 struct irq_domain *domain = sachip->irqdomain;
456 void __iomem *irqbase = sachip->base + SA1111_INTC;
457 int i;
458
459 /* disable all IRQs */
460 writel_relaxed(0, irqbase + SA1111_INTEN0);
461 writel_relaxed(0, irqbase + SA1111_INTEN1);
462 writel_relaxed(0, irqbase + SA1111_WAKEEN0);
463 writel_relaxed(0, irqbase + SA1111_WAKEEN1);
464
465 irq_set_chained_handler_and_data(sachip->irq, NULL, NULL);
466 for (i = 0; i < SA1111_IRQ_NR; i++)
467 irq_dispose_mapping(irq_find_mapping(domain, i));
468 irq_domain_remove(domain);
469
470 release_mem_region(sachip->phys + SA1111_INTC, 512);
471 }
472
473 enum {
474 SA1111_GPIO_PXDDR = (SA1111_GPIO_PADDR - SA1111_GPIO_PADDR),
475 SA1111_GPIO_PXDRR = (SA1111_GPIO_PADRR - SA1111_GPIO_PADDR),
476 SA1111_GPIO_PXDWR = (SA1111_GPIO_PADWR - SA1111_GPIO_PADDR),
477 SA1111_GPIO_PXSDR = (SA1111_GPIO_PASDR - SA1111_GPIO_PADDR),
478 SA1111_GPIO_PXSSR = (SA1111_GPIO_PASSR - SA1111_GPIO_PADDR),
479 };
480
481 static struct sa1111 *gc_to_sa1111(struct gpio_chip *gc)
482 {
483 return container_of(gc, struct sa1111, gc);
484 }
485
486 static void __iomem *sa1111_gpio_map_reg(struct sa1111 *sachip, unsigned offset)
487 {
488 void __iomem *reg = sachip->base + SA1111_GPIO;
489
490 if (offset < 4)
491 return reg + SA1111_GPIO_PADDR;
492 if (offset < 10)
493 return reg + SA1111_GPIO_PBDDR;
494 if (offset < 18)
495 return reg + SA1111_GPIO_PCDDR;
496 return NULL;
497 }
498
499 static u32 sa1111_gpio_map_bit(unsigned offset)
500 {
501 if (offset < 4)
502 return BIT(offset);
503 if (offset < 10)
504 return BIT(offset - 4);
505 if (offset < 18)
506 return BIT(offset - 10);
507 return 0;
508 }
509
510 static void sa1111_gpio_modify(void __iomem *reg, u32 mask, u32 set)
511 {
512 u32 val;
513
514 val = readl_relaxed(reg);
515 val &= ~mask;
516 val |= mask & set;
517 writel_relaxed(val, reg);
518 }
519
520 static int sa1111_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
521 {
522 struct sa1111 *sachip = gc_to_sa1111(gc);
523 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
524 u32 mask = sa1111_gpio_map_bit(offset);
525
526 return !!(readl_relaxed(reg + SA1111_GPIO_PXDDR) & mask);
527 }
528
529 static int sa1111_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
530 {
531 struct sa1111 *sachip = gc_to_sa1111(gc);
532 unsigned long flags;
533 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
534 u32 mask = sa1111_gpio_map_bit(offset);
535
536 spin_lock_irqsave(&sachip->lock, flags);
537 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, mask);
538 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, mask);
539 spin_unlock_irqrestore(&sachip->lock, flags);
540
541 return 0;
542 }
543
544 static int sa1111_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
545 int value)
546 {
547 struct sa1111 *sachip = gc_to_sa1111(gc);
548 unsigned long flags;
549 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
550 u32 mask = sa1111_gpio_map_bit(offset);
551
552 spin_lock_irqsave(&sachip->lock, flags);
553 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
554 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
555 sa1111_gpio_modify(reg + SA1111_GPIO_PXDDR, mask, 0);
556 sa1111_gpio_modify(reg + SA1111_GPIO_PXSDR, mask, 0);
557 spin_unlock_irqrestore(&sachip->lock, flags);
558
559 return 0;
560 }
561
562 static int sa1111_gpio_get(struct gpio_chip *gc, unsigned offset)
563 {
564 struct sa1111 *sachip = gc_to_sa1111(gc);
565 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
566 u32 mask = sa1111_gpio_map_bit(offset);
567
568 return !!(readl_relaxed(reg + SA1111_GPIO_PXDRR) & mask);
569 }
570
571 static void sa1111_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
572 {
573 struct sa1111 *sachip = gc_to_sa1111(gc);
574 unsigned long flags;
575 void __iomem *reg = sa1111_gpio_map_reg(sachip, offset);
576 u32 mask = sa1111_gpio_map_bit(offset);
577
578 spin_lock_irqsave(&sachip->lock, flags);
579 sa1111_gpio_modify(reg + SA1111_GPIO_PXDWR, mask, value ? mask : 0);
580 sa1111_gpio_modify(reg + SA1111_GPIO_PXSSR, mask, value ? mask : 0);
581 spin_unlock_irqrestore(&sachip->lock, flags);
582 }
583
584 static void sa1111_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
585 unsigned long *bits)
586 {
587 struct sa1111 *sachip = gc_to_sa1111(gc);
588 unsigned long flags;
589 void __iomem *reg = sachip->base + SA1111_GPIO;
590 u32 msk, val;
591
592 msk = *mask;
593 val = *bits;
594
595 spin_lock_irqsave(&sachip->lock, flags);
596 sa1111_gpio_modify(reg + SA1111_GPIO_PADWR, msk & 15, val);
597 sa1111_gpio_modify(reg + SA1111_GPIO_PASSR, msk & 15, val);
598 sa1111_gpio_modify(reg + SA1111_GPIO_PBDWR, (msk >> 4) & 255, val >> 4);
599 sa1111_gpio_modify(reg + SA1111_GPIO_PBSSR, (msk >> 4) & 255, val >> 4);
600 sa1111_gpio_modify(reg + SA1111_GPIO_PCDWR, (msk >> 12) & 255, val >> 12);
601 sa1111_gpio_modify(reg + SA1111_GPIO_PCSSR, (msk >> 12) & 255, val >> 12);
602 spin_unlock_irqrestore(&sachip->lock, flags);
603 }
604
605 static int sa1111_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
606 {
607 struct sa1111 *sachip = gc_to_sa1111(gc);
608
609 return sa1111_map_irq(sachip, offset);
610 }
611
612 static int sa1111_setup_gpios(struct sa1111 *sachip)
613 {
614 sachip->gc.label = "sa1111";
615 sachip->gc.parent = sachip->dev;
616 sachip->gc.owner = THIS_MODULE;
617 sachip->gc.get_direction = sa1111_gpio_get_direction;
618 sachip->gc.direction_input = sa1111_gpio_direction_input;
619 sachip->gc.direction_output = sa1111_gpio_direction_output;
620 sachip->gc.get = sa1111_gpio_get;
621 sachip->gc.set = sa1111_gpio_set;
622 sachip->gc.set_multiple = sa1111_gpio_set_multiple;
623 sachip->gc.to_irq = sa1111_gpio_to_irq;
624 sachip->gc.base = -1;
625 sachip->gc.ngpio = 18;
626
627 return devm_gpiochip_add_data(sachip->dev, &sachip->gc, sachip);
628 }
629
630 /*
631 * Bring the SA1111 out of reset. This requires a set procedure:
632 * 1. nRESET asserted (by hardware)
633 * 2. CLK turned on from SA1110
634 * 3. nRESET deasserted
635 * 4. VCO turned on, PLL_BYPASS turned off
636 * 5. Wait lock time, then assert RCLKEn
637 * 7. PCR set to allow clocking of individual functions
638 *
639 * Until we've done this, the only registers we can access are:
640 * SBI_SKCR
641 * SBI_SMCR
642 * SBI_SKID
643 */
644 static void sa1111_wake(struct sa1111 *sachip)
645 {
646 unsigned long flags, r;
647
648 spin_lock_irqsave(&sachip->lock, flags);
649
650 clk_enable(sachip->clk);
651
652 /*
653 * Turn VCO on, and disable PLL Bypass.
654 */
655 r = readl_relaxed(sachip->base + SA1111_SKCR);
656 r &= ~SKCR_VCO_OFF;
657 writel_relaxed(r, sachip->base + SA1111_SKCR);
658 r |= SKCR_PLL_BYPASS | SKCR_OE_EN;
659 writel_relaxed(r, sachip->base + SA1111_SKCR);
660
661 /*
662 * Wait lock time. SA1111 manual _doesn't_
663 * specify a figure for this! We choose 100us.
664 */
665 udelay(100);
666
667 /*
668 * Enable RCLK. We also ensure that RDYEN is set.
669 */
670 r |= SKCR_RCLKEN | SKCR_RDYEN;
671 writel_relaxed(r, sachip->base + SA1111_SKCR);
672
673 /*
674 * Wait 14 RCLK cycles for the chip to finish coming out
675 * of reset. (RCLK=24MHz). This is 590ns.
676 */
677 udelay(1);
678
679 /*
680 * Ensure all clocks are initially off.
681 */
682 writel_relaxed(0, sachip->base + SA1111_SKPCR);
683
684 spin_unlock_irqrestore(&sachip->lock, flags);
685 }
686
687 #ifdef CONFIG_ARCH_SA1100
688
689 static u32 sa1111_dma_mask[] = {
690 ~0,
691 ~(1 << 20),
692 ~(1 << 23),
693 ~(1 << 24),
694 ~(1 << 25),
695 ~(1 << 20),
696 ~(1 << 20),
697 0,
698 };
699
700 /*
701 * Configure the SA1111 shared memory controller.
702 */
703 void
704 sa1111_configure_smc(struct sa1111 *sachip, int sdram, unsigned int drac,
705 unsigned int cas_latency)
706 {
707 unsigned int smcr = SMCR_DTIM | SMCR_MBGE | FInsrt(drac, SMCR_DRAC);
708
709 if (cas_latency == 3)
710 smcr |= SMCR_CLAT;
711
712 writel_relaxed(smcr, sachip->base + SA1111_SMCR);
713
714 /*
715 * Now clear the bits in the DMA mask to work around the SA1111
716 * DMA erratum (Intel StrongARM SA-1111 Microprocessor Companion
717 * Chip Specification Update, June 2000, Erratum #7).
718 */
719 if (sachip->dev->dma_mask)
720 *sachip->dev->dma_mask &= sa1111_dma_mask[drac >> 2];
721
722 sachip->dev->coherent_dma_mask &= sa1111_dma_mask[drac >> 2];
723 }
724 #endif
725
726 static void sa1111_dev_release(struct device *_dev)
727 {
728 struct sa1111_dev *dev = to_sa1111_device(_dev);
729
730 kfree(dev);
731 }
732
733 static int
734 sa1111_init_one_child(struct sa1111 *sachip, struct resource *parent,
735 struct sa1111_dev_info *info)
736 {
737 struct sa1111_dev *dev;
738 unsigned i;
739 int ret;
740
741 dev = kzalloc(sizeof(struct sa1111_dev), GFP_KERNEL);
742 if (!dev) {
743 ret = -ENOMEM;
744 goto err_alloc;
745 }
746
747 device_initialize(&dev->dev);
748 dev_set_name(&dev->dev, "%4.4lx", info->offset);
749 dev->devid = info->devid;
750 dev->dev.parent = sachip->dev;
751 dev->dev.bus = &sa1111_bus_type;
752 dev->dev.release = sa1111_dev_release;
753 dev->res.start = sachip->phys + info->offset;
754 dev->res.end = dev->res.start + 511;
755 dev->res.name = dev_name(&dev->dev);
756 dev->res.flags = IORESOURCE_MEM;
757 dev->mapbase = sachip->base + info->offset;
758 dev->skpcr_mask = info->skpcr_mask;
759
760 for (i = 0; i < ARRAY_SIZE(info->hwirq); i++)
761 dev->hwirq[i] = info->hwirq[i];
762
763 /*
764 * If the parent device has a DMA mask associated with it, and
765 * this child supports DMA, propagate it down to the children.
766 */
767 if (info->dma && sachip->dev->dma_mask) {
768 dev->dma_mask = *sachip->dev->dma_mask;
769 dev->dev.dma_mask = &dev->dma_mask;
770 dev->dev.coherent_dma_mask = sachip->dev->coherent_dma_mask;
771 }
772
773 ret = request_resource(parent, &dev->res);
774 if (ret) {
775 dev_err(sachip->dev, "failed to allocate resource for %s\n",
776 dev->res.name);
777 goto err_resource;
778 }
779
780 ret = device_add(&dev->dev);
781 if (ret)
782 goto err_add;
783 return 0;
784
785 err_add:
786 release_resource(&dev->res);
787 err_resource:
788 put_device(&dev->dev);
789 err_alloc:
790 return ret;
791 }
792
793 /**
794 * sa1111_probe - probe for a single SA1111 chip.
795 * @phys_addr: physical address of device.
796 *
797 * Probe for a SA1111 chip. This must be called
798 * before any other SA1111-specific code.
799 *
800 * Returns:
801 * %-ENODEV device not found.
802 * %-EBUSY physical address already marked in-use.
803 * %-EINVAL no platform data passed
804 * %0 successful.
805 */
806 static int __sa1111_probe(struct device *me, struct resource *mem, int irq)
807 {
808 struct sa1111_platform_data *pd = me->platform_data;
809 struct sa1111 *sachip;
810 unsigned long id;
811 unsigned int has_devs;
812 int i, ret = -ENODEV;
813
814 if (!pd)
815 return -EINVAL;
816
817 sachip = devm_kzalloc(me, sizeof(struct sa1111), GFP_KERNEL);
818 if (!sachip)
819 return -ENOMEM;
820
821 sachip->clk = devm_clk_get(me, "SA1111_CLK");
822 if (IS_ERR(sachip->clk))
823 return PTR_ERR(sachip->clk);
824
825 ret = clk_prepare(sachip->clk);
826 if (ret)
827 return ret;
828
829 spin_lock_init(&sachip->lock);
830
831 sachip->dev = me;
832 dev_set_drvdata(sachip->dev, sachip);
833
834 sachip->pdata = pd;
835 sachip->phys = mem->start;
836 sachip->irq = irq;
837
838 /*
839 * Map the whole region. This also maps the
840 * registers for our children.
841 */
842 sachip->base = ioremap(mem->start, PAGE_SIZE * 2);
843 if (!sachip->base) {
844 ret = -ENOMEM;
845 goto err_clk_unprep;
846 }
847
848 /*
849 * Probe for the chip. Only touch the SBI registers.
850 */
851 id = readl_relaxed(sachip->base + SA1111_SKID);
852 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
853 printk(KERN_DEBUG "SA1111 not detected: ID = %08lx\n", id);
854 ret = -ENODEV;
855 goto err_unmap;
856 }
857
858 pr_info("SA1111 Microprocessor Companion Chip: silicon revision %lx, metal revision %lx\n",
859 (id & SKID_SIREV_MASK) >> 4, id & SKID_MTREV_MASK);
860
861 /*
862 * We found it. Wake the chip up, and initialise.
863 */
864 sa1111_wake(sachip);
865
866 /*
867 * The interrupt controller must be initialised before any
868 * other device to ensure that the interrupts are available.
869 */
870 ret = sa1111_setup_irq(sachip, pd->irq_base);
871 if (ret)
872 goto err_clk;
873
874 /* Setup the GPIOs - should really be done after the IRQ setup */
875 ret = sa1111_setup_gpios(sachip);
876 if (ret)
877 goto err_irq;
878
879 #ifdef CONFIG_ARCH_SA1100
880 {
881 unsigned int val;
882
883 /*
884 * The SDRAM configuration of the SA1110 and the SA1111 must
885 * match. This is very important to ensure that SA1111 accesses
886 * don't corrupt the SDRAM. Note that this ungates the SA1111's
887 * MBGNT signal, so we must have called sa1110_mb_disable()
888 * beforehand.
889 */
890 sa1111_configure_smc(sachip, 1,
891 FExtr(MDCNFG, MDCNFG_SA1110_DRAC0),
892 FExtr(MDCNFG, MDCNFG_SA1110_TDL0));
893
894 /*
895 * We only need to turn on DCLK whenever we want to use the
896 * DMA. It can otherwise be held firmly in the off position.
897 * (currently, we always enable it.)
898 */
899 val = readl_relaxed(sachip->base + SA1111_SKPCR);
900 writel_relaxed(val | SKPCR_DCLKEN, sachip->base + SA1111_SKPCR);
901
902 /*
903 * Enable the SA1110 memory bus request and grant signals.
904 */
905 sa1110_mb_enable();
906 }
907 #endif
908
909 g_sa1111 = sachip;
910
911 has_devs = ~0;
912 if (pd)
913 has_devs &= ~pd->disable_devs;
914
915 for (i = 0; i < ARRAY_SIZE(sa1111_devices); i++)
916 if (sa1111_devices[i].devid & has_devs)
917 sa1111_init_one_child(sachip, mem, &sa1111_devices[i]);
918
919 return 0;
920
921 err_irq:
922 sa1111_remove_irq(sachip);
923 err_clk:
924 clk_disable(sachip->clk);
925 err_unmap:
926 iounmap(sachip->base);
927 err_clk_unprep:
928 clk_unprepare(sachip->clk);
929 return ret;
930 }
931
932 static int sa1111_remove_one(struct device *dev, void *data)
933 {
934 struct sa1111_dev *sadev = to_sa1111_device(dev);
935 if (dev->bus != &sa1111_bus_type)
936 return 0;
937 device_del(&sadev->dev);
938 release_resource(&sadev->res);
939 put_device(&sadev->dev);
940 return 0;
941 }
942
943 static void __sa1111_remove(struct sa1111 *sachip)
944 {
945 device_for_each_child(sachip->dev, NULL, sa1111_remove_one);
946
947 sa1111_remove_irq(sachip);
948
949 clk_disable(sachip->clk);
950 clk_unprepare(sachip->clk);
951
952 iounmap(sachip->base);
953 }
954
955 struct sa1111_save_data {
956 unsigned int skcr;
957 unsigned int skpcr;
958 unsigned int skcdr;
959 unsigned char skaud;
960 unsigned char skpwm0;
961 unsigned char skpwm1;
962
963 /*
964 * Interrupt controller
965 */
966 unsigned int intpol0;
967 unsigned int intpol1;
968 unsigned int inten0;
969 unsigned int inten1;
970 unsigned int wakepol0;
971 unsigned int wakepol1;
972 unsigned int wakeen0;
973 unsigned int wakeen1;
974 };
975
976 #ifdef CONFIG_PM
977
978 static int sa1111_suspend_noirq(struct device *dev)
979 {
980 struct sa1111 *sachip = dev_get_drvdata(dev);
981 struct sa1111_save_data *save;
982 unsigned long flags;
983 unsigned int val;
984 void __iomem *base;
985
986 save = kmalloc(sizeof(struct sa1111_save_data), GFP_KERNEL);
987 if (!save)
988 return -ENOMEM;
989 sachip->saved_state = save;
990
991 spin_lock_irqsave(&sachip->lock, flags);
992
993 /*
994 * Save state.
995 */
996 base = sachip->base;
997 save->skcr = readl_relaxed(base + SA1111_SKCR);
998 save->skpcr = readl_relaxed(base + SA1111_SKPCR);
999 save->skcdr = readl_relaxed(base + SA1111_SKCDR);
1000 save->skaud = readl_relaxed(base + SA1111_SKAUD);
1001 save->skpwm0 = readl_relaxed(base + SA1111_SKPWM0);
1002 save->skpwm1 = readl_relaxed(base + SA1111_SKPWM1);
1003
1004 writel_relaxed(0, sachip->base + SA1111_SKPWM0);
1005 writel_relaxed(0, sachip->base + SA1111_SKPWM1);
1006
1007 base = sachip->base + SA1111_INTC;
1008 save->intpol0 = readl_relaxed(base + SA1111_INTPOL0);
1009 save->intpol1 = readl_relaxed(base + SA1111_INTPOL1);
1010 save->inten0 = readl_relaxed(base + SA1111_INTEN0);
1011 save->inten1 = readl_relaxed(base + SA1111_INTEN1);
1012 save->wakepol0 = readl_relaxed(base + SA1111_WAKEPOL0);
1013 save->wakepol1 = readl_relaxed(base + SA1111_WAKEPOL1);
1014 save->wakeen0 = readl_relaxed(base + SA1111_WAKEEN0);
1015 save->wakeen1 = readl_relaxed(base + SA1111_WAKEEN1);
1016
1017 /*
1018 * Disable.
1019 */
1020 val = readl_relaxed(sachip->base + SA1111_SKCR);
1021 writel_relaxed(val | SKCR_SLEEP, sachip->base + SA1111_SKCR);
1022
1023 clk_disable(sachip->clk);
1024
1025 spin_unlock_irqrestore(&sachip->lock, flags);
1026
1027 #ifdef CONFIG_ARCH_SA1100
1028 sa1110_mb_disable();
1029 #endif
1030
1031 return 0;
1032 }
1033
1034 /*
1035 * sa1111_resume - Restore the SA1111 device state.
1036 * @dev: device to restore
1037 *
1038 * Restore the general state of the SA1111; clock control and
1039 * interrupt controller. Other parts of the SA1111 must be
1040 * restored by their respective drivers, and must be called
1041 * via LDM after this function.
1042 */
1043 static int sa1111_resume_noirq(struct device *dev)
1044 {
1045 struct sa1111 *sachip = dev_get_drvdata(dev);
1046 struct sa1111_save_data *save;
1047 unsigned long flags, id;
1048 void __iomem *base;
1049
1050 save = sachip->saved_state;
1051 if (!save)
1052 return 0;
1053
1054 /*
1055 * Ensure that the SA1111 is still here.
1056 * FIXME: shouldn't do this here.
1057 */
1058 id = readl_relaxed(sachip->base + SA1111_SKID);
1059 if ((id & SKID_ID_MASK) != SKID_SA1111_ID) {
1060 __sa1111_remove(sachip);
1061 dev_set_drvdata(dev, NULL);
1062 kfree(save);
1063 return 0;
1064 }
1065
1066 /*
1067 * First of all, wake up the chip.
1068 */
1069 sa1111_wake(sachip);
1070
1071 #ifdef CONFIG_ARCH_SA1100
1072 /* Enable the memory bus request/grant signals */
1073 sa1110_mb_enable();
1074 #endif
1075
1076 /*
1077 * Only lock for write ops. Also, sa1111_wake must be called with
1078 * released spinlock!
1079 */
1080 spin_lock_irqsave(&sachip->lock, flags);
1081
1082 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN0);
1083 writel_relaxed(0, sachip->base + SA1111_INTC + SA1111_INTEN1);
1084
1085 base = sachip->base;
1086 writel_relaxed(save->skcr, base + SA1111_SKCR);
1087 writel_relaxed(save->skpcr, base + SA1111_SKPCR);
1088 writel_relaxed(save->skcdr, base + SA1111_SKCDR);
1089 writel_relaxed(save->skaud, base + SA1111_SKAUD);
1090 writel_relaxed(save->skpwm0, base + SA1111_SKPWM0);
1091 writel_relaxed(save->skpwm1, base + SA1111_SKPWM1);
1092
1093 base = sachip->base + SA1111_INTC;
1094 writel_relaxed(save->intpol0, base + SA1111_INTPOL0);
1095 writel_relaxed(save->intpol1, base + SA1111_INTPOL1);
1096 writel_relaxed(save->inten0, base + SA1111_INTEN0);
1097 writel_relaxed(save->inten1, base + SA1111_INTEN1);
1098 writel_relaxed(save->wakepol0, base + SA1111_WAKEPOL0);
1099 writel_relaxed(save->wakepol1, base + SA1111_WAKEPOL1);
1100 writel_relaxed(save->wakeen0, base + SA1111_WAKEEN0);
1101 writel_relaxed(save->wakeen1, base + SA1111_WAKEEN1);
1102
1103 spin_unlock_irqrestore(&sachip->lock, flags);
1104
1105 sachip->saved_state = NULL;
1106 kfree(save);
1107
1108 return 0;
1109 }
1110
1111 #else
1112 #define sa1111_suspend_noirq NULL
1113 #define sa1111_resume_noirq NULL
1114 #endif
1115
1116 static int sa1111_probe(struct platform_device *pdev)
1117 {
1118 struct resource *mem;
1119 int irq;
1120
1121 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1122 if (!mem)
1123 return -EINVAL;
1124 irq = platform_get_irq(pdev, 0);
1125 if (irq < 0)
1126 return irq;
1127
1128 return __sa1111_probe(&pdev->dev, mem, irq);
1129 }
1130
1131 static int sa1111_remove(struct platform_device *pdev)
1132 {
1133 struct sa1111 *sachip = platform_get_drvdata(pdev);
1134
1135 if (sachip) {
1136 #ifdef CONFIG_PM
1137 kfree(sachip->saved_state);
1138 sachip->saved_state = NULL;
1139 #endif
1140 __sa1111_remove(sachip);
1141 platform_set_drvdata(pdev, NULL);
1142 }
1143
1144 return 0;
1145 }
1146
1147 static struct dev_pm_ops sa1111_pm_ops = {
1148 .suspend_noirq = sa1111_suspend_noirq,
1149 .resume_noirq = sa1111_resume_noirq,
1150 };
1151
1152 /*
1153 * Not sure if this should be on the system bus or not yet.
1154 * We really want some way to register a system device at
1155 * the per-machine level, and then have this driver pick
1156 * up the registered devices.
1157 *
1158 * We also need to handle the SDRAM configuration for
1159 * PXA250/SA1110 machine classes.
1160 */
1161 static struct platform_driver sa1111_device_driver = {
1162 .probe = sa1111_probe,
1163 .remove = sa1111_remove,
1164 .driver = {
1165 .name = "sa1111",
1166 .pm = &sa1111_pm_ops,
1167 },
1168 };
1169
1170 /*
1171 * Get the parent device driver (us) structure
1172 * from a child function device
1173 */
1174 static inline struct sa1111 *sa1111_chip_driver(struct sa1111_dev *sadev)
1175 {
1176 return (struct sa1111 *)dev_get_drvdata(sadev->dev.parent);
1177 }
1178
1179 /*
1180 * The bits in the opdiv field are non-linear.
1181 */
1182 static unsigned char opdiv_table[] = { 1, 4, 2, 8 };
1183
1184 static unsigned int __sa1111_pll_clock(struct sa1111 *sachip)
1185 {
1186 unsigned int skcdr, fbdiv, ipdiv, opdiv;
1187
1188 skcdr = readl_relaxed(sachip->base + SA1111_SKCDR);
1189
1190 fbdiv = (skcdr & 0x007f) + 2;
1191 ipdiv = ((skcdr & 0x0f80) >> 7) + 2;
1192 opdiv = opdiv_table[(skcdr & 0x3000) >> 12];
1193
1194 return 3686400 * fbdiv / (ipdiv * opdiv);
1195 }
1196
1197 /**
1198 * sa1111_pll_clock - return the current PLL clock frequency.
1199 * @sadev: SA1111 function block
1200 *
1201 * BUG: we should look at SKCR. We also blindly believe that
1202 * the chip is being fed with the 3.6864MHz clock.
1203 *
1204 * Returns the PLL clock in Hz.
1205 */
1206 unsigned int sa1111_pll_clock(struct sa1111_dev *sadev)
1207 {
1208 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1209
1210 return __sa1111_pll_clock(sachip);
1211 }
1212 EXPORT_SYMBOL(sa1111_pll_clock);
1213
1214 /**
1215 * sa1111_select_audio_mode - select I2S or AC link mode
1216 * @sadev: SA1111 function block
1217 * @mode: One of %SA1111_AUDIO_ACLINK or %SA1111_AUDIO_I2S
1218 *
1219 * Frob the SKCR to select AC Link mode or I2S mode for
1220 * the audio block.
1221 */
1222 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode)
1223 {
1224 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1225 unsigned long flags;
1226 unsigned int val;
1227
1228 spin_lock_irqsave(&sachip->lock, flags);
1229
1230 val = readl_relaxed(sachip->base + SA1111_SKCR);
1231 if (mode == SA1111_AUDIO_I2S) {
1232 val &= ~SKCR_SELAC;
1233 } else {
1234 val |= SKCR_SELAC;
1235 }
1236 writel_relaxed(val, sachip->base + SA1111_SKCR);
1237
1238 spin_unlock_irqrestore(&sachip->lock, flags);
1239 }
1240 EXPORT_SYMBOL(sa1111_select_audio_mode);
1241
1242 /**
1243 * sa1111_set_audio_rate - set the audio sample rate
1244 * @sadev: SA1111 SAC function block
1245 * @rate: sample rate to select
1246 */
1247 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate)
1248 {
1249 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1250 unsigned int div;
1251
1252 if (sadev->devid != SA1111_DEVID_SAC)
1253 return -EINVAL;
1254
1255 div = (__sa1111_pll_clock(sachip) / 256 + rate / 2) / rate;
1256 if (div == 0)
1257 div = 1;
1258 if (div > 128)
1259 div = 128;
1260
1261 writel_relaxed(div - 1, sachip->base + SA1111_SKAUD);
1262
1263 return 0;
1264 }
1265 EXPORT_SYMBOL(sa1111_set_audio_rate);
1266
1267 /**
1268 * sa1111_get_audio_rate - get the audio sample rate
1269 * @sadev: SA1111 SAC function block device
1270 */
1271 int sa1111_get_audio_rate(struct sa1111_dev *sadev)
1272 {
1273 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1274 unsigned long div;
1275
1276 if (sadev->devid != SA1111_DEVID_SAC)
1277 return -EINVAL;
1278
1279 div = readl_relaxed(sachip->base + SA1111_SKAUD) + 1;
1280
1281 return __sa1111_pll_clock(sachip) / (256 * div);
1282 }
1283 EXPORT_SYMBOL(sa1111_get_audio_rate);
1284
1285 void sa1111_set_io_dir(struct sa1111_dev *sadev,
1286 unsigned int bits, unsigned int dir,
1287 unsigned int sleep_dir)
1288 {
1289 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1290 unsigned long flags;
1291 unsigned int val;
1292 void __iomem *gpio = sachip->base + SA1111_GPIO;
1293
1294 #define MODIFY_BITS(port, mask, dir) \
1295 if (mask) { \
1296 val = readl_relaxed(port); \
1297 val &= ~(mask); \
1298 val |= (dir) & (mask); \
1299 writel_relaxed(val, port); \
1300 }
1301
1302 spin_lock_irqsave(&sachip->lock, flags);
1303 MODIFY_BITS(gpio + SA1111_GPIO_PADDR, bits & 15, dir);
1304 MODIFY_BITS(gpio + SA1111_GPIO_PBDDR, (bits >> 8) & 255, dir >> 8);
1305 MODIFY_BITS(gpio + SA1111_GPIO_PCDDR, (bits >> 16) & 255, dir >> 16);
1306
1307 MODIFY_BITS(gpio + SA1111_GPIO_PASDR, bits & 15, sleep_dir);
1308 MODIFY_BITS(gpio + SA1111_GPIO_PBSDR, (bits >> 8) & 255, sleep_dir >> 8);
1309 MODIFY_BITS(gpio + SA1111_GPIO_PCSDR, (bits >> 16) & 255, sleep_dir >> 16);
1310 spin_unlock_irqrestore(&sachip->lock, flags);
1311 }
1312 EXPORT_SYMBOL(sa1111_set_io_dir);
1313
1314 void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v)
1315 {
1316 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1317 unsigned long flags;
1318 unsigned int val;
1319 void __iomem *gpio = sachip->base + SA1111_GPIO;
1320
1321 spin_lock_irqsave(&sachip->lock, flags);
1322 MODIFY_BITS(gpio + SA1111_GPIO_PADWR, bits & 15, v);
1323 MODIFY_BITS(gpio + SA1111_GPIO_PBDWR, (bits >> 8) & 255, v >> 8);
1324 MODIFY_BITS(gpio + SA1111_GPIO_PCDWR, (bits >> 16) & 255, v >> 16);
1325 spin_unlock_irqrestore(&sachip->lock, flags);
1326 }
1327 EXPORT_SYMBOL(sa1111_set_io);
1328
1329 void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v)
1330 {
1331 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1332 unsigned long flags;
1333 unsigned int val;
1334 void __iomem *gpio = sachip->base + SA1111_GPIO;
1335
1336 spin_lock_irqsave(&sachip->lock, flags);
1337 MODIFY_BITS(gpio + SA1111_GPIO_PASSR, bits & 15, v);
1338 MODIFY_BITS(gpio + SA1111_GPIO_PBSSR, (bits >> 8) & 255, v >> 8);
1339 MODIFY_BITS(gpio + SA1111_GPIO_PCSSR, (bits >> 16) & 255, v >> 16);
1340 spin_unlock_irqrestore(&sachip->lock, flags);
1341 }
1342 EXPORT_SYMBOL(sa1111_set_sleep_io);
1343
1344 /*
1345 * Individual device operations.
1346 */
1347
1348 /**
1349 * sa1111_enable_device - enable an on-chip SA1111 function block
1350 * @sadev: SA1111 function block device to enable
1351 */
1352 int sa1111_enable_device(struct sa1111_dev *sadev)
1353 {
1354 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1355 unsigned long flags;
1356 unsigned int val;
1357 int ret = 0;
1358
1359 if (sachip->pdata && sachip->pdata->enable)
1360 ret = sachip->pdata->enable(sachip->pdata->data, sadev->devid);
1361
1362 if (ret == 0) {
1363 spin_lock_irqsave(&sachip->lock, flags);
1364 val = readl_relaxed(sachip->base + SA1111_SKPCR);
1365 writel_relaxed(val | sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1366 spin_unlock_irqrestore(&sachip->lock, flags);
1367 }
1368 return ret;
1369 }
1370 EXPORT_SYMBOL(sa1111_enable_device);
1371
1372 /**
1373 * sa1111_disable_device - disable an on-chip SA1111 function block
1374 * @sadev: SA1111 function block device to disable
1375 */
1376 void sa1111_disable_device(struct sa1111_dev *sadev)
1377 {
1378 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1379 unsigned long flags;
1380 unsigned int val;
1381
1382 spin_lock_irqsave(&sachip->lock, flags);
1383 val = readl_relaxed(sachip->base + SA1111_SKPCR);
1384 writel_relaxed(val & ~sadev->skpcr_mask, sachip->base + SA1111_SKPCR);
1385 spin_unlock_irqrestore(&sachip->lock, flags);
1386
1387 if (sachip->pdata && sachip->pdata->disable)
1388 sachip->pdata->disable(sachip->pdata->data, sadev->devid);
1389 }
1390 EXPORT_SYMBOL(sa1111_disable_device);
1391
1392 int sa1111_get_irq(struct sa1111_dev *sadev, unsigned num)
1393 {
1394 struct sa1111 *sachip = sa1111_chip_driver(sadev);
1395 if (num >= ARRAY_SIZE(sadev->hwirq))
1396 return -EINVAL;
1397 return sa1111_map_irq(sachip, sadev->hwirq[num]);
1398 }
1399 EXPORT_SYMBOL_GPL(sa1111_get_irq);
1400
1401 /*
1402 * SA1111 "Register Access Bus."
1403 *
1404 * We model this as a regular bus type, and hang devices directly
1405 * off this.
1406 */
1407 static int sa1111_match(struct device *_dev, struct device_driver *_drv)
1408 {
1409 struct sa1111_dev *dev = to_sa1111_device(_dev);
1410 struct sa1111_driver *drv = SA1111_DRV(_drv);
1411
1412 return !!(dev->devid & drv->devid);
1413 }
1414
1415 static int sa1111_bus_probe(struct device *dev)
1416 {
1417 struct sa1111_dev *sadev = to_sa1111_device(dev);
1418 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1419 int ret = -ENODEV;
1420
1421 if (drv->probe)
1422 ret = drv->probe(sadev);
1423 return ret;
1424 }
1425
1426 static int sa1111_bus_remove(struct device *dev)
1427 {
1428 struct sa1111_dev *sadev = to_sa1111_device(dev);
1429 struct sa1111_driver *drv = SA1111_DRV(dev->driver);
1430 int ret = 0;
1431
1432 if (drv->remove)
1433 ret = drv->remove(sadev);
1434 return ret;
1435 }
1436
1437 struct bus_type sa1111_bus_type = {
1438 .name = "sa1111-rab",
1439 .match = sa1111_match,
1440 .probe = sa1111_bus_probe,
1441 .remove = sa1111_bus_remove,
1442 };
1443 EXPORT_SYMBOL(sa1111_bus_type);
1444
1445 int sa1111_driver_register(struct sa1111_driver *driver)
1446 {
1447 driver->drv.bus = &sa1111_bus_type;
1448 return driver_register(&driver->drv);
1449 }
1450 EXPORT_SYMBOL(sa1111_driver_register);
1451
1452 void sa1111_driver_unregister(struct sa1111_driver *driver)
1453 {
1454 driver_unregister(&driver->drv);
1455 }
1456 EXPORT_SYMBOL(sa1111_driver_unregister);
1457
1458 #ifdef CONFIG_DMABOUNCE
1459 /*
1460 * According to the "Intel StrongARM SA-1111 Microprocessor Companion
1461 * Chip Specification Update" (June 2000), erratum #7, there is a
1462 * significant bug in the SA1111 SDRAM shared memory controller. If
1463 * an access to a region of memory above 1MB relative to the bank base,
1464 * it is important that address bit 10 _NOT_ be asserted. Depending
1465 * on the configuration of the RAM, bit 10 may correspond to one
1466 * of several different (processor-relative) address bits.
1467 *
1468 * This routine only identifies whether or not a given DMA address
1469 * is susceptible to the bug.
1470 *
1471 * This should only get called for sa1111_device types due to the
1472 * way we configure our device dma_masks.
1473 */
1474 static int sa1111_needs_bounce(struct device *dev, dma_addr_t addr, size_t size)
1475 {
1476 /*
1477 * Section 4.6 of the "Intel StrongARM SA-1111 Development Module
1478 * User's Guide" mentions that jumpers R51 and R52 control the
1479 * target of SA-1111 DMA (either SDRAM bank 0 on Assabet, or
1480 * SDRAM bank 1 on Neponset). The default configuration selects
1481 * Assabet, so any address in bank 1 is necessarily invalid.
1482 */
1483 return (machine_is_assabet() || machine_is_pfs168()) &&
1484 (addr >= 0xc8000000 || (addr + size) >= 0xc8000000);
1485 }
1486
1487 static int sa1111_notifier_call(struct notifier_block *n, unsigned long action,
1488 void *data)
1489 {
1490 struct sa1111_dev *dev = to_sa1111_device(data);
1491
1492 switch (action) {
1493 case BUS_NOTIFY_ADD_DEVICE:
1494 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL) {
1495 int ret = dmabounce_register_dev(&dev->dev, 1024, 4096,
1496 sa1111_needs_bounce);
1497 if (ret)
1498 dev_err(&dev->dev, "failed to register with dmabounce: %d\n", ret);
1499 }
1500 break;
1501
1502 case BUS_NOTIFY_DEL_DEVICE:
1503 if (dev->dev.dma_mask && dev->dma_mask < 0xffffffffUL)
1504 dmabounce_unregister_dev(&dev->dev);
1505 break;
1506 }
1507 return NOTIFY_OK;
1508 }
1509
1510 static struct notifier_block sa1111_bus_notifier = {
1511 .notifier_call = sa1111_notifier_call,
1512 };
1513 #endif
1514
1515 static int __init sa1111_init(void)
1516 {
1517 int ret = bus_register(&sa1111_bus_type);
1518 #ifdef CONFIG_DMABOUNCE
1519 if (ret == 0)
1520 bus_register_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
1521 #endif
1522 if (ret == 0)
1523 platform_driver_register(&sa1111_device_driver);
1524 return ret;
1525 }
1526
1527 static void __exit sa1111_exit(void)
1528 {
1529 platform_driver_unregister(&sa1111_device_driver);
1530 #ifdef CONFIG_DMABOUNCE
1531 bus_unregister_notifier(&sa1111_bus_type, &sa1111_bus_notifier);
1532 #endif
1533 bus_unregister(&sa1111_bus_type);
1534 }
1535
1536 subsys_initcall(sa1111_init);
1537 module_exit(sa1111_exit);
1538
1539 MODULE_DESCRIPTION("Intel Corporation SA1111 core driver");
1540 MODULE_LICENSE("GPL");
Linux with added FPC-III support