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V4L: pvrusb2: Limit hor res for 24xxx devices
[linux/fpc-iii.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
bloba36a69d9e7de71bfe234e8bd64906891e467bb55
1 /*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <asm/semaphore.h>
28 #include "pvrusb2.h"
29 #include "pvrusb2-std.h"
30 #include "pvrusb2-util.h"
31 #include "pvrusb2-hdw.h"
32 #include "pvrusb2-i2c-core.h"
33 #include "pvrusb2-tuner.h"
34 #include "pvrusb2-eeprom.h"
35 #include "pvrusb2-hdw-internal.h"
36 #include "pvrusb2-encoder.h"
37 #include "pvrusb2-debug.h"
38
39 struct usb_device_id pvr2_device_table[] = {
40 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
41 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
42 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
43 #endif
44 { }
45 };
46
47 MODULE_DEVICE_TABLE(usb, pvr2_device_table);
48
49 static const char *pvr2_device_names[] = {
50 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
51 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
52 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
53 #endif
54 };
55
56 struct pvr2_string_table {
57 const char **lst;
58 unsigned int cnt;
59 };
60
61 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
62 // Names of other client modules to request for 24xxx model hardware
63 static const char *pvr2_client_24xxx[] = {
64 "cx25840",
65 "tuner",
66 "wm8775",
67 };
68 #endif
69
70 // Names of other client modules to request for 29xxx model hardware
71 static const char *pvr2_client_29xxx[] = {
72 "msp3400",
73 "saa7115",
74 "tuner",
75 };
76
77 static struct pvr2_string_table pvr2_client_lists[] = {
78 [PVR2_HDW_TYPE_29XXX] = {
79 pvr2_client_29xxx,
80 sizeof(pvr2_client_29xxx)/sizeof(pvr2_client_29xxx[0]),
81 },
82 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
83 [PVR2_HDW_TYPE_24XXX] = {
84 pvr2_client_24xxx,
85 sizeof(pvr2_client_24xxx)/sizeof(pvr2_client_24xxx[0]),
86 },
87 #endif
88 };
89
90 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
91 static DECLARE_MUTEX(pvr2_unit_sem);
92
93 static int ctlchg = 0;
94 static int initusbreset = 1;
95 static int procreload = 0;
96 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
97 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
98 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
99 static int init_pause_msec = 0;
100
101 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
102 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
103 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
104 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
105 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
106 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
107 module_param(procreload, int, S_IRUGO|S_IWUSR);
108 MODULE_PARM_DESC(procreload,
109 "Attempt init failure recovery with firmware reload");
110 module_param_array(tuner, int, NULL, 0444);
111 MODULE_PARM_DESC(tuner,"specify installed tuner type");
112 module_param_array(video_std, int, NULL, 0444);
113 MODULE_PARM_DESC(video_std,"specify initial video standard");
114 module_param_array(tolerance, int, NULL, 0444);
115 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
116
117 #define PVR2_CTL_WRITE_ENDPOINT 0x01
118 #define PVR2_CTL_READ_ENDPOINT 0x81
119
120 #define PVR2_GPIO_IN 0x9008
121 #define PVR2_GPIO_OUT 0x900c
122 #define PVR2_GPIO_DIR 0x9020
123
124 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
125
126 #define PVR2_FIRMWARE_ENDPOINT 0x02
127
128 /* size of a firmware chunk */
129 #define FIRMWARE_CHUNK_SIZE 0x2000
130
131 /* Define the list of additional controls we'll dynamically construct based
132 on query of the cx2341x module. */
133 struct pvr2_mpeg_ids {
134 const char *strid;
135 int id;
136 };
137 static const struct pvr2_mpeg_ids mpeg_ids[] = {
138 {
139 .strid = "audio_layer",
140 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
141 },{
142 .strid = "audio_bitrate",
143 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
144 },{
145 /* Already using audio_mode elsewhere :-( */
146 .strid = "mpeg_audio_mode",
147 .id = V4L2_CID_MPEG_AUDIO_MODE,
148 },{
149 .strid = "mpeg_audio_mode_extension",
150 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
151 },{
152 .strid = "audio_emphasis",
153 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
154 },{
155 .strid = "audio_crc",
156 .id = V4L2_CID_MPEG_AUDIO_CRC,
157 },{
158 .strid = "video_aspect",
159 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
160 },{
161 .strid = "video_b_frames",
162 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
163 },{
164 .strid = "video_gop_size",
165 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
166 },{
167 .strid = "video_gop_closure",
168 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
169 },{
170 .strid = "video_pulldown",
171 .id = V4L2_CID_MPEG_VIDEO_PULLDOWN,
172 },{
173 .strid = "video_bitrate_mode",
174 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
175 },{
176 .strid = "video_bitrate",
177 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
178 },{
179 .strid = "video_bitrate_peak",
180 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
181 },{
182 .strid = "video_temporal_decimation",
183 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
184 },{
185 .strid = "stream_type",
186 .id = V4L2_CID_MPEG_STREAM_TYPE,
187 },{
188 .strid = "video_spatial_filter_mode",
189 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
190 },{
191 .strid = "video_spatial_filter",
192 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
193 },{
194 .strid = "video_luma_spatial_filter_type",
195 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
196 },{
197 .strid = "video_chroma_spatial_filter_type",
198 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
199 },{
200 .strid = "video_temporal_filter_mode",
201 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
202 },{
203 .strid = "video_temporal_filter",
204 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
205 },{
206 .strid = "video_median_filter_type",
207 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
208 },{
209 .strid = "video_luma_median_filter_top",
210 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
211 },{
212 .strid = "video_luma_median_filter_bottom",
213 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
214 },{
215 .strid = "video_chroma_median_filter_top",
216 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
217 },{
218 .strid = "video_chroma_median_filter_bottom",
219 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
220 }
221 };
222 #define MPEGDEF_COUNT (sizeof(mpeg_ids)/sizeof(mpeg_ids[0]))
223
224 static const char *control_values_srate[] = {
225 [PVR2_CVAL_SRATE_48] = "48KHz",
226 [PVR2_CVAL_SRATE_44_1] = "44.1KHz",
227 };
228
229
230
231
232 static const char *control_values_input[] = {
233 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
234 [PVR2_CVAL_INPUT_RADIO] = "radio",
235 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
236 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
237 };
238
239
240 static const char *control_values_audiomode[] = {
241 [V4L2_TUNER_MODE_MONO] = "Mono",
242 [V4L2_TUNER_MODE_STEREO] = "Stereo",
243 [V4L2_TUNER_MODE_LANG1] = "Lang1",
244 [V4L2_TUNER_MODE_LANG2] = "Lang2",
245 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
246 };
247
248
249 static const char *control_values_hsm[] = {
250 [PVR2_CVAL_HSM_FAIL] = "Fail",
251 [PVR2_CVAL_HSM_HIGH] = "High",
252 [PVR2_CVAL_HSM_FULL] = "Full",
253 };
254
255
256 static const char *control_values_subsystem[] = {
257 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
258 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
259 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
260 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
261 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
262 };
263
264 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
265 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
266 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
267 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw);
268 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
269 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
270 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
271 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
272 unsigned long msk,
273 unsigned long val);
274 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
275 unsigned long msk,
276 unsigned long val);
277 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
278 unsigned int timeout,int probe_fl,
279 void *write_data,unsigned int write_len,
280 void *read_data,unsigned int read_len);
281 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res);
282 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res);
283
284 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
285 {
286 struct pvr2_hdw *hdw = cptr->hdw;
287 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
288 *vp = hdw->freqTable[hdw->freqProgSlot-1];
289 } else {
290 *vp = 0;
291 }
292 return 0;
293 }
294
295 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
296 {
297 struct pvr2_hdw *hdw = cptr->hdw;
298 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
299 hdw->freqTable[hdw->freqProgSlot-1] = v;
300 }
301 return 0;
302 }
303
304 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
305 {
306 *vp = cptr->hdw->freqProgSlot;
307 return 0;
308 }
309
310 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
311 {
312 struct pvr2_hdw *hdw = cptr->hdw;
313 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
314 hdw->freqProgSlot = v;
315 }
316 return 0;
317 }
318
319 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
320 {
321 *vp = cptr->hdw->freqSlot;
322 return 0;
323 }
324
325 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int v)
326 {
327 unsigned freq = 0;
328 struct pvr2_hdw *hdw = cptr->hdw;
329 hdw->freqSlot = v;
330 if ((hdw->freqSlot > 0) && (hdw->freqSlot <= FREQTABLE_SIZE)) {
331 freq = hdw->freqTable[hdw->freqSlot-1];
332 }
333 if (freq && (freq != hdw->freqVal)) {
334 hdw->freqVal = freq;
335 hdw->freqDirty = !0;
336 }
337 return 0;
338 }
339
340 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
341 {
342 *vp = cptr->hdw->freqVal;
343 return 0;
344 }
345
346 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
347 {
348 return cptr->hdw->freqDirty != 0;
349 }
350
351 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
352 {
353 cptr->hdw->freqDirty = 0;
354 }
355
356 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
357 {
358 struct pvr2_hdw *hdw = cptr->hdw;
359 hdw->freqVal = v;
360 hdw->freqDirty = !0;
361 hdw->freqSlot = 0;
362 return 0;
363 }
364
365 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
366 static int ctrl_hres_max_get(struct pvr2_ctrl *cptr,int *vp)
367 {
368 /* If we're dealing with a 24xxx device, force the horizontal
369 maximum to be 720 no matter what, since we can't get the device
370 to work properly with any other value. Otherwise just return
371 the normal value. */
372 *vp = cptr->info->def.type_int.max_value;
373 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
374 return 0;
375 }
376
377 static int ctrl_hres_min_get(struct pvr2_ctrl *cptr,int *vp)
378 {
379 /* If we're dealing with a 24xxx device, force the horizontal
380 minimum to be 720 no matter what, since we can't get the device
381 to work properly with any other value. Otherwise just return
382 the normal value. */
383 *vp = cptr->info->def.type_int.min_value;
384 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) *vp = 720;
385 return 0;
386 }
387 #endif
388
389 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
390 {
391 return cptr->hdw->enc_stale != 0;
392 }
393
394 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
395 {
396 cptr->hdw->enc_stale = 0;
397 }
398
399 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
400 {
401 int ret;
402 struct v4l2_ext_controls cs;
403 struct v4l2_ext_control c1;
404 memset(&cs,0,sizeof(cs));
405 memset(&c1,0,sizeof(c1));
406 cs.controls = &c1;
407 cs.count = 1;
408 c1.id = cptr->info->v4l_id;
409 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
410 VIDIOC_G_EXT_CTRLS);
411 if (ret) return ret;
412 *vp = c1.value;
413 return 0;
414 }
415
416 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
417 {
418 int ret;
419 struct v4l2_ext_controls cs;
420 struct v4l2_ext_control c1;
421 memset(&cs,0,sizeof(cs));
422 memset(&c1,0,sizeof(c1));
423 cs.controls = &c1;
424 cs.count = 1;
425 c1.id = cptr->info->v4l_id;
426 c1.value = v;
427 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state,&cs,
428 VIDIOC_S_EXT_CTRLS);
429 if (ret) return ret;
430 cptr->hdw->enc_stale = !0;
431 return 0;
432 }
433
434 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
435 {
436 struct v4l2_queryctrl qctrl;
437 struct pvr2_ctl_info *info;
438 qctrl.id = cptr->info->v4l_id;
439 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
440 /* Strip out the const so we can adjust a function pointer. It's
441 OK to do this here because we know this is a dynamically created
442 control, so the underlying storage for the info pointer is (a)
443 private to us, and (b) not in read-only storage. Either we do
444 this or we significantly complicate the underlying control
445 implementation. */
446 info = (struct pvr2_ctl_info *)(cptr->info);
447 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
448 if (info->set_value) {
449 info->set_value = NULL;
450 }
451 } else {
452 if (!(info->set_value)) {
453 info->set_value = ctrl_cx2341x_set;
454 }
455 }
456 return qctrl.flags;
457 }
458
459 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
460 {
461 *vp = cptr->hdw->flag_streaming_enabled;
462 return 0;
463 }
464
465 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
466 {
467 int result = pvr2_hdw_is_hsm(cptr->hdw);
468 *vp = PVR2_CVAL_HSM_FULL;
469 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
470 if (result) *vp = PVR2_CVAL_HSM_HIGH;
471 return 0;
472 }
473
474 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
475 {
476 *vp = cptr->hdw->std_mask_avail;
477 return 0;
478 }
479
480 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
481 {
482 struct pvr2_hdw *hdw = cptr->hdw;
483 v4l2_std_id ns;
484 ns = hdw->std_mask_avail;
485 ns = (ns & ~m) | (v & m);
486 if (ns == hdw->std_mask_avail) return 0;
487 hdw->std_mask_avail = ns;
488 pvr2_hdw_internal_set_std_avail(hdw);
489 pvr2_hdw_internal_find_stdenum(hdw);
490 return 0;
491 }
492
493 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
494 char *bufPtr,unsigned int bufSize,
495 unsigned int *len)
496 {
497 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
498 return 0;
499 }
500
501 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
502 const char *bufPtr,unsigned int bufSize,
503 int *mskp,int *valp)
504 {
505 int ret;
506 v4l2_std_id id;
507 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
508 if (ret < 0) return ret;
509 if (mskp) *mskp = id;
510 if (valp) *valp = id;
511 return 0;
512 }
513
514 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
515 {
516 *vp = cptr->hdw->std_mask_cur;
517 return 0;
518 }
519
520 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
521 {
522 struct pvr2_hdw *hdw = cptr->hdw;
523 v4l2_std_id ns;
524 ns = hdw->std_mask_cur;
525 ns = (ns & ~m) | (v & m);
526 if (ns == hdw->std_mask_cur) return 0;
527 hdw->std_mask_cur = ns;
528 hdw->std_dirty = !0;
529 pvr2_hdw_internal_find_stdenum(hdw);
530 return 0;
531 }
532
533 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
534 {
535 return cptr->hdw->std_dirty != 0;
536 }
537
538 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
539 {
540 cptr->hdw->std_dirty = 0;
541 }
542
543 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
544 {
545 *vp = ((pvr2_hdw_get_signal_status_internal(cptr->hdw) &
546 PVR2_SIGNAL_OK) ? 1 : 0);
547 return 0;
548 }
549
550 static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
551 {
552 *vp = cptr->hdw->subsys_enabled_mask;
553 return 0;
554 }
555
556 static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
557 {
558 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
559 return 0;
560 }
561
562 static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
563 {
564 *vp = cptr->hdw->subsys_stream_mask;
565 return 0;
566 }
567
568 static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
569 {
570 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
571 return 0;
572 }
573
574 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
575 {
576 struct pvr2_hdw *hdw = cptr->hdw;
577 if (v < 0) return -EINVAL;
578 if (v > hdw->std_enum_cnt) return -EINVAL;
579 hdw->std_enum_cur = v;
580 if (!v) return 0;
581 v--;
582 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
583 hdw->std_mask_cur = hdw->std_defs[v].id;
584 hdw->std_dirty = !0;
585 return 0;
586 }
587
588
589 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
590 {
591 *vp = cptr->hdw->std_enum_cur;
592 return 0;
593 }
594
595
596 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
597 {
598 return cptr->hdw->std_dirty != 0;
599 }
600
601
602 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
603 {
604 cptr->hdw->std_dirty = 0;
605 }
606
607
608 #define DEFINT(vmin,vmax) \
609 .type = pvr2_ctl_int, \
610 .def.type_int.min_value = vmin, \
611 .def.type_int.max_value = vmax
612
613 #define DEFENUM(tab) \
614 .type = pvr2_ctl_enum, \
615 .def.type_enum.count = (sizeof(tab)/sizeof((tab)[0])), \
616 .def.type_enum.value_names = tab
617
618 #define DEFBOOL \
619 .type = pvr2_ctl_bool
620
621 #define DEFMASK(msk,tab) \
622 .type = pvr2_ctl_bitmask, \
623 .def.type_bitmask.valid_bits = msk, \
624 .def.type_bitmask.bit_names = tab
625
626 #define DEFREF(vname) \
627 .set_value = ctrl_set_##vname, \
628 .get_value = ctrl_get_##vname, \
629 .is_dirty = ctrl_isdirty_##vname, \
630 .clear_dirty = ctrl_cleardirty_##vname
631
632
633 #define VCREATE_FUNCS(vname) \
634 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
635 {*vp = cptr->hdw->vname##_val; return 0;} \
636 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
637 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
638 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
639 {return cptr->hdw->vname##_dirty != 0;} \
640 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
641 {cptr->hdw->vname##_dirty = 0;}
642
643 VCREATE_FUNCS(brightness)
644 VCREATE_FUNCS(contrast)
645 VCREATE_FUNCS(saturation)
646 VCREATE_FUNCS(hue)
647 VCREATE_FUNCS(volume)
648 VCREATE_FUNCS(balance)
649 VCREATE_FUNCS(bass)
650 VCREATE_FUNCS(treble)
651 VCREATE_FUNCS(mute)
652 VCREATE_FUNCS(input)
653 VCREATE_FUNCS(audiomode)
654 VCREATE_FUNCS(res_hor)
655 VCREATE_FUNCS(res_ver)
656 VCREATE_FUNCS(srate)
657
658 #define MIN_FREQ 55250000L
659 #define MAX_FREQ 850000000L
660
661 /* Table definition of all controls which can be manipulated */
662 static const struct pvr2_ctl_info control_defs[] = {
663 {
664 .v4l_id = V4L2_CID_BRIGHTNESS,
665 .desc = "Brightness",
666 .name = "brightness",
667 .default_value = 128,
668 DEFREF(brightness),
669 DEFINT(0,255),
670 },{
671 .v4l_id = V4L2_CID_CONTRAST,
672 .desc = "Contrast",
673 .name = "contrast",
674 .default_value = 68,
675 DEFREF(contrast),
676 DEFINT(0,127),
677 },{
678 .v4l_id = V4L2_CID_SATURATION,
679 .desc = "Saturation",
680 .name = "saturation",
681 .default_value = 64,
682 DEFREF(saturation),
683 DEFINT(0,127),
684 },{
685 .v4l_id = V4L2_CID_HUE,
686 .desc = "Hue",
687 .name = "hue",
688 .default_value = 0,
689 DEFREF(hue),
690 DEFINT(-128,127),
691 },{
692 .v4l_id = V4L2_CID_AUDIO_VOLUME,
693 .desc = "Volume",
694 .name = "volume",
695 .default_value = 65535,
696 DEFREF(volume),
697 DEFINT(0,65535),
698 },{
699 .v4l_id = V4L2_CID_AUDIO_BALANCE,
700 .desc = "Balance",
701 .name = "balance",
702 .default_value = 0,
703 DEFREF(balance),
704 DEFINT(-32768,32767),
705 },{
706 .v4l_id = V4L2_CID_AUDIO_BASS,
707 .desc = "Bass",
708 .name = "bass",
709 .default_value = 0,
710 DEFREF(bass),
711 DEFINT(-32768,32767),
712 },{
713 .v4l_id = V4L2_CID_AUDIO_TREBLE,
714 .desc = "Treble",
715 .name = "treble",
716 .default_value = 0,
717 DEFREF(treble),
718 DEFINT(-32768,32767),
719 },{
720 .v4l_id = V4L2_CID_AUDIO_MUTE,
721 .desc = "Mute",
722 .name = "mute",
723 .default_value = 0,
724 DEFREF(mute),
725 DEFBOOL,
726 },{
727 .desc = "Video Source",
728 .name = "input",
729 .internal_id = PVR2_CID_INPUT,
730 .default_value = PVR2_CVAL_INPUT_TV,
731 DEFREF(input),
732 DEFENUM(control_values_input),
733 },{
734 .desc = "Audio Mode",
735 .name = "audio_mode",
736 .internal_id = PVR2_CID_AUDIOMODE,
737 .default_value = V4L2_TUNER_MODE_STEREO,
738 DEFREF(audiomode),
739 DEFENUM(control_values_audiomode),
740 },{
741 .desc = "Horizontal capture resolution",
742 .name = "resolution_hor",
743 .internal_id = PVR2_CID_HRES,
744 .default_value = 720,
745 DEFREF(res_hor),
746 DEFINT(320,720),
747 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
748 /* Hook in check for clamp on horizontal resolution in
749 order to avoid unsolved problem involving cx25840. */
750 .get_max_value = ctrl_hres_max_get,
751 .get_min_value = ctrl_hres_min_get,
752 #endif
753 },{
754 .desc = "Vertical capture resolution",
755 .name = "resolution_ver",
756 .internal_id = PVR2_CID_VRES,
757 .default_value = 480,
758 DEFREF(res_ver),
759 DEFINT(200,625),
760 },{
761 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
762 .desc = "Sample rate",
763 .name = "srate",
764 .default_value = PVR2_CVAL_SRATE_48,
765 DEFREF(srate),
766 DEFENUM(control_values_srate),
767 },{
768 .desc = "Tuner Frequency (Hz)",
769 .name = "frequency",
770 .internal_id = PVR2_CID_FREQUENCY,
771 .default_value = 175250000L,
772 .set_value = ctrl_freq_set,
773 .get_value = ctrl_freq_get,
774 .is_dirty = ctrl_freq_is_dirty,
775 .clear_dirty = ctrl_freq_clear_dirty,
776 DEFINT(MIN_FREQ,MAX_FREQ),
777 },{
778 .desc = "Channel",
779 .name = "channel",
780 .set_value = ctrl_channel_set,
781 .get_value = ctrl_channel_get,
782 DEFINT(0,FREQTABLE_SIZE),
783 },{
784 .desc = "Channel Program Frequency",
785 .name = "freq_table_value",
786 .set_value = ctrl_channelfreq_set,
787 .get_value = ctrl_channelfreq_get,
788 DEFINT(MIN_FREQ,MAX_FREQ),
789 },{
790 .desc = "Channel Program ID",
791 .name = "freq_table_channel",
792 .set_value = ctrl_channelprog_set,
793 .get_value = ctrl_channelprog_get,
794 DEFINT(0,FREQTABLE_SIZE),
795 },{
796 .desc = "Streaming Enabled",
797 .name = "streaming_enabled",
798 .get_value = ctrl_streamingenabled_get,
799 DEFBOOL,
800 },{
801 .desc = "USB Speed",
802 .name = "usb_speed",
803 .get_value = ctrl_hsm_get,
804 DEFENUM(control_values_hsm),
805 },{
806 .desc = "Signal Present",
807 .name = "signal_present",
808 .get_value = ctrl_signal_get,
809 DEFBOOL,
810 },{
811 .desc = "Video Standards Available Mask",
812 .name = "video_standard_mask_available",
813 .internal_id = PVR2_CID_STDAVAIL,
814 .skip_init = !0,
815 .get_value = ctrl_stdavail_get,
816 .set_value = ctrl_stdavail_set,
817 .val_to_sym = ctrl_std_val_to_sym,
818 .sym_to_val = ctrl_std_sym_to_val,
819 .type = pvr2_ctl_bitmask,
820 },{
821 .desc = "Video Standards In Use Mask",
822 .name = "video_standard_mask_active",
823 .internal_id = PVR2_CID_STDCUR,
824 .skip_init = !0,
825 .get_value = ctrl_stdcur_get,
826 .set_value = ctrl_stdcur_set,
827 .is_dirty = ctrl_stdcur_is_dirty,
828 .clear_dirty = ctrl_stdcur_clear_dirty,
829 .val_to_sym = ctrl_std_val_to_sym,
830 .sym_to_val = ctrl_std_sym_to_val,
831 .type = pvr2_ctl_bitmask,
832 },{
833 .desc = "Subsystem enabled mask",
834 .name = "debug_subsys_mask",
835 .skip_init = !0,
836 .get_value = ctrl_subsys_get,
837 .set_value = ctrl_subsys_set,
838 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
839 },{
840 .desc = "Subsystem stream mask",
841 .name = "debug_subsys_stream_mask",
842 .skip_init = !0,
843 .get_value = ctrl_subsys_stream_get,
844 .set_value = ctrl_subsys_stream_set,
845 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
846 },{
847 .desc = "Video Standard Name",
848 .name = "video_standard",
849 .internal_id = PVR2_CID_STDENUM,
850 .skip_init = !0,
851 .get_value = ctrl_stdenumcur_get,
852 .set_value = ctrl_stdenumcur_set,
853 .is_dirty = ctrl_stdenumcur_is_dirty,
854 .clear_dirty = ctrl_stdenumcur_clear_dirty,
855 .type = pvr2_ctl_enum,
856 }
857 };
858
859 #define CTRLDEF_COUNT (sizeof(control_defs)/sizeof(control_defs[0]))
860
861
862 const char *pvr2_config_get_name(enum pvr2_config cfg)
863 {
864 switch (cfg) {
865 case pvr2_config_empty: return "empty";
866 case pvr2_config_mpeg: return "mpeg";
867 case pvr2_config_vbi: return "vbi";
868 case pvr2_config_radio: return "radio";
869 }
870 return "<unknown>";
871 }
872
873
874 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
875 {
876 return hdw->usb_dev;
877 }
878
879
880 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
881 {
882 return hdw->serial_number;
883 }
884
885 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
886 {
887 return hdw->unit_number;
888 }
889
890
891 /* Attempt to locate one of the given set of files. Messages are logged
892 appropriate to what has been found. The return value will be 0 or
893 greater on success (it will be the index of the file name found) and
894 fw_entry will be filled in. Otherwise a negative error is returned on
895 failure. If the return value is -ENOENT then no viable firmware file
896 could be located. */
897 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
898 const struct firmware **fw_entry,
899 const char *fwtypename,
900 unsigned int fwcount,
901 const char *fwnames[])
902 {
903 unsigned int idx;
904 int ret = -EINVAL;
905 for (idx = 0; idx < fwcount; idx++) {
906 ret = request_firmware(fw_entry,
907 fwnames[idx],
908 &hdw->usb_dev->dev);
909 if (!ret) {
910 trace_firmware("Located %s firmware: %s;"
911 " uploading...",
912 fwtypename,
913 fwnames[idx]);
914 return idx;
915 }
916 if (ret == -ENOENT) continue;
917 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
918 "request_firmware fatal error with code=%d",ret);
919 return ret;
920 }
921 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
922 "***WARNING***"
923 " Device %s firmware"
924 " seems to be missing.",
925 fwtypename);
926 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
927 "Did you install the pvrusb2 firmware files"
928 " in their proper location?");
929 if (fwcount == 1) {
930 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
931 "request_firmware unable to locate %s file %s",
932 fwtypename,fwnames[0]);
933 } else {
934 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
935 "request_firmware unable to locate"
936 " one of the following %s files:",
937 fwtypename);
938 for (idx = 0; idx < fwcount; idx++) {
939 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
940 "request_firmware: Failed to find %s",
941 fwnames[idx]);
942 }
943 }
944 return ret;
945 }
946
947
948 /*
949 * pvr2_upload_firmware1().
950 *
951 * Send the 8051 firmware to the device. After the upload, arrange for
952 * device to re-enumerate.
953 *
954 * NOTE : the pointer to the firmware data given by request_firmware()
955 * is not suitable for an usb transaction.
956 *
957 */
958 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
959 {
960 const struct firmware *fw_entry = NULL;
961 void *fw_ptr;
962 unsigned int pipe;
963 int ret;
964 u16 address;
965 static const char *fw_files_29xxx[] = {
966 "v4l-pvrusb2-29xxx-01.fw",
967 };
968 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
969 static const char *fw_files_24xxx[] = {
970 "v4l-pvrusb2-24xxx-01.fw",
971 };
972 #endif
973 static const struct pvr2_string_table fw_file_defs[] = {
974 [PVR2_HDW_TYPE_29XXX] = {
975 fw_files_29xxx,
976 sizeof(fw_files_29xxx)/sizeof(fw_files_29xxx[0]),
977 },
978 #ifdef CONFIG_VIDEO_PVRUSB2_24XXX
979 [PVR2_HDW_TYPE_24XXX] = {
980 fw_files_24xxx,
981 sizeof(fw_files_24xxx)/sizeof(fw_files_24xxx[0]),
982 },
983 #endif
984 };
985 hdw->fw1_state = FW1_STATE_FAILED; // default result
986
987 trace_firmware("pvr2_upload_firmware1");
988
989 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
990 fw_file_defs[hdw->hdw_type].cnt,
991 fw_file_defs[hdw->hdw_type].lst);
992 if (ret < 0) {
993 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
994 return ret;
995 }
996
997 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
998 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
999
1000 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1001
1002 if (fw_entry->size != 0x2000){
1003 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1004 release_firmware(fw_entry);
1005 return -ENOMEM;
1006 }
1007
1008 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1009 if (fw_ptr == NULL){
1010 release_firmware(fw_entry);
1011 return -ENOMEM;
1012 }
1013
1014 /* We have to hold the CPU during firmware upload. */
1015 pvr2_hdw_cpureset_assert(hdw,1);
1016
1017 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1018 chunk. */
1019
1020 ret = 0;
1021 for(address = 0; address < fw_entry->size; address += 0x800) {
1022 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1023 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1024 0, fw_ptr, 0x800, HZ);
1025 }
1026
1027 trace_firmware("Upload done, releasing device's CPU");
1028
1029 /* Now release the CPU. It will disconnect and reconnect later. */
1030 pvr2_hdw_cpureset_assert(hdw,0);
1031
1032 kfree(fw_ptr);
1033 release_firmware(fw_entry);
1034
1035 trace_firmware("Upload done (%d bytes sent)",ret);
1036
1037 /* We should have written 8192 bytes */
1038 if (ret == 8192) {
1039 hdw->fw1_state = FW1_STATE_RELOAD;
1040 return 0;
1041 }
1042
1043 return -EIO;
1044 }
1045
1046
1047 /*
1048 * pvr2_upload_firmware2()
1049 *
1050 * This uploads encoder firmware on endpoint 2.
1051 *
1052 */
1053
1054 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1055 {
1056 const struct firmware *fw_entry = NULL;
1057 void *fw_ptr;
1058 unsigned int pipe, fw_len, fw_done;
1059 int actual_length;
1060 int ret = 0;
1061 int fwidx;
1062 static const char *fw_files[] = {
1063 CX2341X_FIRM_ENC_FILENAME,
1064 };
1065
1066 trace_firmware("pvr2_upload_firmware2");
1067
1068 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1069 sizeof(fw_files)/sizeof(fw_files[0]),
1070 fw_files);
1071 if (ret < 0) return ret;
1072 fwidx = ret;
1073 ret = 0;
1074 /* Since we're about to completely reinitialize the encoder,
1075 invalidate our cached copy of its configuration state. Next
1076 time we configure the encoder, then we'll fully configure it. */
1077 hdw->enc_cur_valid = 0;
1078
1079 /* First prepare firmware loading */
1080 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1081 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1082 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1083 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1084 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1085 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1086 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1087 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1088 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1089 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1090 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1091 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1092 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1093 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1094 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1095 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1096 ret |= pvr2_write_u8(hdw, 0x52, 0);
1097 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1098
1099 if (ret) {
1100 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1101 "firmware2 upload prep failed, ret=%d",ret);
1102 release_firmware(fw_entry);
1103 return ret;
1104 }
1105
1106 /* Now send firmware */
1107
1108 fw_len = fw_entry->size;
1109
1110 if (fw_len % FIRMWARE_CHUNK_SIZE) {
1111 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1112 "size of %s firmware"
1113 " must be a multiple of 8192B",
1114 fw_files[fwidx]);
1115 release_firmware(fw_entry);
1116 return -1;
1117 }
1118
1119 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1120 if (fw_ptr == NULL){
1121 release_firmware(fw_entry);
1122 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1123 "failed to allocate memory for firmware2 upload");
1124 return -ENOMEM;
1125 }
1126
1127 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1128
1129 for (fw_done = 0 ; (fw_done < fw_len) && !ret ;
1130 fw_done += FIRMWARE_CHUNK_SIZE ) {
1131 int i;
1132 memcpy(fw_ptr, fw_entry->data + fw_done, FIRMWARE_CHUNK_SIZE);
1133 /* Usbsnoop log shows that we must swap bytes... */
1134 for (i = 0; i < FIRMWARE_CHUNK_SIZE/4 ; i++)
1135 ((u32 *)fw_ptr)[i] = ___swab32(((u32 *)fw_ptr)[i]);
1136
1137 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,
1138 FIRMWARE_CHUNK_SIZE,
1139 &actual_length, HZ);
1140 ret |= (actual_length != FIRMWARE_CHUNK_SIZE);
1141 }
1142
1143 trace_firmware("upload of %s : %i / %i ",
1144 fw_files[fwidx],fw_done,fw_len);
1145
1146 kfree(fw_ptr);
1147 release_firmware(fw_entry);
1148
1149 if (ret) {
1150 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1151 "firmware2 upload transfer failure");
1152 return ret;
1153 }
1154
1155 /* Finish upload */
1156
1157 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1158 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1159 ret |= pvr2_write_u16(hdw, 0x0600, 0);
1160
1161 if (ret) {
1162 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1163 "firmware2 upload post-proc failure");
1164 } else {
1165 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1166 }
1167 return ret;
1168 }
1169
1170
1171 #define FIRMWARE_RECOVERY_BITS \
1172 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1173 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1174 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1175 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1176
1177 /*
1178
1179 This single function is key to pretty much everything. The pvrusb2
1180 device can logically be viewed as a series of subsystems which can be
1181 stopped / started or unconfigured / configured. To get things streaming,
1182 one must configure everything and start everything, but there may be
1183 various reasons over time to deconfigure something or stop something.
1184 This function handles all of this activity. Everything EVERYWHERE that
1185 must affect a subsystem eventually comes here to do the work.
1186
1187 The current state of all subsystems is represented by a single bit mask,
1188 known as subsys_enabled_mask. The bit positions are defined by the
1189 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1190 time the set of configured or active subsystems can be queried just by
1191 looking at that mask. To change bits in that mask, this function here
1192 must be called. The "msk" argument indicates which bit positions to
1193 change, and the "val" argument defines the new values for the positions
1194 defined by "msk".
1195
1196 There is a priority ordering of starting / stopping things, and for
1197 multiple requested changes, this function implements that ordering.
1198 (Thus we will act on a request to load encoder firmware before we
1199 configure the encoder.) In addition to priority ordering, there is a
1200 recovery strategy implemented here. If a particular step fails and we
1201 detect that failure, this function will clear the affected subsystem bits
1202 and restart. Thus we have a means for recovering from a dead encoder:
1203 Clear all bits that correspond to subsystems that we need to restart /
1204 reconfigure and start over.
1205
1206 */
1207 static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1208 unsigned long msk,
1209 unsigned long val)
1210 {
1211 unsigned long nmsk;
1212 unsigned long vmsk;
1213 int ret;
1214 unsigned int tryCount = 0;
1215
1216 if (!hdw->flag_ok) return;
1217
1218 msk &= PVR2_SUBSYS_ALL;
1219 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1220 nmsk &= PVR2_SUBSYS_ALL;
1221
1222 for (;;) {
1223 tryCount++;
1224 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1225 PVR2_SUBSYS_ALL)) break;
1226 if (tryCount > 4) {
1227 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1228 "Too many retries when configuring device;"
1229 " giving up");
1230 pvr2_hdw_render_useless(hdw);
1231 break;
1232 }
1233 if (tryCount > 1) {
1234 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1235 "Retrying device reconfiguration");
1236 }
1237 pvr2_trace(PVR2_TRACE_INIT,
1238 "subsys mask changing 0x%lx:0x%lx"
1239 " from 0x%lx to 0x%lx",
1240 msk,val,hdw->subsys_enabled_mask,nmsk);
1241
1242 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1243 hdw->subsys_enabled_mask;
1244 if (vmsk) {
1245 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1246 pvr2_trace(PVR2_TRACE_CTL,
1247 "/*---TRACE_CTL----*/"
1248 " pvr2_encoder_stop");
1249 ret = pvr2_encoder_stop(hdw);
1250 if (ret) {
1251 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1252 "Error recovery initiated");
1253 hdw->subsys_enabled_mask &=
1254 ~FIRMWARE_RECOVERY_BITS;
1255 continue;
1256 }
1257 }
1258 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1259 pvr2_trace(PVR2_TRACE_CTL,
1260 "/*---TRACE_CTL----*/"
1261 " pvr2_hdw_cmd_usbstream(0)");
1262 pvr2_hdw_cmd_usbstream(hdw,0);
1263 }
1264 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1265 pvr2_trace(PVR2_TRACE_CTL,
1266 "/*---TRACE_CTL----*/"
1267 " decoder disable");
1268 if (hdw->decoder_ctrl) {
1269 hdw->decoder_ctrl->enable(
1270 hdw->decoder_ctrl->ctxt,0);
1271 } else {
1272 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1273 "WARNING:"
1274 " No decoder present");
1275 }
1276 hdw->subsys_enabled_mask &=
1277 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1278 }
1279 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1280 hdw->subsys_enabled_mask &=
1281 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1282 }
1283 }
1284 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1285 if (vmsk) {
1286 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1287 pvr2_trace(PVR2_TRACE_CTL,
1288 "/*---TRACE_CTL----*/"
1289 " pvr2_upload_firmware2");
1290 ret = pvr2_upload_firmware2(hdw);
1291 if (ret) {
1292 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1293 "Failure uploading encoder"
1294 " firmware");
1295 pvr2_hdw_render_useless(hdw);
1296 break;
1297 }
1298 }
1299 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1300 pvr2_trace(PVR2_TRACE_CTL,
1301 "/*---TRACE_CTL----*/"
1302 " pvr2_encoder_configure");
1303 ret = pvr2_encoder_configure(hdw);
1304 if (ret) {
1305 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1306 "Error recovery initiated");
1307 hdw->subsys_enabled_mask &=
1308 ~FIRMWARE_RECOVERY_BITS;
1309 continue;
1310 }
1311 }
1312 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1313 pvr2_trace(PVR2_TRACE_CTL,
1314 "/*---TRACE_CTL----*/"
1315 " decoder enable");
1316 if (hdw->decoder_ctrl) {
1317 hdw->decoder_ctrl->enable(
1318 hdw->decoder_ctrl->ctxt,!0);
1319 } else {
1320 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1321 "WARNING:"
1322 " No decoder present");
1323 }
1324 hdw->subsys_enabled_mask |=
1325 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1326 }
1327 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1328 pvr2_trace(PVR2_TRACE_CTL,
1329 "/*---TRACE_CTL----*/"
1330 " pvr2_hdw_cmd_usbstream(1)");
1331 pvr2_hdw_cmd_usbstream(hdw,!0);
1332 }
1333 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1334 pvr2_trace(PVR2_TRACE_CTL,
1335 "/*---TRACE_CTL----*/"
1336 " pvr2_encoder_start");
1337 ret = pvr2_encoder_start(hdw);
1338 if (ret) {
1339 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1340 "Error recovery initiated");
1341 hdw->subsys_enabled_mask &=
1342 ~FIRMWARE_RECOVERY_BITS;
1343 continue;
1344 }
1345 }
1346 }
1347 }
1348 }
1349
1350
1351 void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1352 unsigned long msk,unsigned long val)
1353 {
1354 LOCK_TAKE(hdw->big_lock); do {
1355 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1356 } while (0); LOCK_GIVE(hdw->big_lock);
1357 }
1358
1359
1360 unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1361 {
1362 return hdw->subsys_enabled_mask;
1363 }
1364
1365
1366 unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1367 {
1368 return hdw->subsys_stream_mask;
1369 }
1370
1371
1372 static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1373 unsigned long msk,
1374 unsigned long val)
1375 {
1376 unsigned long val2;
1377 msk &= PVR2_SUBSYS_ALL;
1378 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1379 pvr2_trace(PVR2_TRACE_INIT,
1380 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1381 msk,val,hdw->subsys_stream_mask,val2);
1382 hdw->subsys_stream_mask = val2;
1383 }
1384
1385
1386 void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1387 unsigned long msk,
1388 unsigned long val)
1389 {
1390 LOCK_TAKE(hdw->big_lock); do {
1391 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1392 } while (0); LOCK_GIVE(hdw->big_lock);
1393 }
1394
1395
1396 static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
1397 {
1398 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1399 if (enableFl) {
1400 pvr2_trace(PVR2_TRACE_START_STOP,
1401 "/*--TRACE_STREAM--*/ enable");
1402 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1403 } else {
1404 pvr2_trace(PVR2_TRACE_START_STOP,
1405 "/*--TRACE_STREAM--*/ disable");
1406 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1407 }
1408 if (!hdw->flag_ok) return -EIO;
1409 hdw->flag_streaming_enabled = enableFl != 0;
1410 return 0;
1411 }
1412
1413
1414 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1415 {
1416 return hdw->flag_streaming_enabled != 0;
1417 }
1418
1419
1420 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1421 {
1422 int ret;
1423 LOCK_TAKE(hdw->big_lock); do {
1424 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1425 } while (0); LOCK_GIVE(hdw->big_lock);
1426 return ret;
1427 }
1428
1429
1430 static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1431 enum pvr2_config config)
1432 {
1433 unsigned long sm = hdw->subsys_enabled_mask;
1434 if (!hdw->flag_ok) return -EIO;
1435 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1436 hdw->config = config;
1437 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1438 return 0;
1439 }
1440
1441
1442 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1443 {
1444 int ret;
1445 if (!hdw->flag_ok) return -EIO;
1446 LOCK_TAKE(hdw->big_lock);
1447 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1448 LOCK_GIVE(hdw->big_lock);
1449 return ret;
1450 }
1451
1452
1453 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1454 {
1455 int unit_number = hdw->unit_number;
1456 int tp = -1;
1457 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1458 tp = tuner[unit_number];
1459 }
1460 if (tp < 0) return -EINVAL;
1461 hdw->tuner_type = tp;
1462 return 0;
1463 }
1464
1465
1466 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1467 {
1468 int unit_number = hdw->unit_number;
1469 int tp = 0;
1470 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1471 tp = video_std[unit_number];
1472 }
1473 return tp;
1474 }
1475
1476
1477 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1478 {
1479 int unit_number = hdw->unit_number;
1480 int tp = 0;
1481 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1482 tp = tolerance[unit_number];
1483 }
1484 return tp;
1485 }
1486
1487
1488 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1489 {
1490 /* Try a harmless request to fetch the eeprom's address over
1491 endpoint 1. See what happens. Only the full FX2 image can
1492 respond to this. If this probe fails then likely the FX2
1493 firmware needs be loaded. */
1494 int result;
1495 LOCK_TAKE(hdw->ctl_lock); do {
1496 hdw->cmd_buffer[0] = 0xeb;
1497 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1498 hdw->cmd_buffer,1,
1499 hdw->cmd_buffer,1);
1500 if (result < 0) break;
1501 } while(0); LOCK_GIVE(hdw->ctl_lock);
1502 if (result) {
1503 pvr2_trace(PVR2_TRACE_INIT,
1504 "Probe of device endpoint 1 result status %d",
1505 result);
1506 } else {
1507 pvr2_trace(PVR2_TRACE_INIT,
1508 "Probe of device endpoint 1 succeeded");
1509 }
1510 return result == 0;
1511 }
1512
1513 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1514 {
1515 char buf[40];
1516 unsigned int bcnt;
1517 v4l2_std_id std1,std2;
1518
1519 std1 = get_default_standard(hdw);
1520
1521 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1522 pvr2_trace(PVR2_TRACE_INIT,
1523 "Supported video standard(s) reported by eeprom: %.*s",
1524 bcnt,buf);
1525
1526 hdw->std_mask_avail = hdw->std_mask_eeprom;
1527
1528 std2 = std1 & ~hdw->std_mask_avail;
1529 if (std2) {
1530 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1531 pvr2_trace(PVR2_TRACE_INIT,
1532 "Expanding supported video standards"
1533 " to include: %.*s",
1534 bcnt,buf);
1535 hdw->std_mask_avail |= std2;
1536 }
1537
1538 pvr2_hdw_internal_set_std_avail(hdw);
1539
1540 if (std1) {
1541 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1542 pvr2_trace(PVR2_TRACE_INIT,
1543 "Initial video standard forced to %.*s",
1544 bcnt,buf);
1545 hdw->std_mask_cur = std1;
1546 hdw->std_dirty = !0;
1547 pvr2_hdw_internal_find_stdenum(hdw);
1548 return;
1549 }
1550
1551 if (hdw->std_enum_cnt > 1) {
1552 // Autoselect the first listed standard
1553 hdw->std_enum_cur = 1;
1554 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1555 hdw->std_dirty = !0;
1556 pvr2_trace(PVR2_TRACE_INIT,
1557 "Initial video standard auto-selected to %s",
1558 hdw->std_defs[hdw->std_enum_cur-1].name);
1559 return;
1560 }
1561
1562 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1563 "Unable to select a viable initial video standard");
1564 }
1565
1566
1567 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1568 {
1569 int ret;
1570 unsigned int idx;
1571 struct pvr2_ctrl *cptr;
1572 int reloadFl = 0;
1573 if (!reloadFl) {
1574 reloadFl = (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1575 == 0);
1576 if (reloadFl) {
1577 pvr2_trace(PVR2_TRACE_INIT,
1578 "USB endpoint config looks strange"
1579 "; possibly firmware needs to be loaded");
1580 }
1581 }
1582 if (!reloadFl) {
1583 reloadFl = !pvr2_hdw_check_firmware(hdw);
1584 if (reloadFl) {
1585 pvr2_trace(PVR2_TRACE_INIT,
1586 "Check for FX2 firmware failed"
1587 "; possibly firmware needs to be loaded");
1588 }
1589 }
1590 if (reloadFl) {
1591 if (pvr2_upload_firmware1(hdw) != 0) {
1592 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1593 "Failure uploading firmware1");
1594 }
1595 return;
1596 }
1597 hdw->fw1_state = FW1_STATE_OK;
1598
1599 if (initusbreset) {
1600 pvr2_hdw_device_reset(hdw);
1601 }
1602 if (!pvr2_hdw_dev_ok(hdw)) return;
1603
1604 for (idx = 0; idx < pvr2_client_lists[hdw->hdw_type].cnt; idx++) {
1605 request_module(pvr2_client_lists[hdw->hdw_type].lst[idx]);
1606 }
1607
1608 pvr2_hdw_cmd_powerup(hdw);
1609 if (!pvr2_hdw_dev_ok(hdw)) return;
1610
1611 if (pvr2_upload_firmware2(hdw)){
1612 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1613 pvr2_hdw_render_useless(hdw);
1614 return;
1615 }
1616
1617 // This step MUST happen after the earlier powerup step.
1618 pvr2_i2c_core_init(hdw);
1619 if (!pvr2_hdw_dev_ok(hdw)) return;
1620
1621 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1622 cptr = hdw->controls + idx;
1623 if (cptr->info->skip_init) continue;
1624 if (!cptr->info->set_value) continue;
1625 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1626 }
1627
1628 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1629 // thread-safe against the normal pvr2_send_request() mechanism.
1630 // (We should make it thread safe).
1631
1632 ret = pvr2_hdw_get_eeprom_addr(hdw);
1633 if (!pvr2_hdw_dev_ok(hdw)) return;
1634 if (ret < 0) {
1635 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1636 "Unable to determine location of eeprom, skipping");
1637 } else {
1638 hdw->eeprom_addr = ret;
1639 pvr2_eeprom_analyze(hdw);
1640 if (!pvr2_hdw_dev_ok(hdw)) return;
1641 }
1642
1643 pvr2_hdw_setup_std(hdw);
1644
1645 if (!get_default_tuner_type(hdw)) {
1646 pvr2_trace(PVR2_TRACE_INIT,
1647 "pvr2_hdw_setup: Tuner type overridden to %d",
1648 hdw->tuner_type);
1649 }
1650
1651 hdw->tuner_updated = !0;
1652 pvr2_i2c_core_check_stale(hdw);
1653 hdw->tuner_updated = 0;
1654
1655 if (!pvr2_hdw_dev_ok(hdw)) return;
1656
1657 pvr2_hdw_commit_ctl_internal(hdw);
1658 if (!pvr2_hdw_dev_ok(hdw)) return;
1659
1660 hdw->vid_stream = pvr2_stream_create();
1661 if (!pvr2_hdw_dev_ok(hdw)) return;
1662 pvr2_trace(PVR2_TRACE_INIT,
1663 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1664 if (hdw->vid_stream) {
1665 idx = get_default_error_tolerance(hdw);
1666 if (idx) {
1667 pvr2_trace(PVR2_TRACE_INIT,
1668 "pvr2_hdw_setup: video stream %p"
1669 " setting tolerance %u",
1670 hdw->vid_stream,idx);
1671 }
1672 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1673 PVR2_VID_ENDPOINT,idx);
1674 }
1675
1676 if (!pvr2_hdw_dev_ok(hdw)) return;
1677
1678 /* Make sure everything is up to date */
1679 pvr2_i2c_core_sync(hdw);
1680
1681 if (!pvr2_hdw_dev_ok(hdw)) return;
1682
1683 hdw->flag_init_ok = !0;
1684 }
1685
1686
1687 int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1688 {
1689 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1690 LOCK_TAKE(hdw->big_lock); do {
1691 pvr2_hdw_setup_low(hdw);
1692 pvr2_trace(PVR2_TRACE_INIT,
1693 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1694 hdw,hdw->flag_ok,hdw->flag_init_ok);
1695 if (pvr2_hdw_dev_ok(hdw)) {
1696 if (pvr2_hdw_init_ok(hdw)) {
1697 pvr2_trace(
1698 PVR2_TRACE_INFO,
1699 "Device initialization"
1700 " completed successfully.");
1701 break;
1702 }
1703 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1704 pvr2_trace(
1705 PVR2_TRACE_INFO,
1706 "Device microcontroller firmware"
1707 " (re)loaded; it should now reset"
1708 " and reconnect.");
1709 break;
1710 }
1711 pvr2_trace(
1712 PVR2_TRACE_ERROR_LEGS,
1713 "Device initialization was not successful.");
1714 if (hdw->fw1_state == FW1_STATE_MISSING) {
1715 pvr2_trace(
1716 PVR2_TRACE_ERROR_LEGS,
1717 "Giving up since device"
1718 " microcontroller firmware"
1719 " appears to be missing.");
1720 break;
1721 }
1722 }
1723 if (procreload) {
1724 pvr2_trace(
1725 PVR2_TRACE_ERROR_LEGS,
1726 "Attempting pvrusb2 recovery by reloading"
1727 " primary firmware.");
1728 pvr2_trace(
1729 PVR2_TRACE_ERROR_LEGS,
1730 "If this works, device should disconnect"
1731 " and reconnect in a sane state.");
1732 hdw->fw1_state = FW1_STATE_UNKNOWN;
1733 pvr2_upload_firmware1(hdw);
1734 } else {
1735 pvr2_trace(
1736 PVR2_TRACE_ERROR_LEGS,
1737 "***WARNING*** pvrusb2 device hardware"
1738 " appears to be jammed"
1739 " and I can't clear it.");
1740 pvr2_trace(
1741 PVR2_TRACE_ERROR_LEGS,
1742 "You might need to power cycle"
1743 " the pvrusb2 device"
1744 " in order to recover.");
1745 }
1746 } while (0); LOCK_GIVE(hdw->big_lock);
1747 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1748 return hdw->flag_init_ok;
1749 }
1750
1751
1752 /* Create and return a structure for interacting with the underlying
1753 hardware */
1754 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1755 const struct usb_device_id *devid)
1756 {
1757 unsigned int idx,cnt1,cnt2;
1758 struct pvr2_hdw *hdw;
1759 unsigned int hdw_type;
1760 int valid_std_mask;
1761 struct pvr2_ctrl *cptr;
1762 __u8 ifnum;
1763 struct v4l2_queryctrl qctrl;
1764 struct pvr2_ctl_info *ciptr;
1765
1766 hdw_type = devid - pvr2_device_table;
1767 if (hdw_type >=
1768 sizeof(pvr2_device_names)/sizeof(pvr2_device_names[0])) {
1769 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1770 "Bogus device type of %u reported",hdw_type);
1771 return NULL;
1772 }
1773
1774 hdw = kmalloc(sizeof(*hdw),GFP_KERNEL);
1775 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1776 hdw,pvr2_device_names[hdw_type]);
1777 if (!hdw) goto fail;
1778 memset(hdw,0,sizeof(*hdw));
1779 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1780
1781 hdw->control_cnt = CTRLDEF_COUNT;
1782 hdw->control_cnt += MPEGDEF_COUNT;
1783 hdw->controls = kmalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1784 GFP_KERNEL);
1785 if (!hdw->controls) goto fail;
1786 memset(hdw->controls,0,sizeof(struct pvr2_ctrl) * hdw->control_cnt);
1787 hdw->hdw_type = hdw_type;
1788 for (idx = 0; idx < hdw->control_cnt; idx++) {
1789 cptr = hdw->controls + idx;
1790 cptr->hdw = hdw;
1791 }
1792 for (idx = 0; idx < 32; idx++) {
1793 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1794 }
1795 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1796 cptr = hdw->controls + idx;
1797 cptr->info = control_defs+idx;
1798 }
1799 /* Define and configure additional controls from cx2341x module. */
1800 hdw->mpeg_ctrl_info = kmalloc(
1801 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1802 if (!hdw->mpeg_ctrl_info) goto fail;
1803 memset(hdw->mpeg_ctrl_info,0,
1804 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT);
1805 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1806 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1807 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1808 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1809 ciptr->name = mpeg_ids[idx].strid;
1810 ciptr->v4l_id = mpeg_ids[idx].id;
1811 ciptr->skip_init = !0;
1812 ciptr->get_value = ctrl_cx2341x_get;
1813 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1814 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1815 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1816 qctrl.id = ciptr->v4l_id;
1817 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1818 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1819 ciptr->set_value = ctrl_cx2341x_set;
1820 }
1821 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1822 PVR2_CTLD_INFO_DESC_SIZE);
1823 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1824 ciptr->default_value = qctrl.default_value;
1825 switch (qctrl.type) {
1826 default:
1827 case V4L2_CTRL_TYPE_INTEGER:
1828 ciptr->type = pvr2_ctl_int;
1829 ciptr->def.type_int.min_value = qctrl.minimum;
1830 ciptr->def.type_int.max_value = qctrl.maximum;
1831 break;
1832 case V4L2_CTRL_TYPE_BOOLEAN:
1833 ciptr->type = pvr2_ctl_bool;
1834 break;
1835 case V4L2_CTRL_TYPE_MENU:
1836 ciptr->type = pvr2_ctl_enum;
1837 ciptr->def.type_enum.value_names =
1838 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1839 for (cnt1 = 0;
1840 ciptr->def.type_enum.value_names[cnt1] != NULL;
1841 cnt1++) { }
1842 ciptr->def.type_enum.count = cnt1;
1843 break;
1844 }
1845 cptr->info = ciptr;
1846 }
1847
1848 // Initialize video standard enum dynamic control
1849 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1850 if (cptr) {
1851 memcpy(&hdw->std_info_enum,cptr->info,
1852 sizeof(hdw->std_info_enum));
1853 cptr->info = &hdw->std_info_enum;
1854
1855 }
1856 // Initialize control data regarding video standard masks
1857 valid_std_mask = pvr2_std_get_usable();
1858 for (idx = 0; idx < 32; idx++) {
1859 if (!(valid_std_mask & (1 << idx))) continue;
1860 cnt1 = pvr2_std_id_to_str(
1861 hdw->std_mask_names[idx],
1862 sizeof(hdw->std_mask_names[idx])-1,
1863 1 << idx);
1864 hdw->std_mask_names[idx][cnt1] = 0;
1865 }
1866 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1867 if (cptr) {
1868 memcpy(&hdw->std_info_avail,cptr->info,
1869 sizeof(hdw->std_info_avail));
1870 cptr->info = &hdw->std_info_avail;
1871 hdw->std_info_avail.def.type_bitmask.bit_names =
1872 hdw->std_mask_ptrs;
1873 hdw->std_info_avail.def.type_bitmask.valid_bits =
1874 valid_std_mask;
1875 }
1876 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1877 if (cptr) {
1878 memcpy(&hdw->std_info_cur,cptr->info,
1879 sizeof(hdw->std_info_cur));
1880 cptr->info = &hdw->std_info_cur;
1881 hdw->std_info_cur.def.type_bitmask.bit_names =
1882 hdw->std_mask_ptrs;
1883 hdw->std_info_avail.def.type_bitmask.valid_bits =
1884 valid_std_mask;
1885 }
1886
1887 hdw->eeprom_addr = -1;
1888 hdw->unit_number = -1;
1889 hdw->v4l_minor_number = -1;
1890 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1891 if (!hdw->ctl_write_buffer) goto fail;
1892 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1893 if (!hdw->ctl_read_buffer) goto fail;
1894 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1895 if (!hdw->ctl_write_urb) goto fail;
1896 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1897 if (!hdw->ctl_read_urb) goto fail;
1898
1899 down(&pvr2_unit_sem); do {
1900 for (idx = 0; idx < PVR_NUM; idx++) {
1901 if (unit_pointers[idx]) continue;
1902 hdw->unit_number = idx;
1903 unit_pointers[idx] = hdw;
1904 break;
1905 }
1906 } while (0); up(&pvr2_unit_sem);
1907
1908 cnt1 = 0;
1909 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1910 cnt1 += cnt2;
1911 if (hdw->unit_number >= 0) {
1912 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1913 ('a' + hdw->unit_number));
1914 cnt1 += cnt2;
1915 }
1916 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1917 hdw->name[cnt1] = 0;
1918
1919 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1920 hdw->unit_number,hdw->name);
1921
1922 hdw->tuner_type = -1;
1923 hdw->flag_ok = !0;
1924 /* Initialize the mask of subsystems that we will shut down when we
1925 stop streaming. */
1926 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
1927 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
1928
1929 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
1930 hdw->subsys_stream_mask);
1931
1932 hdw->usb_intf = intf;
1933 hdw->usb_dev = interface_to_usbdev(intf);
1934
1935 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
1936 usb_set_interface(hdw->usb_dev,ifnum,0);
1937
1938 mutex_init(&hdw->ctl_lock_mutex);
1939 mutex_init(&hdw->big_lock_mutex);
1940
1941 return hdw;
1942 fail:
1943 if (hdw) {
1944 if (hdw->ctl_read_urb) usb_free_urb(hdw->ctl_read_urb);
1945 if (hdw->ctl_write_urb) usb_free_urb(hdw->ctl_write_urb);
1946 if (hdw->ctl_read_buffer) kfree(hdw->ctl_read_buffer);
1947 if (hdw->ctl_write_buffer) kfree(hdw->ctl_write_buffer);
1948 if (hdw->controls) kfree(hdw->controls);
1949 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
1950 kfree(hdw);
1951 }
1952 return NULL;
1953 }
1954
1955
1956 /* Remove _all_ associations between this driver and the underlying USB
1957 layer. */
1958 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
1959 {
1960 if (hdw->flag_disconnected) return;
1961 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
1962 if (hdw->ctl_read_urb) {
1963 usb_kill_urb(hdw->ctl_read_urb);
1964 usb_free_urb(hdw->ctl_read_urb);
1965 hdw->ctl_read_urb = NULL;
1966 }
1967 if (hdw->ctl_write_urb) {
1968 usb_kill_urb(hdw->ctl_write_urb);
1969 usb_free_urb(hdw->ctl_write_urb);
1970 hdw->ctl_write_urb = NULL;
1971 }
1972 if (hdw->ctl_read_buffer) {
1973 kfree(hdw->ctl_read_buffer);
1974 hdw->ctl_read_buffer = NULL;
1975 }
1976 if (hdw->ctl_write_buffer) {
1977 kfree(hdw->ctl_write_buffer);
1978 hdw->ctl_write_buffer = NULL;
1979 }
1980 pvr2_hdw_render_useless_unlocked(hdw);
1981 hdw->flag_disconnected = !0;
1982 hdw->usb_dev = NULL;
1983 hdw->usb_intf = NULL;
1984 }
1985
1986
1987 /* Destroy hardware interaction structure */
1988 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
1989 {
1990 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
1991 if (hdw->fw_buffer) {
1992 kfree(hdw->fw_buffer);
1993 hdw->fw_buffer = NULL;
1994 }
1995 if (hdw->vid_stream) {
1996 pvr2_stream_destroy(hdw->vid_stream);
1997 hdw->vid_stream = NULL;
1998 }
1999 if (hdw->audio_stat) {
2000 hdw->audio_stat->detach(hdw->audio_stat->ctxt);
2001 }
2002 if (hdw->decoder_ctrl) {
2003 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2004 }
2005 pvr2_i2c_core_done(hdw);
2006 pvr2_hdw_remove_usb_stuff(hdw);
2007 down(&pvr2_unit_sem); do {
2008 if ((hdw->unit_number >= 0) &&
2009 (hdw->unit_number < PVR_NUM) &&
2010 (unit_pointers[hdw->unit_number] == hdw)) {
2011 unit_pointers[hdw->unit_number] = NULL;
2012 }
2013 } while (0); up(&pvr2_unit_sem);
2014 if (hdw->controls) kfree(hdw->controls);
2015 if (hdw->mpeg_ctrl_info) kfree(hdw->mpeg_ctrl_info);
2016 if (hdw->std_defs) kfree(hdw->std_defs);
2017 if (hdw->std_enum_names) kfree(hdw->std_enum_names);
2018 kfree(hdw);
2019 }
2020
2021
2022 int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2023 {
2024 return hdw->flag_init_ok;
2025 }
2026
2027
2028 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2029 {
2030 return (hdw && hdw->flag_ok);
2031 }
2032
2033
2034 /* Called when hardware has been unplugged */
2035 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2036 {
2037 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2038 LOCK_TAKE(hdw->big_lock);
2039 LOCK_TAKE(hdw->ctl_lock);
2040 pvr2_hdw_remove_usb_stuff(hdw);
2041 LOCK_GIVE(hdw->ctl_lock);
2042 LOCK_GIVE(hdw->big_lock);
2043 }
2044
2045
2046 // Attempt to autoselect an appropriate value for std_enum_cur given
2047 // whatever is currently in std_mask_cur
2048 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2049 {
2050 unsigned int idx;
2051 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2052 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2053 hdw->std_enum_cur = idx;
2054 return;
2055 }
2056 }
2057 hdw->std_enum_cur = 0;
2058 }
2059
2060
2061 // Calculate correct set of enumerated standards based on currently known
2062 // set of available standards bits.
2063 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2064 {
2065 struct v4l2_standard *newstd;
2066 unsigned int std_cnt;
2067 unsigned int idx;
2068
2069 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2070
2071 if (hdw->std_defs) {
2072 kfree(hdw->std_defs);
2073 hdw->std_defs = NULL;
2074 }
2075 hdw->std_enum_cnt = 0;
2076 if (hdw->std_enum_names) {
2077 kfree(hdw->std_enum_names);
2078 hdw->std_enum_names = NULL;
2079 }
2080
2081 if (!std_cnt) {
2082 pvr2_trace(
2083 PVR2_TRACE_ERROR_LEGS,
2084 "WARNING: Failed to identify any viable standards");
2085 }
2086 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2087 hdw->std_enum_names[0] = "none";
2088 for (idx = 0; idx < std_cnt; idx++) {
2089 hdw->std_enum_names[idx+1] =
2090 newstd[idx].name;
2091 }
2092 // Set up the dynamic control for this standard
2093 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2094 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2095 hdw->std_defs = newstd;
2096 hdw->std_enum_cnt = std_cnt+1;
2097 hdw->std_enum_cur = 0;
2098 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2099 }
2100
2101
2102 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2103 struct v4l2_standard *std,
2104 unsigned int idx)
2105 {
2106 int ret = -EINVAL;
2107 if (!idx) return ret;
2108 LOCK_TAKE(hdw->big_lock); do {
2109 if (idx >= hdw->std_enum_cnt) break;
2110 idx--;
2111 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2112 ret = 0;
2113 } while (0); LOCK_GIVE(hdw->big_lock);
2114 return ret;
2115 }
2116
2117
2118 /* Get the number of defined controls */
2119 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2120 {
2121 return hdw->control_cnt;
2122 }
2123
2124
2125 /* Retrieve a control handle given its index (0..count-1) */
2126 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2127 unsigned int idx)
2128 {
2129 if (idx >= hdw->control_cnt) return NULL;
2130 return hdw->controls + idx;
2131 }
2132
2133
2134 /* Retrieve a control handle given its index (0..count-1) */
2135 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2136 unsigned int ctl_id)
2137 {
2138 struct pvr2_ctrl *cptr;
2139 unsigned int idx;
2140 int i;
2141
2142 /* This could be made a lot more efficient, but for now... */
2143 for (idx = 0; idx < hdw->control_cnt; idx++) {
2144 cptr = hdw->controls + idx;
2145 i = cptr->info->internal_id;
2146 if (i && (i == ctl_id)) return cptr;
2147 }
2148 return NULL;
2149 }
2150
2151
2152 /* Given a V4L ID, retrieve the control structure associated with it. */
2153 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2154 {
2155 struct pvr2_ctrl *cptr;
2156 unsigned int idx;
2157 int i;
2158
2159 /* This could be made a lot more efficient, but for now... */
2160 for (idx = 0; idx < hdw->control_cnt; idx++) {
2161 cptr = hdw->controls + idx;
2162 i = cptr->info->v4l_id;
2163 if (i && (i == ctl_id)) return cptr;
2164 }
2165 return NULL;
2166 }
2167
2168
2169 /* Given a V4L ID for its immediate predecessor, retrieve the control
2170 structure associated with it. */
2171 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2172 unsigned int ctl_id)
2173 {
2174 struct pvr2_ctrl *cptr,*cp2;
2175 unsigned int idx;
2176 int i;
2177
2178 /* This could be made a lot more efficient, but for now... */
2179 cp2 = NULL;
2180 for (idx = 0; idx < hdw->control_cnt; idx++) {
2181 cptr = hdw->controls + idx;
2182 i = cptr->info->v4l_id;
2183 if (!i) continue;
2184 if (i <= ctl_id) continue;
2185 if (cp2 && (cp2->info->v4l_id < i)) continue;
2186 cp2 = cptr;
2187 }
2188 return cp2;
2189 return NULL;
2190 }
2191
2192
2193 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2194 {
2195 switch (tp) {
2196 case pvr2_ctl_int: return "integer";
2197 case pvr2_ctl_enum: return "enum";
2198 case pvr2_ctl_bool: return "boolean";
2199 case pvr2_ctl_bitmask: return "bitmask";
2200 }
2201 return "";
2202 }
2203
2204
2205 /* Commit all control changes made up to this point. Subsystems can be
2206 indirectly affected by these changes. For a given set of things being
2207 committed, we'll clear the affected subsystem bits and then once we're
2208 done committing everything we'll make a request to restore the subsystem
2209 state(s) back to their previous value before this function was called.
2210 Thus we can automatically reconfigure affected pieces of the driver as
2211 controls are changed. */
2212 static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
2213 {
2214 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2215 unsigned long stale_subsys_mask = 0;
2216 unsigned int idx;
2217 struct pvr2_ctrl *cptr;
2218 int value;
2219 int commit_flag = 0;
2220 char buf[100];
2221 unsigned int bcnt,ccnt;
2222
2223 for (idx = 0; idx < hdw->control_cnt; idx++) {
2224 cptr = hdw->controls + idx;
2225 if (cptr->info->is_dirty == 0) continue;
2226 if (!cptr->info->is_dirty(cptr)) continue;
2227 if (!commit_flag) {
2228 commit_flag = !0;
2229 }
2230
2231 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2232 cptr->info->name);
2233 value = 0;
2234 cptr->info->get_value(cptr,&value);
2235 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2236 buf+bcnt,
2237 sizeof(buf)-bcnt,&ccnt);
2238 bcnt += ccnt;
2239 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2240 get_ctrl_typename(cptr->info->type));
2241 pvr2_trace(PVR2_TRACE_CTL,
2242 "/*--TRACE_COMMIT--*/ %.*s",
2243 bcnt,buf);
2244 }
2245
2246 if (!commit_flag) {
2247 /* Nothing has changed */
2248 return 0;
2249 }
2250
2251 /* When video standard changes, reset the hres and vres values -
2252 but if the user has pending changes there, then let the changes
2253 take priority. */
2254 if (hdw->std_dirty) {
2255 /* Rewrite the vertical resolution to be appropriate to the
2256 video standard that has been selected. */
2257 int nvres;
2258 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2259 nvres = 480;
2260 } else {
2261 nvres = 576;
2262 }
2263 if (nvres != hdw->res_ver_val) {
2264 hdw->res_ver_val = nvres;
2265 hdw->res_ver_dirty = !0;
2266 }
2267 }
2268
2269 if (hdw->std_dirty ||
2270 0) {
2271 /* If any of this changes, then the encoder needs to be
2272 reconfigured, and we need to reset the stream. */
2273 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2274 stale_subsys_mask |= hdw->subsys_stream_mask;
2275 }
2276
2277 if (hdw->srate_dirty) {
2278 /* Write new sample rate into control structure since
2279 * the master copy is stale. We must track srate
2280 * separate from the mpeg control structure because
2281 * other logic also uses this value. */
2282 struct v4l2_ext_controls cs;
2283 struct v4l2_ext_control c1;
2284 memset(&cs,0,sizeof(cs));
2285 memset(&c1,0,sizeof(c1));
2286 cs.controls = &c1;
2287 cs.count = 1;
2288 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2289 c1.value = hdw->srate_val;
2290 cx2341x_ext_ctrls(&hdw->enc_ctl_state,&cs,VIDIOC_S_EXT_CTRLS);
2291 }
2292
2293 /* Scan i2c core at this point - before we clear all the dirty
2294 bits. Various parts of the i2c core will notice dirty bits as
2295 appropriate and arrange to broadcast or directly send updates to
2296 the client drivers in order to keep everything in sync */
2297 pvr2_i2c_core_check_stale(hdw);
2298
2299 for (idx = 0; idx < hdw->control_cnt; idx++) {
2300 cptr = hdw->controls + idx;
2301 if (!cptr->info->clear_dirty) continue;
2302 cptr->info->clear_dirty(cptr);
2303 }
2304
2305 /* Now execute i2c core update */
2306 pvr2_i2c_core_sync(hdw);
2307
2308 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2309 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2310
2311 return 0;
2312 }
2313
2314
2315 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2316 {
2317 LOCK_TAKE(hdw->big_lock); do {
2318 pvr2_hdw_commit_ctl_internal(hdw);
2319 } while (0); LOCK_GIVE(hdw->big_lock);
2320 return 0;
2321 }
2322
2323
2324 void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2325 {
2326 LOCK_TAKE(hdw->big_lock); do {
2327 pvr2_i2c_core_sync(hdw);
2328 } while (0); LOCK_GIVE(hdw->big_lock);
2329 }
2330
2331
2332 void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2333 void (*func)(void *),
2334 void *data)
2335 {
2336 LOCK_TAKE(hdw->big_lock); do {
2337 hdw->poll_trigger_func = func;
2338 hdw->poll_trigger_data = data;
2339 } while (0); LOCK_GIVE(hdw->big_lock);
2340 }
2341
2342
2343 void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2344 {
2345 if (hdw->poll_trigger_func) {
2346 hdw->poll_trigger_func(hdw->poll_trigger_data);
2347 }
2348 }
2349
2350 /* Return name for this driver instance */
2351 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2352 {
2353 return hdw->name;
2354 }
2355
2356
2357 /* Return bit mask indicating signal status */
2358 static unsigned int pvr2_hdw_get_signal_status_internal(struct pvr2_hdw *hdw)
2359 {
2360 unsigned int msk = 0;
2361 switch (hdw->input_val) {
2362 case PVR2_CVAL_INPUT_TV:
2363 case PVR2_CVAL_INPUT_RADIO:
2364 if (hdw->decoder_ctrl &&
2365 hdw->decoder_ctrl->tuned(hdw->decoder_ctrl->ctxt)) {
2366 msk |= PVR2_SIGNAL_OK;
2367 if (hdw->audio_stat &&
2368 hdw->audio_stat->status(hdw->audio_stat->ctxt)) {
2369 if (hdw->flag_stereo) {
2370 msk |= PVR2_SIGNAL_STEREO;
2371 }
2372 if (hdw->flag_bilingual) {
2373 msk |= PVR2_SIGNAL_SAP;
2374 }
2375 }
2376 }
2377 break;
2378 default:
2379 msk |= PVR2_SIGNAL_OK | PVR2_SIGNAL_STEREO;
2380 }
2381 return msk;
2382 }
2383
2384
2385 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2386 {
2387 int result;
2388 LOCK_TAKE(hdw->ctl_lock); do {
2389 hdw->cmd_buffer[0] = 0x0b;
2390 result = pvr2_send_request(hdw,
2391 hdw->cmd_buffer,1,
2392 hdw->cmd_buffer,1);
2393 if (result < 0) break;
2394 result = (hdw->cmd_buffer[0] != 0);
2395 } while(0); LOCK_GIVE(hdw->ctl_lock);
2396 return result;
2397 }
2398
2399
2400 /* Return bit mask indicating signal status */
2401 unsigned int pvr2_hdw_get_signal_status(struct pvr2_hdw *hdw)
2402 {
2403 unsigned int msk = 0;
2404 LOCK_TAKE(hdw->big_lock); do {
2405 msk = pvr2_hdw_get_signal_status_internal(hdw);
2406 } while (0); LOCK_GIVE(hdw->big_lock);
2407 return msk;
2408 }
2409
2410
2411 /* Get handle to video output stream */
2412 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2413 {
2414 return hp->vid_stream;
2415 }
2416
2417
2418 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2419 {
2420 int nr = pvr2_hdw_get_unit_number(hdw);
2421 LOCK_TAKE(hdw->big_lock); do {
2422 hdw->log_requested = !0;
2423 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2424 pvr2_i2c_core_check_stale(hdw);
2425 hdw->log_requested = 0;
2426 pvr2_i2c_core_sync(hdw);
2427 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2428 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2429 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2430 } while (0); LOCK_GIVE(hdw->big_lock);
2431 }
2432
2433 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw, int enable_flag)
2434 {
2435 int ret;
2436 u16 address;
2437 unsigned int pipe;
2438 LOCK_TAKE(hdw->big_lock); do {
2439 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2440
2441 if (!enable_flag) {
2442 pvr2_trace(PVR2_TRACE_FIRMWARE,
2443 "Cleaning up after CPU firmware fetch");
2444 kfree(hdw->fw_buffer);
2445 hdw->fw_buffer = NULL;
2446 hdw->fw_size = 0;
2447 /* Now release the CPU. It will disconnect and
2448 reconnect later. */
2449 pvr2_hdw_cpureset_assert(hdw,0);
2450 break;
2451 }
2452
2453 pvr2_trace(PVR2_TRACE_FIRMWARE,
2454 "Preparing to suck out CPU firmware");
2455 hdw->fw_size = 0x2000;
2456 hdw->fw_buffer = kmalloc(hdw->fw_size,GFP_KERNEL);
2457 if (!hdw->fw_buffer) {
2458 hdw->fw_size = 0;
2459 break;
2460 }
2461
2462 memset(hdw->fw_buffer,0,hdw->fw_size);
2463
2464 /* We have to hold the CPU during firmware upload. */
2465 pvr2_hdw_cpureset_assert(hdw,1);
2466
2467 /* download the firmware from address 0000-1fff in 2048
2468 (=0x800) bytes chunk. */
2469
2470 pvr2_trace(PVR2_TRACE_FIRMWARE,"Grabbing CPU firmware");
2471 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2472 for(address = 0; address < hdw->fw_size; address += 0x800) {
2473 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0xc0,
2474 address,0,
2475 hdw->fw_buffer+address,0x800,HZ);
2476 if (ret < 0) break;
2477 }
2478
2479 pvr2_trace(PVR2_TRACE_FIRMWARE,"Done grabbing CPU firmware");
2480
2481 } while (0); LOCK_GIVE(hdw->big_lock);
2482 }
2483
2484
2485 /* Return true if we're in a mode for retrieval CPU firmware */
2486 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2487 {
2488 return hdw->fw_buffer != 0;
2489 }
2490
2491
2492 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2493 char *buf,unsigned int cnt)
2494 {
2495 int ret = -EINVAL;
2496 LOCK_TAKE(hdw->big_lock); do {
2497 if (!buf) break;
2498 if (!cnt) break;
2499
2500 if (!hdw->fw_buffer) {
2501 ret = -EIO;
2502 break;
2503 }
2504
2505 if (offs >= hdw->fw_size) {
2506 pvr2_trace(PVR2_TRACE_FIRMWARE,
2507 "Read firmware data offs=%d EOF",
2508 offs);
2509 ret = 0;
2510 break;
2511 }
2512
2513 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2514
2515 memcpy(buf,hdw->fw_buffer+offs,cnt);
2516
2517 pvr2_trace(PVR2_TRACE_FIRMWARE,
2518 "Read firmware data offs=%d cnt=%d",
2519 offs,cnt);
2520 ret = cnt;
2521 } while (0); LOCK_GIVE(hdw->big_lock);
2522
2523 return ret;
2524 }
2525
2526
2527 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw)
2528 {
2529 return hdw->v4l_minor_number;
2530 }
2531
2532
2533 /* Store the v4l minor device number */
2534 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,int v)
2535 {
2536 hdw->v4l_minor_number = v;
2537 }
2538
2539
2540 static void pvr2_ctl_write_complete(struct urb *urb, struct pt_regs *regs)
2541 {
2542 struct pvr2_hdw *hdw = urb->context;
2543 hdw->ctl_write_pend_flag = 0;
2544 if (hdw->ctl_read_pend_flag) return;
2545 complete(&hdw->ctl_done);
2546 }
2547
2548
2549 static void pvr2_ctl_read_complete(struct urb *urb, struct pt_regs *regs)
2550 {
2551 struct pvr2_hdw *hdw = urb->context;
2552 hdw->ctl_read_pend_flag = 0;
2553 if (hdw->ctl_write_pend_flag) return;
2554 complete(&hdw->ctl_done);
2555 }
2556
2557
2558 static void pvr2_ctl_timeout(unsigned long data)
2559 {
2560 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2561 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2562 hdw->ctl_timeout_flag = !0;
2563 if (hdw->ctl_write_pend_flag && hdw->ctl_write_urb) {
2564 usb_unlink_urb(hdw->ctl_write_urb);
2565 }
2566 if (hdw->ctl_read_pend_flag && hdw->ctl_read_urb) {
2567 usb_unlink_urb(hdw->ctl_read_urb);
2568 }
2569 }
2570 }
2571
2572
2573 /* Issue a command and get a response from the device. This extended
2574 version includes a probe flag (which if set means that device errors
2575 should not be logged or treated as fatal) and a timeout in jiffies.
2576 This can be used to non-lethally probe the health of endpoint 1. */
2577 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2578 unsigned int timeout,int probe_fl,
2579 void *write_data,unsigned int write_len,
2580 void *read_data,unsigned int read_len)
2581 {
2582 unsigned int idx;
2583 int status = 0;
2584 struct timer_list timer;
2585 if (!hdw->ctl_lock_held) {
2586 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2587 "Attempted to execute control transfer"
2588 " without lock!!");
2589 return -EDEADLK;
2590 }
2591 if ((!hdw->flag_ok) && !probe_fl) {
2592 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2593 "Attempted to execute control transfer"
2594 " when device not ok");
2595 return -EIO;
2596 }
2597 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2598 if (!probe_fl) {
2599 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2600 "Attempted to execute control transfer"
2601 " when USB is disconnected");
2602 }
2603 return -ENOTTY;
2604 }
2605
2606 /* Ensure that we have sane parameters */
2607 if (!write_data) write_len = 0;
2608 if (!read_data) read_len = 0;
2609 if (write_len > PVR2_CTL_BUFFSIZE) {
2610 pvr2_trace(
2611 PVR2_TRACE_ERROR_LEGS,
2612 "Attempted to execute %d byte"
2613 " control-write transfer (limit=%d)",
2614 write_len,PVR2_CTL_BUFFSIZE);
2615 return -EINVAL;
2616 }
2617 if (read_len > PVR2_CTL_BUFFSIZE) {
2618 pvr2_trace(
2619 PVR2_TRACE_ERROR_LEGS,
2620 "Attempted to execute %d byte"
2621 " control-read transfer (limit=%d)",
2622 write_len,PVR2_CTL_BUFFSIZE);
2623 return -EINVAL;
2624 }
2625 if ((!write_len) && (!read_len)) {
2626 pvr2_trace(
2627 PVR2_TRACE_ERROR_LEGS,
2628 "Attempted to execute null control transfer?");
2629 return -EINVAL;
2630 }
2631
2632
2633 hdw->cmd_debug_state = 1;
2634 if (write_len) {
2635 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2636 } else {
2637 hdw->cmd_debug_code = 0;
2638 }
2639 hdw->cmd_debug_write_len = write_len;
2640 hdw->cmd_debug_read_len = read_len;
2641
2642 /* Initialize common stuff */
2643 init_completion(&hdw->ctl_done);
2644 hdw->ctl_timeout_flag = 0;
2645 hdw->ctl_write_pend_flag = 0;
2646 hdw->ctl_read_pend_flag = 0;
2647 init_timer(&timer);
2648 timer.expires = jiffies + timeout;
2649 timer.data = (unsigned long)hdw;
2650 timer.function = pvr2_ctl_timeout;
2651
2652 if (write_len) {
2653 hdw->cmd_debug_state = 2;
2654 /* Transfer write data to internal buffer */
2655 for (idx = 0; idx < write_len; idx++) {
2656 hdw->ctl_write_buffer[idx] =
2657 ((unsigned char *)write_data)[idx];
2658 }
2659 /* Initiate a write request */
2660 usb_fill_bulk_urb(hdw->ctl_write_urb,
2661 hdw->usb_dev,
2662 usb_sndbulkpipe(hdw->usb_dev,
2663 PVR2_CTL_WRITE_ENDPOINT),
2664 hdw->ctl_write_buffer,
2665 write_len,
2666 pvr2_ctl_write_complete,
2667 hdw);
2668 hdw->ctl_write_urb->actual_length = 0;
2669 hdw->ctl_write_pend_flag = !0;
2670 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2671 if (status < 0) {
2672 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2673 "Failed to submit write-control"
2674 " URB status=%d",status);
2675 hdw->ctl_write_pend_flag = 0;
2676 goto done;
2677 }
2678 }
2679
2680 if (read_len) {
2681 hdw->cmd_debug_state = 3;
2682 memset(hdw->ctl_read_buffer,0x43,read_len);
2683 /* Initiate a read request */
2684 usb_fill_bulk_urb(hdw->ctl_read_urb,
2685 hdw->usb_dev,
2686 usb_rcvbulkpipe(hdw->usb_dev,
2687 PVR2_CTL_READ_ENDPOINT),
2688 hdw->ctl_read_buffer,
2689 read_len,
2690 pvr2_ctl_read_complete,
2691 hdw);
2692 hdw->ctl_read_urb->actual_length = 0;
2693 hdw->ctl_read_pend_flag = !0;
2694 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2695 if (status < 0) {
2696 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2697 "Failed to submit read-control"
2698 " URB status=%d",status);
2699 hdw->ctl_read_pend_flag = 0;
2700 goto done;
2701 }
2702 }
2703
2704 /* Start timer */
2705 add_timer(&timer);
2706
2707 /* Now wait for all I/O to complete */
2708 hdw->cmd_debug_state = 4;
2709 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2710 wait_for_completion(&hdw->ctl_done);
2711 }
2712 hdw->cmd_debug_state = 5;
2713
2714 /* Stop timer */
2715 del_timer_sync(&timer);
2716
2717 hdw->cmd_debug_state = 6;
2718 status = 0;
2719
2720 if (hdw->ctl_timeout_flag) {
2721 status = -ETIMEDOUT;
2722 if (!probe_fl) {
2723 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2724 "Timed out control-write");
2725 }
2726 goto done;
2727 }
2728
2729 if (write_len) {
2730 /* Validate results of write request */
2731 if ((hdw->ctl_write_urb->status != 0) &&
2732 (hdw->ctl_write_urb->status != -ENOENT) &&
2733 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2734 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2735 /* USB subsystem is reporting some kind of failure
2736 on the write */
2737 status = hdw->ctl_write_urb->status;
2738 if (!probe_fl) {
2739 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2740 "control-write URB failure,"
2741 " status=%d",
2742 status);
2743 }
2744 goto done;
2745 }
2746 if (hdw->ctl_write_urb->actual_length < write_len) {
2747 /* Failed to write enough data */
2748 status = -EIO;
2749 if (!probe_fl) {
2750 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2751 "control-write URB short,"
2752 " expected=%d got=%d",
2753 write_len,
2754 hdw->ctl_write_urb->actual_length);
2755 }
2756 goto done;
2757 }
2758 }
2759 if (read_len) {
2760 /* Validate results of read request */
2761 if ((hdw->ctl_read_urb->status != 0) &&
2762 (hdw->ctl_read_urb->status != -ENOENT) &&
2763 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
2764 (hdw->ctl_read_urb->status != -ECONNRESET)) {
2765 /* USB subsystem is reporting some kind of failure
2766 on the read */
2767 status = hdw->ctl_read_urb->status;
2768 if (!probe_fl) {
2769 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2770 "control-read URB failure,"
2771 " status=%d",
2772 status);
2773 }
2774 goto done;
2775 }
2776 if (hdw->ctl_read_urb->actual_length < read_len) {
2777 /* Failed to read enough data */
2778 status = -EIO;
2779 if (!probe_fl) {
2780 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2781 "control-read URB short,"
2782 " expected=%d got=%d",
2783 read_len,
2784 hdw->ctl_read_urb->actual_length);
2785 }
2786 goto done;
2787 }
2788 /* Transfer retrieved data out from internal buffer */
2789 for (idx = 0; idx < read_len; idx++) {
2790 ((unsigned char *)read_data)[idx] =
2791 hdw->ctl_read_buffer[idx];
2792 }
2793 }
2794
2795 done:
2796
2797 hdw->cmd_debug_state = 0;
2798 if ((status < 0) && (!probe_fl)) {
2799 pvr2_hdw_render_useless_unlocked(hdw);
2800 }
2801 return status;
2802 }
2803
2804
2805 int pvr2_send_request(struct pvr2_hdw *hdw,
2806 void *write_data,unsigned int write_len,
2807 void *read_data,unsigned int read_len)
2808 {
2809 return pvr2_send_request_ex(hdw,HZ*4,0,
2810 write_data,write_len,
2811 read_data,read_len);
2812 }
2813
2814 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
2815 {
2816 int ret;
2817
2818 LOCK_TAKE(hdw->ctl_lock);
2819
2820 hdw->cmd_buffer[0] = 0x04; /* write register prefix */
2821 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
2822 hdw->cmd_buffer[5] = 0;
2823 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2824 hdw->cmd_buffer[7] = reg & 0xff;
2825
2826
2827 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
2828
2829 LOCK_GIVE(hdw->ctl_lock);
2830
2831 return ret;
2832 }
2833
2834
2835 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
2836 {
2837 int ret = 0;
2838
2839 LOCK_TAKE(hdw->ctl_lock);
2840
2841 hdw->cmd_buffer[0] = 0x05; /* read register prefix */
2842 hdw->cmd_buffer[1] = 0;
2843 hdw->cmd_buffer[2] = 0;
2844 hdw->cmd_buffer[3] = 0;
2845 hdw->cmd_buffer[4] = 0;
2846 hdw->cmd_buffer[5] = 0;
2847 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
2848 hdw->cmd_buffer[7] = reg & 0xff;
2849
2850 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
2851 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
2852
2853 LOCK_GIVE(hdw->ctl_lock);
2854
2855 return ret;
2856 }
2857
2858
2859 static int pvr2_write_u16(struct pvr2_hdw *hdw, u16 data, int res)
2860 {
2861 int ret;
2862
2863 LOCK_TAKE(hdw->ctl_lock);
2864
2865 hdw->cmd_buffer[0] = (data >> 8) & 0xff;
2866 hdw->cmd_buffer[1] = data & 0xff;
2867
2868 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 2, hdw->cmd_buffer, res);
2869
2870 LOCK_GIVE(hdw->ctl_lock);
2871
2872 return ret;
2873 }
2874
2875
2876 static int pvr2_write_u8(struct pvr2_hdw *hdw, u8 data, int res)
2877 {
2878 int ret;
2879
2880 LOCK_TAKE(hdw->ctl_lock);
2881
2882 hdw->cmd_buffer[0] = data;
2883
2884 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 1, hdw->cmd_buffer, res);
2885
2886 LOCK_GIVE(hdw->ctl_lock);
2887
2888 return ret;
2889 }
2890
2891
2892 static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
2893 {
2894 if (!hdw->flag_ok) return;
2895 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
2896 hdw->flag_ok = 0;
2897 if (hdw->vid_stream) {
2898 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
2899 }
2900 hdw->flag_streaming_enabled = 0;
2901 hdw->subsys_enabled_mask = 0;
2902 }
2903
2904
2905 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
2906 {
2907 LOCK_TAKE(hdw->ctl_lock);
2908 pvr2_hdw_render_useless_unlocked(hdw);
2909 LOCK_GIVE(hdw->ctl_lock);
2910 }
2911
2912
2913 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
2914 {
2915 int ret;
2916 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
2917 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
2918 if (ret == 1) {
2919 ret = usb_reset_device(hdw->usb_dev);
2920 usb_unlock_device(hdw->usb_dev);
2921 } else {
2922 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2923 "Failed to lock USB device ret=%d",ret);
2924 }
2925 if (init_pause_msec) {
2926 pvr2_trace(PVR2_TRACE_INFO,
2927 "Waiting %u msec for hardware to settle",
2928 init_pause_msec);
2929 msleep(init_pause_msec);
2930 }
2931
2932 }
2933
2934
2935 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
2936 {
2937 char da[1];
2938 unsigned int pipe;
2939 int ret;
2940
2941 if (!hdw->usb_dev) return;
2942
2943 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
2944
2945 da[0] = val ? 0x01 : 0x00;
2946
2947 /* Write the CPUCS register on the 8051. The lsb of the register
2948 is the reset bit; a 1 asserts reset while a 0 clears it. */
2949 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
2950 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
2951 if (ret < 0) {
2952 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2953 "cpureset_assert(%d) error=%d",val,ret);
2954 pvr2_hdw_render_useless(hdw);
2955 }
2956 }
2957
2958
2959 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
2960 {
2961 int status;
2962 LOCK_TAKE(hdw->ctl_lock); do {
2963 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
2964 hdw->flag_ok = !0;
2965 hdw->cmd_buffer[0] = 0xdd;
2966 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2967 } while (0); LOCK_GIVE(hdw->ctl_lock);
2968 return status;
2969 }
2970
2971
2972 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
2973 {
2974 int status;
2975 LOCK_TAKE(hdw->ctl_lock); do {
2976 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
2977 hdw->cmd_buffer[0] = 0xde;
2978 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
2979 } while (0); LOCK_GIVE(hdw->ctl_lock);
2980 return status;
2981 }
2982
2983
2984 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
2985 {
2986 if (!hdw->decoder_ctrl) {
2987 pvr2_trace(PVR2_TRACE_INIT,
2988 "Unable to reset decoder: nothing attached");
2989 return -ENOTTY;
2990 }
2991
2992 if (!hdw->decoder_ctrl->force_reset) {
2993 pvr2_trace(PVR2_TRACE_INIT,
2994 "Unable to reset decoder: not implemented");
2995 return -ENOTTY;
2996 }
2997
2998 pvr2_trace(PVR2_TRACE_INIT,
2999 "Requesting decoder reset");
3000 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3001 return 0;
3002 }
3003
3004
3005 /* Stop / start video stream transport */
3006 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3007 {
3008 int status;
3009 LOCK_TAKE(hdw->ctl_lock); do {
3010 hdw->cmd_buffer[0] = (runFl ? 0x36 : 0x37);
3011 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3012 } while (0); LOCK_GIVE(hdw->ctl_lock);
3013 if (!status) {
3014 hdw->subsys_enabled_mask =
3015 ((hdw->subsys_enabled_mask &
3016 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3017 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3018 }
3019 return status;
3020 }
3021
3022
3023 void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3024 struct pvr2_hdw_debug_info *ptr)
3025 {
3026 ptr->big_lock_held = hdw->big_lock_held;
3027 ptr->ctl_lock_held = hdw->ctl_lock_held;
3028 ptr->flag_ok = hdw->flag_ok;
3029 ptr->flag_disconnected = hdw->flag_disconnected;
3030 ptr->flag_init_ok = hdw->flag_init_ok;
3031 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3032 ptr->subsys_flags = hdw->subsys_enabled_mask;
3033 ptr->cmd_debug_state = hdw->cmd_debug_state;
3034 ptr->cmd_code = hdw->cmd_debug_code;
3035 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3036 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3037 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3038 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3039 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3040 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3041 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3042 }
3043
3044
3045 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3046 {
3047 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3048 }
3049
3050
3051 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3052 {
3053 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3054 }
3055
3056
3057 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3058 {
3059 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3060 }
3061
3062
3063 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3064 {
3065 u32 cval,nval;
3066 int ret;
3067 if (~msk) {
3068 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3069 if (ret) return ret;
3070 nval = (cval & ~msk) | (val & msk);
3071 pvr2_trace(PVR2_TRACE_GPIO,
3072 "GPIO direction changing 0x%x:0x%x"
3073 " from 0x%x to 0x%x",
3074 msk,val,cval,nval);
3075 } else {
3076 nval = val;
3077 pvr2_trace(PVR2_TRACE_GPIO,
3078 "GPIO direction changing to 0x%x",nval);
3079 }
3080 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3081 }
3082
3083
3084 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3085 {
3086 u32 cval,nval;
3087 int ret;
3088 if (~msk) {
3089 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3090 if (ret) return ret;
3091 nval = (cval & ~msk) | (val & msk);
3092 pvr2_trace(PVR2_TRACE_GPIO,
3093 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3094 msk,val,cval,nval);
3095 } else {
3096 nval = val;
3097 pvr2_trace(PVR2_TRACE_GPIO,
3098 "GPIO output changing to 0x%x",nval);
3099 }
3100 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3101 }
3102
3103
3104 /* Find I2C address of eeprom */
3105 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3106 {
3107 int result;
3108 LOCK_TAKE(hdw->ctl_lock); do {
3109 hdw->cmd_buffer[0] = 0xeb;
3110 result = pvr2_send_request(hdw,
3111 hdw->cmd_buffer,1,
3112 hdw->cmd_buffer,1);
3113 if (result < 0) break;
3114 result = hdw->cmd_buffer[0];
3115 } while(0); LOCK_GIVE(hdw->ctl_lock);
3116 return result;
3117 }
3118
3119
3120 /*
3121 Stuff for Emacs to see, in order to encourage consistent editing style:
3122 *** Local Variables: ***
3123 *** mode: c ***
3124 *** fill-column: 75 ***
3125 *** tab-width: 8 ***
3126 *** c-basic-offset: 8 ***
3127 *** End: ***
3128 */
Linux with added FPC-III support