Documentation/devicetree/bindings/clock/sunxi.txt

   1 Device Tree Clock bindings for arch-sunxi
   2
   3 This binding uses the common clock binding[1].
   4
   5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7 Required properties:
   8 - compatible : shall be one of the following:
   9         "allwinner,sun4i-osc-clk" - for a gatable oscillator
  10         "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
  11         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  12         "allwinner,sun4i-pll5-clk" - for the PLL5 clock
  13         "allwinner,sun4i-pll6-clk" - for the PLL6 clock
  14         "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
  15         "allwinner,sun4i-axi-clk" - for the AXI clock
  16         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  17         "allwinner,sun4i-ahb-clk" - for the AHB clock
  18         "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
  19         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  20         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  21         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  22         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
  23         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  24         "allwinner,sun4i-apb0-clk" - for the APB0 clock
  25         "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
  26         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  27         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  28         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  29         "allwinner,sun4i-apb1-clk" - for the APB1 clock
  30         "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
  31         "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
  32         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  33         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  34         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  35         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  36         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  37         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  38         "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  39         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  40
  41 Required properties for all clocks:
  42 - reg : shall be the control register address for the clock.
  43 - clocks : shall be the input parent clock(s) phandle for the clock. For
  44         multiplexed clocks, the list order must match the hardware
  45         programming order.
  46 - #clock-cells : from common clock binding; shall be set to 0 except for
  47         "allwinner,*-gates-clk" where it shall be set to 1
  48
  49 Additionally, "allwinner,*-gates-clk" clocks require:
  50 - clock-output-names : the corresponding gate names that the clock controls
  51
  52 Clock consumers should specify the desired clocks they use with a
  53 "clocks" phandle cell. Consumers that are using a gated clock should
  54 provide an additional ID in their clock property. This ID is the
  55 offset of the bit controlling this particular gate in the register.
  56
  57 For example:
  58
  59 osc24M: osc24M@01c20050 {
  60         #clock-cells = <0>;
  61         compatible = "allwinner,sun4i-osc-clk";
  62         reg = <0x01c20050 0x4>;
  63         clocks = <&osc24M_fixed>;
  64 };
  65
  66 pll1: pll1@01c20000 {
  67         #clock-cells = <0>;
  68         compatible = "allwinner,sun4i-pll1-clk";
  69         reg = <0x01c20000 0x4>;
  70         clocks = <&osc24M>;
  71 };
  72
  73 cpu: cpu@01c20054 {
  74         #clock-cells = <0>;
  75         compatible = "allwinner,sun4i-cpu-clk";
  76         reg = <0x01c20054 0x4>;
  77         clocks = <&osc32k>, <&osc24M>, <&pll1>;
  78 };