Documentation/devicetree/bindings/clock/ti/gate.txt

   1 Binding for Texas Instruments gate clock.
   2
   3 Binding status: Unstable - ABI compatibility may be broken in the future
   4
   5 This binding uses the common clock binding[1]. This clock is
   6 quite much similar to the basic gate-clock [2], however,
   7 it supports a number of additional features. If no register
   8 is provided for this clock, the code assumes that a clockdomain
   9 will be controlled instead and the corresponding hw-ops for
  10 that is used.
  11
  12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  13 [2] Documentation/devicetree/bindings/clock/gate-clock.txt
  14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
  15
  16 Required properties:
  17 - compatible : shall be one of:
  18   "ti,gate-clock" - basic gate clock
  19   "ti,wait-gate-clock" - gate clock which waits until clock is active before
  20                          returning from clk_enable()
  21   "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
  22   "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
  23   "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
  24                           clock directly from a clockdomain, see [3] how
  25                           to map clockdomains properly
  26   "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
  27                           required for a hardware errata
  28 - #clock-cells : from common clock binding; shall be set to 0
  29 - clocks : link to phandle of parent clock
  30 - reg : offset for register controlling adjustable gate, not needed for
  31         ti,clkdm-gate-clock type
  32
  33 Optional properties:
  34 - ti,bit-shift : bit shift for programming the clock gate, invalid for
  35                  ti,clkdm-gate-clock type
  36 - ti,set-bit-to-disable : inverts default gate programming. Setting the bit
  37   gates the clock and clearing the bit ungates the clock.
  38
  39 Examples:
  40         mmchs2_fck: mmchs2_fck@48004a00 {
  41                 #clock-cells = <0>;
  42                 compatible = "ti,gate-clock";
  43                 clocks = <&core_96m_fck>;
  44                 reg = <0x48004a00 0x4>;
  45                 ti,bit-shift = <25>;
  46         };
  47
  48         uart4_fck_am35xx: uart4_fck_am35xx {
  49                 #clock-cells = <0>;
  50                 compatible = "ti,wait-gate-clock";
  51                 clocks = <&core_48m_fck>;
  52                 reg = <0x0a00>;
  53                 ti,bit-shift = <23>;
  54         };
  55
  56         dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
  57                 #clock-cells = <0>;
  58                 compatible = "ti,dss-gate-clock";
  59                 clocks = <&dpll4_m4x2_ck>;
  60                 reg = <0x48004e00 0x4>;
  61                 ti,bit-shift = <0>;
  62         };
  63
  64         emac_ick: emac_ick@4800259c {
  65                 #clock-cells = <0>;
  66                 compatible = "ti,am35xx-gate-clock";
  67                 clocks = <&ipss_ick>;
  68                 reg = <0x4800259c 0x4>;
  69                 ti,bit-shift = <1>;
  70         };
  71
  72         emu_src_ck: emu_src_ck {
  73                 #clock-cells = <0>;
  74                 compatible = "ti,clkdm-gate-clock";
  75                 clocks = <&emu_src_mux_ck>;
  76         };
  77
  78         dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
  79                 #clock-cells = <0>;
  80                 compatible = "ti,hsdiv-gate-clock";
  81                 clocks = <&dpll4_m2x2_mul_ck>;
  82                 ti,bit-shift = <0x1b>;
  83                 reg = <0x48004d00 0x4>;
  84                 ti,set-bit-to-disable;
  85         };