1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
6 - compatible: shall be "marvell,orion-intc"
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
13 - 0 maps to bit 0 of first base address,
14 - 1 maps to bit 1 of first base address,
15 - 32 maps to bit 0 of second base address, and so on.
18 intc: interrupt-controller {
19 compatible = "marvell,orion-intc";
21 #interrupt-cells = <1>;
22 /* Dove has 64 first level interrupts */
23 reg = <0x20200 0x10>, <0x20210 0x10>;
26 * Bridge interrupt controller
29 - compatible: shall be "marvell,orion-bridge-intc"
30 - reg: base address of bridge interrupt registers starting with CAUSE register
31 - interrupts: bridge interrupt of the main interrupt controller
32 - interrupt-controller: identifies the node as an interrupt controller
33 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
36 - marvell,#interrupts: number of interrupts provided by bridge interrupt
37 controller, defaults to 32 if not set
40 bridge_intc: interrupt-controller {
41 compatible = "marvell,orion-bridge-intc";
43 #interrupt-cells = <1>;
46 /* Dove bridge provides 5 interrupts */
47 marvell,#interrupts = <5>;