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[linux/fpc-iii.git] / Documentation / devicetree / bindings / spi / spi-davinci.txt
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1 Davinci SPI controller device bindings
3 Required properties:
4 - #address-cells: number of cells required to define a chip select
5         address on the SPI bus. Should be set to 1.
6 - #size-cells: should be zero.
7 - compatible:
8         - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
9         - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
10 - reg: Offset and length of SPI controller register space
11 - num-cs: Number of chip selects
12 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
13         IP to the interrupt controller within the SoC. Possible values
14         are 0 and 1. Manual says one of the two possible interrupt
15         lines can be tied to the interrupt controller. Set this
16         based on a specifc SoC configuration.
17 - interrupts: interrupt number mapped to CPU.
18 - clocks: spi clk phandle
20 Example of a NOR flash slave device (n25q032) connected to DaVinci
21 SPI controller device over the SPI bus.
23 spi0:spi@20BF0000 {
24         #address-cells                  = <1>;
25         #size-cells                     = <0>;
26         compatible                      = "ti,dm6446-spi";
27         reg                             = <0x20BF0000 0x1000>;
28         num-cs                          = <4>;
29         ti,davinci-spi-intr-line        = <0>;
30         interrupts                      = <338>;
31         clocks                          = <&clkspi>;
33         flash: n25q032@0 {
34                 #address-cells = <1>;
35                 #size-cells = <1>;
36                 compatible = "st,m25p32";
37                 spi-max-frequency = <25000000>;
38                 reg = <0>;
40                 partition@0 {
41                         label = "u-boot-spl";
42                         reg = <0x0 0x80000>;
43                         read-only;
44                 };
46                 partition@1 {
47                         label = "test";
48                         reg = <0x80000 0x380000>;
49                 };
50         };