1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/smp_plat.h>
26 #include <asm/smp_scu.h>
27 #include <asm/firmware.h>
29 #include <mach/hardware.h>
36 extern void exynos4_secondary_startup(void);
38 static inline void __iomem
*cpu_boot_reg_base(void)
40 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1
)
45 static inline void __iomem
*cpu_boot_reg(int cpu
)
47 void __iomem
*boot_reg
;
49 boot_reg
= cpu_boot_reg_base();
50 if (soc_is_exynos4412())
52 else if (soc_is_exynos5420())
58 * Write pen_release in a way that is guaranteed to be visible to all
59 * observers, irrespective of whether they're taking part in coherency
60 * or not. This is necessary for the hotplug code to work reliably.
62 static void write_pen_release(int val
)
66 sync_cache_w(&pen_release
);
69 static void __iomem
*scu_base_addr(void)
71 return (void __iomem
*)(S5P_VA_SCU
);
74 static DEFINE_SPINLOCK(boot_lock
);
76 static void exynos_secondary_init(unsigned int cpu
)
79 * let the primary processor know we're out of the
80 * pen, then head off into the C entry point
82 write_pen_release(-1);
85 * Synchronise with the boot thread.
87 spin_lock(&boot_lock
);
88 spin_unlock(&boot_lock
);
91 static int exynos_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
93 unsigned long timeout
;
94 unsigned long phys_cpu
= cpu_logical_map(cpu
);
97 * Set synchronisation state between this boot processor
98 * and the secondary one
100 spin_lock(&boot_lock
);
103 * The secondary processor is waiting to be released from
104 * the holding pen - release it, then wait for it to flag
105 * that it has been released by resetting pen_release.
107 * Note that "pen_release" is the hardware CPU ID, whereas
108 * "cpu" is Linux's internal ID.
110 write_pen_release(phys_cpu
);
112 if (!(__raw_readl(S5P_ARM_CORE1_STATUS
) & S5P_CORE_LOCAL_PWR_EN
)) {
113 __raw_writel(S5P_CORE_LOCAL_PWR_EN
,
114 S5P_ARM_CORE1_CONFIGURATION
);
118 /* wait max 10 ms until cpu1 is on */
119 while ((__raw_readl(S5P_ARM_CORE1_STATUS
)
120 & S5P_CORE_LOCAL_PWR_EN
) != S5P_CORE_LOCAL_PWR_EN
) {
128 printk(KERN_ERR
"cpu1 power enable failed");
129 spin_unlock(&boot_lock
);
134 * Send the secondary CPU a soft interrupt, thereby causing
135 * the boot monitor to read the system wide flags register,
136 * and branch to the address found there.
139 timeout
= jiffies
+ (1 * HZ
);
140 while (time_before(jiffies
, timeout
)) {
141 unsigned long boot_addr
;
145 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
148 * Try to set boot address using firmware first
149 * and fall back to boot register if it fails.
151 if (call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
))
152 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
154 call_firmware_op(cpu_boot
, phys_cpu
);
156 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));
158 if (pen_release
== -1)
165 * now the secondary core is starting up let it run its
166 * calibrations, then wait for it to finish
168 spin_unlock(&boot_lock
);
170 return pen_release
!= -1 ? -ENOSYS
: 0;
174 * Initialise the CPU possible map early - this describes the CPUs
175 * which may be present or become present in the system.
178 static void __init
exynos_smp_init_cpus(void)
180 void __iomem
*scu_base
= scu_base_addr();
181 unsigned int i
, ncores
;
183 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
184 ncores
= scu_base
? scu_get_core_count(scu_base
) : 1;
187 * CPU Nodes are passed thru DT and set_cpu_possible
188 * is set by "arm_dt_init_cpu_maps".
193 if (ncores
> nr_cpu_ids
) {
194 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
199 for (i
= 0; i
< ncores
; i
++)
200 set_cpu_possible(i
, true);
203 static void __init
exynos_smp_prepare_cpus(unsigned int max_cpus
)
207 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9
)
208 scu_enable(scu_base_addr());
211 * Write the address of secondary startup into the
212 * system-wide flags register. The boot monitor waits
213 * until it receives a soft interrupt, and then the
214 * secondary CPU branches to this address.
216 * Try using firmware operation first and fall back to
217 * boot register if it fails.
219 for (i
= 1; i
< max_cpus
; ++i
) {
220 unsigned long phys_cpu
;
221 unsigned long boot_addr
;
223 phys_cpu
= cpu_logical_map(i
);
224 boot_addr
= virt_to_phys(exynos4_secondary_startup
);
226 if (call_firmware_op(set_cpu_boot_addr
, phys_cpu
, boot_addr
))
227 __raw_writel(boot_addr
, cpu_boot_reg(phys_cpu
));
231 struct smp_operations exynos_smp_ops __initdata
= {
232 .smp_init_cpus
= exynos_smp_init_cpus
,
233 .smp_prepare_cpus
= exynos_smp_prepare_cpus
,
234 .smp_secondary_init
= exynos_secondary_init
,
235 .smp_boot_secondary
= exynos_boot_secondary
,
236 #ifdef CONFIG_HOTPLUG_CPU
237 .cpu_die
= exynos_cpu_die
,