Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / arch / arm / mach-s5p64x0 / pm.c
blob861e15cea691e62331e293b9639e7d1eb1f07bcb
1 /* linux/arch/arm/mach-s5p64x0/pm.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P64X0 Power Management Support
8 * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/suspend.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/io.h>
19 #include <plat/cpu.h>
20 #include <plat/pm.h>
21 #include <plat/wakeup-mask.h>
23 #include <mach/regs-clock.h>
24 #include <mach/regs-gpio.h>
26 static struct sleep_save s5p64x0_core_save[] = {
27 SAVE_ITEM(S5P64X0_APLL_CON),
28 SAVE_ITEM(S5P64X0_MPLL_CON),
29 SAVE_ITEM(S5P64X0_EPLL_CON),
30 SAVE_ITEM(S5P64X0_EPLL_CON_K),
31 SAVE_ITEM(S5P64X0_CLK_SRC0),
32 SAVE_ITEM(S5P64X0_CLK_SRC1),
33 SAVE_ITEM(S5P64X0_CLK_DIV0),
34 SAVE_ITEM(S5P64X0_CLK_DIV1),
35 SAVE_ITEM(S5P64X0_CLK_DIV2),
36 SAVE_ITEM(S5P64X0_CLK_DIV3),
37 SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
38 SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
39 SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
42 static struct sleep_save s5p64x0_misc_save[] = {
43 SAVE_ITEM(S5P64X0_AHB_CON0),
44 SAVE_ITEM(S5P64X0_SPCON0),
45 SAVE_ITEM(S5P64X0_SPCON1),
46 SAVE_ITEM(S5P64X0_MEM0CONSLP0),
47 SAVE_ITEM(S5P64X0_MEM0CONSLP1),
48 SAVE_ITEM(S5P64X0_MEM0DRVCON),
49 SAVE_ITEM(S5P64X0_MEM1DRVCON),
52 /* DPLL is present only in S5P6450 */
53 static struct sleep_save s5p6450_core_save[] = {
54 SAVE_ITEM(S5P6450_DPLL_CON),
55 SAVE_ITEM(S5P6450_DPLL_CON_K),
58 void s3c_pm_configure_extint(void)
60 __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
63 void s3c_pm_restore_core(void)
65 __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
67 s3c_pm_do_restore_core(s5p64x0_core_save,
68 ARRAY_SIZE(s5p64x0_core_save));
70 if (soc_is_s5p6450())
71 s3c_pm_do_restore_core(s5p6450_core_save,
72 ARRAY_SIZE(s5p6450_core_save));
74 s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
77 void s3c_pm_save_core(void)
79 s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
81 if (soc_is_s5p6450())
82 s3c_pm_do_save(s5p6450_core_save,
83 ARRAY_SIZE(s5p6450_core_save));
85 s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
88 static int s5p64x0_cpu_suspend(unsigned long arg)
90 unsigned long tmp = 0;
93 * Issue the standby signal into the pm unit. Note, we
94 * issue a write-buffer drain just in case.
96 asm("b 1f\n\t"
97 ".align 5\n\t"
98 "1:\n\t"
99 "mcr p15, 0, %0, c7, c10, 5\n\t"
100 "mcr p15, 0, %0, c7, c10, 4\n\t"
101 "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
103 pr_info("Failed to suspend the system\n");
104 return 1; /* Aborting suspend */
107 /* mapping of interrupts to parts of the wakeup mask */
108 static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
109 { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
110 { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
111 { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
112 { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
115 static void s5p64x0_pm_prepare(void)
117 u32 tmp;
119 samsung_sync_wakemask(S5P64X0_PWR_CFG,
120 s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
122 /* store the resume address in INFORM0 register */
123 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
125 /* setup clock gating for FIMGVG block */
126 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
127 (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
128 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
129 (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
131 /* Configure the stabilization counter with wait time required */
132 __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
134 /* set WFI to SLEEP mode configuration */
135 tmp = __raw_readl(S5P64X0_SLEEP_CFG);
136 tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
137 __raw_writel(tmp, S5P64X0_SLEEP_CFG);
139 tmp = __raw_readl(S5P64X0_PWR_CFG);
140 tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
141 tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
142 __raw_writel(tmp, S5P64X0_PWR_CFG);
145 * set OTHERS register to disable interrupt before going to
146 * sleep. This bit is present only in S5P6450, it is reserved
147 * in S5P6440.
149 if (soc_is_s5p6450()) {
150 tmp = __raw_readl(S5P64X0_OTHERS);
151 tmp |= S5P6450_OTHERS_DISABLE_INT;
152 __raw_writel(tmp, S5P64X0_OTHERS);
155 /* ensure previous wakeup state is cleared before sleeping */
156 __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
160 static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
162 pm_cpu_prep = s5p64x0_pm_prepare;
163 pm_cpu_sleep = s5p64x0_cpu_suspend;
164 pm_uart_udivslot = 1;
166 return 0;
169 static struct subsys_interface s5p64x0_pm_interface = {
170 .name = "s5p64x0_pm",
171 .subsys = &s5p64x0_subsys,
172 .add_dev = s5p64x0_pm_add,
175 static __init int s5p64x0_pm_drvinit(void)
177 s3c_pm_init();
179 return subsys_interface_register(&s5p64x0_pm_interface);
181 arch_initcall(s5p64x0_pm_drvinit);
183 static void s5p64x0_pm_resume(void)
185 u32 tmp;
187 tmp = __raw_readl(S5P64X0_OTHERS);
188 tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
189 S5P64X0_OTHERS_RET_UART);
190 __raw_writel(tmp , S5P64X0_OTHERS);
193 static struct syscore_ops s5p64x0_pm_syscore_ops = {
194 .resume = s5p64x0_pm_resume,
197 static __init int s5p64x0_pm_syscore_init(void)
199 register_syscore_ops(&s5p64x0_pm_syscore_ops);
201 return 0;
203 arch_initcall(s5p64x0_pm_syscore_init);