2 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 #include <linux/linkage.h>
18 #include <linux/init.h>
20 #include <asm/cache.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/hardware/cache-l2x0.h>
30 #define PMC_SCRATCH41 0x140
32 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
34 #ifdef CONFIG_PM_SLEEP
38 * CPU boot vector when restarting the a CPU following
39 * an LP2 transition. Also branched to by LP0 and LP1 resume after
46 check_cpu_part_num 0xc09, r8, r9
54 /* Are we on Tegra20? */
57 /* Clear the flow controller flags for this CPU. */
59 mov32 r2, TEGRA_FLOW_CTRL_BASE
61 /* Clear event & intr flag */
63 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
64 movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps
65 @ & ext flags for CPU power mgnt
72 bne end_ca9_scu_l2_resume
73 #ifdef CONFIG_HAVE_ARM_SCU
75 mov32 r0, TEGRA_ARM_PERIF_BASE
81 /* L2 cache resume & re-enable */
82 l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
83 end_ca9_scu_l2_resume:
86 bleq tegra_init_l2_for_a15
92 #ifdef CONFIG_CACHE_L2X0
93 .globl l2x0_saved_regs_addr
99 ENTRY(__tegra_cpu_reset_handler_start)
102 * __tegra_cpu_reset_handler:
104 * Common handler for all CPU reset events.
106 * Register usage within the reset handler:
110 * R7 = CPU present (to the OS) mask
111 * R8 = CPU in LP1 state mask
112 * R9 = CPU in LP2 state mask
115 * R12 = pointer to reset handler data
117 * NOTE: This code is copied to IRAM. All code and data accesses
118 * must be position-independent.
121 .align L1_CACHE_SHIFT
122 ENTRY(__tegra_cpu_reset_handler)
124 cpsid aif, 0x13 @ SVC mode, interrupts disabled
126 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
127 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
132 # Tegra20 is a Cortex-A9 r1p1
133 mrc p15, 0, r0, c1, c0, 0 @ read system control register
134 orr r0, r0, #1 << 14 @ erratum 716044
135 mcr p15, 0, r0, c1, c0, 0 @ write system control register
136 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
137 orr r0, r0, #1 << 4 @ erratum 742230
138 orr r0, r0, #1 << 11 @ erratum 751472
139 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
143 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
148 # Tegra30 is a Cortex-A9 r2p9
149 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
150 orr r0, r0, #1 << 6 @ erratum 743622
151 orr r0, r0, #1 << 11 @ erratum 751472
152 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
157 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
158 and r10, r10, #0x3 @ R10 = CPU number
160 mov r11, r11, lsl r10 @ R11 = CPU mask
161 adr r12, __tegra_cpu_reset_handler_data
164 /* Does the OS know about this CPU? */
165 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
166 tst r7, r11 @ if !present
167 bleq __die @ CPU not present (to OS)
170 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
171 /* Are we on Tegra20? */
174 /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
175 mov32 r5, TEGRA_PMC_BASE
178 strne r0, [r5, #PMC_SCRATCH41]
182 /* Waking up from LP1? */
183 ldr r8, [r12, #RESET_DATA(MASK_LP1)]
184 tst r8, r11 @ if in_lp1
187 bne __die @ only CPU0 can be here
188 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
190 bleq __die @ no LP1 startup handler
191 THUMB( add lr, lr, #1 ) @ switch to Thumb mode
195 /* Waking up from LP2? */
196 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
197 tst r9, r11 @ if in_lp2
199 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
201 bleq __die @ no LP2 startup handler
208 * Can only be secondary boot (initial or hotplug)
209 * CPU0 can't be here for Tegra20/30
214 bleq __die @ CPU0 cannot be here
216 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
218 bleq __die @ no secondary startup handler
223 * We don't know why the CPU reset. Just kill it.
224 * The LR register will contain the address we died at + 4.
229 mov32 r7, TEGRA_PMC_BASE
230 str lr, [r7, #PMC_SCRATCH41]
232 mov32 r7, TEGRA_CLK_RESET_BASE
234 /* Are we on Tegra20? */
238 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
241 str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
244 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
245 mov32 r6, TEGRA_FLOW_CTRL_BASE
248 moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
249 moveq r2, #FLOW_CTRL_CPU0_CSR
250 movne r1, r10, lsl #3
251 addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
252 addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
254 /* Clear CPU "event" and "interrupt" flags and power gate
255 it when halting but not before it is in the "WFI" state. */
257 orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
258 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
261 /* Unconditionally halt this CPU */
262 mov r0, #FLOW_CTRL_WAITEVENT
264 ldr r0, [r6, +r1] @ memory barrier
268 wfi @ CPU should be power gated here
270 /* If the CPU didn't power gate above just kill it's clock. */
273 str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
276 /* If the CPU still isn't dead, just spin here. */
278 ENDPROC(__tegra_cpu_reset_handler)
280 .align L1_CACHE_SHIFT
281 .type __tegra_cpu_reset_handler_data, %object
282 .globl __tegra_cpu_reset_handler_data
283 __tegra_cpu_reset_handler_data:
284 .rept TEGRA_RESET_DATA_SIZE
287 .align L1_CACHE_SHIFT
289 ENTRY(__tegra_cpu_reset_handler_end)