2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
10 #include <linux/interrupt.h>
11 #include <linux/ioport.h>
12 #include <linux/sched.h>
13 #include <linux/irqdomain.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
18 #include <asm/bootinfo.h>
19 #include <asm/irq_cpu.h>
21 #include <lantiq_soc.h>
24 /* register definitions - internal irqs */
25 #define LTQ_ICU_IM0_ISR 0x0000
26 #define LTQ_ICU_IM0_IER 0x0008
27 #define LTQ_ICU_IM0_IOSR 0x0010
28 #define LTQ_ICU_IM0_IRSR 0x0018
29 #define LTQ_ICU_IM0_IMR 0x0020
30 #define LTQ_ICU_IM1_ISR 0x0028
31 #define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
33 /* register definitions - external irqs */
34 #define LTQ_EIU_EXIN_C 0x0000
35 #define LTQ_EIU_EXIN_INIC 0x0004
36 #define LTQ_EIU_EXIN_INC 0x0008
37 #define LTQ_EIU_EXIN_INEN 0x000C
39 /* number of external interrupts */
42 /* the performance counter */
43 #define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
46 * irqs generated by devices attached to the EBU need to be acked in
49 #define LTQ_ICU_EBU_IRQ 22
51 #define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
52 #define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
54 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
55 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
57 /* our 2 ipi interrupts for VSMP */
58 #define MIPS_CPU_IPI_RESCHED_IRQ 0
59 #define MIPS_CPU_IPI_CALL_IRQ 1
61 /* we have a cascade of 8 irqs */
62 #define MIPS_CPU_IRQ_CASCADE 8
64 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
68 static int exin_avail
;
69 static struct resource ltq_eiu_irq
[MAX_EIU
];
70 static void __iomem
*ltq_icu_membase
[MAX_IM
];
71 static void __iomem
*ltq_eiu_membase
;
72 static struct irq_domain
*ltq_domain
;
74 int ltq_eiu_get_irq(int exin
)
76 if (exin
< exin_avail
)
77 return ltq_eiu_irq
[exin
].start
;
81 void ltq_disable_irq(struct irq_data
*d
)
83 u32 ier
= LTQ_ICU_IM0_IER
;
84 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
85 int im
= offset
/ INT_NUM_IM_OFFSET
;
87 offset
%= INT_NUM_IM_OFFSET
;
88 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) & ~BIT(offset
), ier
);
91 void ltq_mask_and_ack_irq(struct irq_data
*d
)
93 u32 ier
= LTQ_ICU_IM0_IER
;
94 u32 isr
= LTQ_ICU_IM0_ISR
;
95 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
96 int im
= offset
/ INT_NUM_IM_OFFSET
;
98 offset
%= INT_NUM_IM_OFFSET
;
99 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) & ~BIT(offset
), ier
);
100 ltq_icu_w32(im
, BIT(offset
), isr
);
103 static void ltq_ack_irq(struct irq_data
*d
)
105 u32 isr
= LTQ_ICU_IM0_ISR
;
106 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
107 int im
= offset
/ INT_NUM_IM_OFFSET
;
109 offset
%= INT_NUM_IM_OFFSET
;
110 ltq_icu_w32(im
, BIT(offset
), isr
);
113 void ltq_enable_irq(struct irq_data
*d
)
115 u32 ier
= LTQ_ICU_IM0_IER
;
116 int offset
= d
->hwirq
- MIPS_CPU_IRQ_CASCADE
;
117 int im
= offset
/ INT_NUM_IM_OFFSET
;
119 offset
%= INT_NUM_IM_OFFSET
;
120 ltq_icu_w32(im
, ltq_icu_r32(im
, ier
) | BIT(offset
), ier
);
123 static int ltq_eiu_settype(struct irq_data
*d
, unsigned int type
)
127 for (i
= 0; i
< MAX_EIU
; i
++) {
128 if (d
->hwirq
== ltq_eiu_irq
[i
].start
) {
133 case IRQF_TRIGGER_NONE
:
135 case IRQF_TRIGGER_RISING
:
139 case IRQF_TRIGGER_FALLING
:
143 case IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
:
147 case IRQF_TRIGGER_HIGH
:
150 case IRQF_TRIGGER_LOW
:
154 pr_err("invalid type %d for irq %ld\n",
160 irq_set_handler(d
->hwirq
, handle_edge_irq
);
162 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C
) |
163 (val
<< (i
* 4)), LTQ_EIU_EXIN_C
);
170 static unsigned int ltq_startup_eiu_irq(struct irq_data
*d
)
175 for (i
= 0; i
< MAX_EIU
; i
++) {
176 if (d
->hwirq
== ltq_eiu_irq
[i
].start
) {
177 /* by default we are low level triggered */
178 ltq_eiu_settype(d
, IRQF_TRIGGER_LOW
);
179 /* clear all pending */
180 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC
) & ~BIT(i
),
183 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) | BIT(i
),
192 static void ltq_shutdown_eiu_irq(struct irq_data
*d
)
197 for (i
= 0; i
< MAX_EIU
; i
++) {
198 if (d
->hwirq
== ltq_eiu_irq
[i
].start
) {
200 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN
) & ~BIT(i
),
207 static struct irq_chip ltq_irq_type
= {
209 .irq_enable
= ltq_enable_irq
,
210 .irq_disable
= ltq_disable_irq
,
211 .irq_unmask
= ltq_enable_irq
,
212 .irq_ack
= ltq_ack_irq
,
213 .irq_mask
= ltq_disable_irq
,
214 .irq_mask_ack
= ltq_mask_and_ack_irq
,
217 static struct irq_chip ltq_eiu_type
= {
219 .irq_startup
= ltq_startup_eiu_irq
,
220 .irq_shutdown
= ltq_shutdown_eiu_irq
,
221 .irq_enable
= ltq_enable_irq
,
222 .irq_disable
= ltq_disable_irq
,
223 .irq_unmask
= ltq_enable_irq
,
224 .irq_ack
= ltq_ack_irq
,
225 .irq_mask
= ltq_disable_irq
,
226 .irq_mask_ack
= ltq_mask_and_ack_irq
,
227 .irq_set_type
= ltq_eiu_settype
,
230 static void ltq_hw_irqdispatch(int module
)
234 irq
= ltq_icu_r32(module
, LTQ_ICU_IM0_IOSR
);
239 * silicon bug causes only the msb set to 1 to be valid. all
240 * other bits might be bogus
243 do_IRQ((int)irq
+ MIPS_CPU_IRQ_CASCADE
+ (INT_NUM_IM_OFFSET
* module
));
245 /* if this is a EBU irq, we need to ack it or get a deadlock */
246 if ((irq
== LTQ_ICU_EBU_IRQ
) && (module
== 0) && LTQ_EBU_PCC_ISTAT
)
247 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT
) | 0x10,
251 #define DEFINE_HWx_IRQDISPATCH(x) \
252 static void ltq_hw ## x ## _irqdispatch(void) \
254 ltq_hw_irqdispatch(x); \
256 DEFINE_HWx_IRQDISPATCH(0)
257 DEFINE_HWx_IRQDISPATCH(1)
258 DEFINE_HWx_IRQDISPATCH(2)
259 DEFINE_HWx_IRQDISPATCH(3)
260 DEFINE_HWx_IRQDISPATCH(4)
262 #if MIPS_CPU_TIMER_IRQ == 7
263 static void ltq_hw5_irqdispatch(void)
265 do_IRQ(MIPS_CPU_TIMER_IRQ
);
268 DEFINE_HWx_IRQDISPATCH(5)
271 #ifdef CONFIG_MIPS_MT_SMP
272 void __init
arch_init_ipiirq(int irq
, struct irqaction
*action
)
274 setup_irq(irq
, action
);
275 irq_set_handler(irq
, handle_percpu_irq
);
278 static void ltq_sw0_irqdispatch(void)
280 do_IRQ(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_RESCHED_IRQ
);
283 static void ltq_sw1_irqdispatch(void)
285 do_IRQ(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_CALL_IRQ
);
287 static irqreturn_t
ipi_resched_interrupt(int irq
, void *dev_id
)
293 static irqreturn_t
ipi_call_interrupt(int irq
, void *dev_id
)
295 smp_call_function_interrupt();
299 static struct irqaction irq_resched
= {
300 .handler
= ipi_resched_interrupt
,
301 .flags
= IRQF_PERCPU
,
302 .name
= "IPI_resched"
305 static struct irqaction irq_call
= {
306 .handler
= ipi_call_interrupt
,
307 .flags
= IRQF_PERCPU
,
312 asmlinkage
void plat_irq_dispatch(void)
314 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
317 if ((MIPS_CPU_TIMER_IRQ
== 7) && (pending
& CAUSEF_IP7
)) {
318 do_IRQ(MIPS_CPU_TIMER_IRQ
);
321 for (i
= 0; i
< MAX_IM
; i
++) {
322 if (pending
& (CAUSEF_IP2
<< i
)) {
323 ltq_hw_irqdispatch(i
);
328 pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
334 static int icu_map(struct irq_domain
*d
, unsigned int irq
, irq_hw_number_t hw
)
336 struct irq_chip
*chip
= <q_irq_type
;
339 if (hw
< MIPS_CPU_IRQ_CASCADE
)
342 for (i
= 0; i
< exin_avail
; i
++)
343 if (hw
== ltq_eiu_irq
[i
].start
)
344 chip
= <q_eiu_type
;
346 irq_set_chip_and_handler(hw
, chip
, handle_level_irq
);
351 static const struct irq_domain_ops irq_domain_ops
= {
352 .xlate
= irq_domain_xlate_onetwocell
,
356 static struct irqaction cascade
= {
357 .handler
= no_action
,
361 int __init
icu_of_init(struct device_node
*node
, struct device_node
*parent
)
363 struct device_node
*eiu_node
;
367 for (i
= 0; i
< MAX_IM
; i
++) {
368 if (of_address_to_resource(node
, i
, &res
))
369 panic("Failed to get icu memory range");
371 if (request_mem_region(res
.start
, resource_size(&res
),
373 pr_err("Failed to request icu memory");
375 ltq_icu_membase
[i
] = ioremap_nocache(res
.start
,
376 resource_size(&res
));
377 if (!ltq_icu_membase
[i
])
378 panic("Failed to remap icu memory");
381 /* the external interrupts are optional and xway only */
382 eiu_node
= of_find_compatible_node(NULL
, NULL
, "lantiq,eiu-xway");
383 if (eiu_node
&& !of_address_to_resource(eiu_node
, 0, &res
)) {
384 /* find out how many external irq sources we have */
385 exin_avail
= of_irq_count(eiu_node
);
387 if (exin_avail
> MAX_EIU
)
388 exin_avail
= MAX_EIU
;
390 ret
= of_irq_to_resource_table(eiu_node
,
391 ltq_eiu_irq
, exin_avail
);
392 if (ret
!= exin_avail
)
393 panic("failed to load external irq resources");
395 if (request_mem_region(res
.start
, resource_size(&res
),
397 pr_err("Failed to request eiu memory");
399 ltq_eiu_membase
= ioremap_nocache(res
.start
,
400 resource_size(&res
));
401 if (!ltq_eiu_membase
)
402 panic("Failed to remap eiu memory");
405 /* turn off all irqs by default */
406 for (i
= 0; i
< MAX_IM
; i
++) {
407 /* make sure all irqs are turned off by default */
408 ltq_icu_w32(i
, 0, LTQ_ICU_IM0_IER
);
409 /* clear all possibly pending interrupts */
410 ltq_icu_w32(i
, ~0, LTQ_ICU_IM0_ISR
);
415 for (i
= 0; i
< MAX_IM
; i
++)
416 setup_irq(i
+ 2, &cascade
);
419 pr_info("Setting up vectored interrupts\n");
420 set_vi_handler(2, ltq_hw0_irqdispatch
);
421 set_vi_handler(3, ltq_hw1_irqdispatch
);
422 set_vi_handler(4, ltq_hw2_irqdispatch
);
423 set_vi_handler(5, ltq_hw3_irqdispatch
);
424 set_vi_handler(6, ltq_hw4_irqdispatch
);
425 set_vi_handler(7, ltq_hw5_irqdispatch
);
428 ltq_domain
= irq_domain_add_linear(node
,
429 (MAX_IM
* INT_NUM_IM_OFFSET
) + MIPS_CPU_IRQ_CASCADE
,
432 #if defined(CONFIG_MIPS_MT_SMP)
434 pr_info("Setting up IPI vectored interrupts\n");
435 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ
, ltq_sw0_irqdispatch
);
436 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ
, ltq_sw1_irqdispatch
);
438 arch_init_ipiirq(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_RESCHED_IRQ
,
440 arch_init_ipiirq(MIPS_CPU_IRQ_BASE
+ MIPS_CPU_IPI_CALL_IRQ
, &irq_call
);
443 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
444 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
445 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
447 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
448 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
451 /* tell oprofile which irq to use */
452 cp0_perfcount_irq
= irq_create_mapping(ltq_domain
, LTQ_PERF_IRQ
);
455 * if the timer irq is not one of the mips irqs we need to
458 if (MIPS_CPU_TIMER_IRQ
!= 7)
459 irq_create_mapping(ltq_domain
, MIPS_CPU_TIMER_IRQ
);
464 unsigned int get_c0_compare_int(void)
466 return MIPS_CPU_TIMER_IRQ
;
469 static struct of_device_id __initdata of_irq_ids
[] = {
470 { .compatible
= "lantiq,icu", .data
= icu_of_init
},
474 void __init
arch_init_irq(void)
476 of_irq_init(of_irq_ids
);