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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[linux/fpc-iii.git] / arch / mips / math-emu / cp1emu.c
blob506925b2c3f366a12aecfb8ecc3cf6d69274654d
1 /*
2 * cp1emu.c: a MIPS coprocessor 1 (fpu) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
26 *
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware fpu at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
32 *
33 * Note if you know that you won't have an fpu, then you'll get much
34 * better performance by compiling with -msoft-float!
35 */
36 #include <linux/sched.h>
37 #include <linux/module.h>
38 #include <linux/debugfs.h>
39 #include <linux/perf_event.h>
40
41 #include <asm/inst.h>
42 #include <asm/bootinfo.h>
43 #include <asm/processor.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/mipsregs.h>
47 #include <asm/fpu_emulator.h>
48 #include <asm/fpu.h>
49 #include <asm/uaccess.h>
50 #include <asm/branch.h>
51
52 #include "ieee754.h"
53
54 /* Strap kernel emulator for full MIPS IV emulation */
55
56 #ifdef __mips
57 #undef __mips
58 #endif
59 #define __mips 4
60
61 /* Function which emulates a floating point instruction. */
62
63 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
64 mips_instruction);
65
66 #if __mips >= 4 && __mips != 32
67 static int fpux_emu(struct pt_regs *,
68 struct mips_fpu_struct *, mips_instruction, void *__user *);
69 #endif
70
71 /* Further private data for which no space exists in mips_fpu_struct */
72
73 #ifdef CONFIG_DEBUG_FS
74 DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
75 #endif
76
77 /* Control registers */
78
79 #define FPCREG_RID 0 /* $0 = revision id */
80 #define FPCREG_CSR 31 /* $31 = csr */
81
82 /* Determine rounding mode from the RM bits of the FCSR */
83 #define modeindex(v) ((v) & FPU_CSR_RM)
84
85 /* microMIPS bitfields */
86 #define MM_POOL32A_MINOR_MASK 0x3f
87 #define MM_POOL32A_MINOR_SHIFT 0x6
88 #define MM_MIPS32_COND_FC 0x30
89
90 /* Convert Mips rounding mode (0..3) to IEEE library modes. */
91 static const unsigned char ieee_rm[4] = {
92 [FPU_CSR_RN] = IEEE754_RN,
93 [FPU_CSR_RZ] = IEEE754_RZ,
94 [FPU_CSR_RU] = IEEE754_RU,
95 [FPU_CSR_RD] = IEEE754_RD,
96 };
97 /* Convert IEEE library modes to Mips rounding mode (0..3). */
98 static const unsigned char mips_rm[4] = {
99 [IEEE754_RN] = FPU_CSR_RN,
100 [IEEE754_RZ] = FPU_CSR_RZ,
101 [IEEE754_RD] = FPU_CSR_RD,
102 [IEEE754_RU] = FPU_CSR_RU,
103 };
104
105 #if __mips >= 4
106 /* convert condition code register number to csr bit */
107 static const unsigned int fpucondbit[8] = {
108 FPU_CSR_COND0,
109 FPU_CSR_COND1,
110 FPU_CSR_COND2,
111 FPU_CSR_COND3,
112 FPU_CSR_COND4,
113 FPU_CSR_COND5,
114 FPU_CSR_COND6,
115 FPU_CSR_COND7
116 };
117 #endif
118
119 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
120 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
121
122 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
123 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
124 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
125 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
126 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
127
128 /*
129 * This functions translates a 32-bit microMIPS instruction
130 * into a 32-bit MIPS32 instruction. Returns 0 on success
131 * and SIGILL otherwise.
132 */
133 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
134 {
135 union mips_instruction insn = *insn_ptr;
136 union mips_instruction mips32_insn = insn;
137 int func, fmt, op;
138
139 switch (insn.mm_i_format.opcode) {
140 case mm_ldc132_op:
141 mips32_insn.mm_i_format.opcode = ldc1_op;
142 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
143 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
144 break;
145 case mm_lwc132_op:
146 mips32_insn.mm_i_format.opcode = lwc1_op;
147 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
148 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
149 break;
150 case mm_sdc132_op:
151 mips32_insn.mm_i_format.opcode = sdc1_op;
152 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
153 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
154 break;
155 case mm_swc132_op:
156 mips32_insn.mm_i_format.opcode = swc1_op;
157 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
158 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
159 break;
160 case mm_pool32i_op:
161 /* NOTE: offset is << by 1 if in microMIPS mode. */
162 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
163 (insn.mm_i_format.rt == mm_bc1t_op)) {
164 mips32_insn.fb_format.opcode = cop1_op;
165 mips32_insn.fb_format.bc = bc_op;
166 mips32_insn.fb_format.flag =
167 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
168 } else
169 return SIGILL;
170 break;
171 case mm_pool32f_op:
172 switch (insn.mm_fp0_format.func) {
173 case mm_32f_01_op:
174 case mm_32f_11_op:
175 case mm_32f_02_op:
176 case mm_32f_12_op:
177 case mm_32f_41_op:
178 case mm_32f_51_op:
179 case mm_32f_42_op:
180 case mm_32f_52_op:
181 op = insn.mm_fp0_format.func;
182 if (op == mm_32f_01_op)
183 func = madd_s_op;
184 else if (op == mm_32f_11_op)
185 func = madd_d_op;
186 else if (op == mm_32f_02_op)
187 func = nmadd_s_op;
188 else if (op == mm_32f_12_op)
189 func = nmadd_d_op;
190 else if (op == mm_32f_41_op)
191 func = msub_s_op;
192 else if (op == mm_32f_51_op)
193 func = msub_d_op;
194 else if (op == mm_32f_42_op)
195 func = nmsub_s_op;
196 else
197 func = nmsub_d_op;
198 mips32_insn.fp6_format.opcode = cop1x_op;
199 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
200 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
201 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
202 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
203 mips32_insn.fp6_format.func = func;
204 break;
205 case mm_32f_10_op:
206 func = -1; /* Invalid */
207 op = insn.mm_fp5_format.op & 0x7;
208 if (op == mm_ldxc1_op)
209 func = ldxc1_op;
210 else if (op == mm_sdxc1_op)
211 func = sdxc1_op;
212 else if (op == mm_lwxc1_op)
213 func = lwxc1_op;
214 else if (op == mm_swxc1_op)
215 func = swxc1_op;
216
217 if (func != -1) {
218 mips32_insn.r_format.opcode = cop1x_op;
219 mips32_insn.r_format.rs =
220 insn.mm_fp5_format.base;
221 mips32_insn.r_format.rt =
222 insn.mm_fp5_format.index;
223 mips32_insn.r_format.rd = 0;
224 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
225 mips32_insn.r_format.func = func;
226 } else
227 return SIGILL;
228 break;
229 case mm_32f_40_op:
230 op = -1; /* Invalid */
231 if (insn.mm_fp2_format.op == mm_fmovt_op)
232 op = 1;
233 else if (insn.mm_fp2_format.op == mm_fmovf_op)
234 op = 0;
235 if (op != -1) {
236 mips32_insn.fp0_format.opcode = cop1_op;
237 mips32_insn.fp0_format.fmt =
238 sdps_format[insn.mm_fp2_format.fmt];
239 mips32_insn.fp0_format.ft =
240 (insn.mm_fp2_format.cc<<2) + op;
241 mips32_insn.fp0_format.fs =
242 insn.mm_fp2_format.fs;
243 mips32_insn.fp0_format.fd =
244 insn.mm_fp2_format.fd;
245 mips32_insn.fp0_format.func = fmovc_op;
246 } else
247 return SIGILL;
248 break;
249 case mm_32f_60_op:
250 func = -1; /* Invalid */
251 if (insn.mm_fp0_format.op == mm_fadd_op)
252 func = fadd_op;
253 else if (insn.mm_fp0_format.op == mm_fsub_op)
254 func = fsub_op;
255 else if (insn.mm_fp0_format.op == mm_fmul_op)
256 func = fmul_op;
257 else if (insn.mm_fp0_format.op == mm_fdiv_op)
258 func = fdiv_op;
259 if (func != -1) {
260 mips32_insn.fp0_format.opcode = cop1_op;
261 mips32_insn.fp0_format.fmt =
262 sdps_format[insn.mm_fp0_format.fmt];
263 mips32_insn.fp0_format.ft =
264 insn.mm_fp0_format.ft;
265 mips32_insn.fp0_format.fs =
266 insn.mm_fp0_format.fs;
267 mips32_insn.fp0_format.fd =
268 insn.mm_fp0_format.fd;
269 mips32_insn.fp0_format.func = func;
270 } else
271 return SIGILL;
272 break;
273 case mm_32f_70_op:
274 func = -1; /* Invalid */
275 if (insn.mm_fp0_format.op == mm_fmovn_op)
276 func = fmovn_op;
277 else if (insn.mm_fp0_format.op == mm_fmovz_op)
278 func = fmovz_op;
279 if (func != -1) {
280 mips32_insn.fp0_format.opcode = cop1_op;
281 mips32_insn.fp0_format.fmt =
282 sdps_format[insn.mm_fp0_format.fmt];
283 mips32_insn.fp0_format.ft =
284 insn.mm_fp0_format.ft;
285 mips32_insn.fp0_format.fs =
286 insn.mm_fp0_format.fs;
287 mips32_insn.fp0_format.fd =
288 insn.mm_fp0_format.fd;
289 mips32_insn.fp0_format.func = func;
290 } else
291 return SIGILL;
292 break;
293 case mm_32f_73_op: /* POOL32FXF */
294 switch (insn.mm_fp1_format.op) {
295 case mm_movf0_op:
296 case mm_movf1_op:
297 case mm_movt0_op:
298 case mm_movt1_op:
299 if ((insn.mm_fp1_format.op & 0x7f) ==
300 mm_movf0_op)
301 op = 0;
302 else
303 op = 1;
304 mips32_insn.r_format.opcode = spec_op;
305 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
306 mips32_insn.r_format.rt =
307 (insn.mm_fp4_format.cc << 2) + op;
308 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
309 mips32_insn.r_format.re = 0;
310 mips32_insn.r_format.func = movc_op;
311 break;
312 case mm_fcvtd0_op:
313 case mm_fcvtd1_op:
314 case mm_fcvts0_op:
315 case mm_fcvts1_op:
316 if ((insn.mm_fp1_format.op & 0x7f) ==
317 mm_fcvtd0_op) {
318 func = fcvtd_op;
319 fmt = swl_format[insn.mm_fp3_format.fmt];
320 } else {
321 func = fcvts_op;
322 fmt = dwl_format[insn.mm_fp3_format.fmt];
323 }
324 mips32_insn.fp0_format.opcode = cop1_op;
325 mips32_insn.fp0_format.fmt = fmt;
326 mips32_insn.fp0_format.ft = 0;
327 mips32_insn.fp0_format.fs =
328 insn.mm_fp3_format.fs;
329 mips32_insn.fp0_format.fd =
330 insn.mm_fp3_format.rt;
331 mips32_insn.fp0_format.func = func;
332 break;
333 case mm_fmov0_op:
334 case mm_fmov1_op:
335 case mm_fabs0_op:
336 case mm_fabs1_op:
337 case mm_fneg0_op:
338 case mm_fneg1_op:
339 if ((insn.mm_fp1_format.op & 0x7f) ==
340 mm_fmov0_op)
341 func = fmov_op;
342 else if ((insn.mm_fp1_format.op & 0x7f) ==
343 mm_fabs0_op)
344 func = fabs_op;
345 else
346 func = fneg_op;
347 mips32_insn.fp0_format.opcode = cop1_op;
348 mips32_insn.fp0_format.fmt =
349 sdps_format[insn.mm_fp3_format.fmt];
350 mips32_insn.fp0_format.ft = 0;
351 mips32_insn.fp0_format.fs =
352 insn.mm_fp3_format.fs;
353 mips32_insn.fp0_format.fd =
354 insn.mm_fp3_format.rt;
355 mips32_insn.fp0_format.func = func;
356 break;
357 case mm_ffloorl_op:
358 case mm_ffloorw_op:
359 case mm_fceill_op:
360 case mm_fceilw_op:
361 case mm_ftruncl_op:
362 case mm_ftruncw_op:
363 case mm_froundl_op:
364 case mm_froundw_op:
365 case mm_fcvtl_op:
366 case mm_fcvtw_op:
367 if (insn.mm_fp1_format.op == mm_ffloorl_op)
368 func = ffloorl_op;
369 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
370 func = ffloor_op;
371 else if (insn.mm_fp1_format.op == mm_fceill_op)
372 func = fceill_op;
373 else if (insn.mm_fp1_format.op == mm_fceilw_op)
374 func = fceil_op;
375 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
376 func = ftruncl_op;
377 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
378 func = ftrunc_op;
379 else if (insn.mm_fp1_format.op == mm_froundl_op)
380 func = froundl_op;
381 else if (insn.mm_fp1_format.op == mm_froundw_op)
382 func = fround_op;
383 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
384 func = fcvtl_op;
385 else
386 func = fcvtw_op;
387 mips32_insn.fp0_format.opcode = cop1_op;
388 mips32_insn.fp0_format.fmt =
389 sd_format[insn.mm_fp1_format.fmt];
390 mips32_insn.fp0_format.ft = 0;
391 mips32_insn.fp0_format.fs =
392 insn.mm_fp1_format.fs;
393 mips32_insn.fp0_format.fd =
394 insn.mm_fp1_format.rt;
395 mips32_insn.fp0_format.func = func;
396 break;
397 case mm_frsqrt_op:
398 case mm_fsqrt_op:
399 case mm_frecip_op:
400 if (insn.mm_fp1_format.op == mm_frsqrt_op)
401 func = frsqrt_op;
402 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
403 func = fsqrt_op;
404 else
405 func = frecip_op;
406 mips32_insn.fp0_format.opcode = cop1_op;
407 mips32_insn.fp0_format.fmt =
408 sdps_format[insn.mm_fp1_format.fmt];
409 mips32_insn.fp0_format.ft = 0;
410 mips32_insn.fp0_format.fs =
411 insn.mm_fp1_format.fs;
412 mips32_insn.fp0_format.fd =
413 insn.mm_fp1_format.rt;
414 mips32_insn.fp0_format.func = func;
415 break;
416 case mm_mfc1_op:
417 case mm_mtc1_op:
418 case mm_cfc1_op:
419 case mm_ctc1_op:
420 case mm_mfhc1_op:
421 case mm_mthc1_op:
422 if (insn.mm_fp1_format.op == mm_mfc1_op)
423 op = mfc_op;
424 else if (insn.mm_fp1_format.op == mm_mtc1_op)
425 op = mtc_op;
426 else if (insn.mm_fp1_format.op == mm_cfc1_op)
427 op = cfc_op;
428 else if (insn.mm_fp1_format.op == mm_ctc1_op)
429 op = ctc_op;
430 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
431 op = mfhc_op;
432 else
433 op = mthc_op;
434 mips32_insn.fp1_format.opcode = cop1_op;
435 mips32_insn.fp1_format.op = op;
436 mips32_insn.fp1_format.rt =
437 insn.mm_fp1_format.rt;
438 mips32_insn.fp1_format.fs =
439 insn.mm_fp1_format.fs;
440 mips32_insn.fp1_format.fd = 0;
441 mips32_insn.fp1_format.func = 0;
442 break;
443 default:
444 return SIGILL;
445 }
446 break;
447 case mm_32f_74_op: /* c.cond.fmt */
448 mips32_insn.fp0_format.opcode = cop1_op;
449 mips32_insn.fp0_format.fmt =
450 sdps_format[insn.mm_fp4_format.fmt];
451 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
452 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
453 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
454 mips32_insn.fp0_format.func =
455 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
456 break;
457 default:
458 return SIGILL;
459 }
460 break;
461 default:
462 return SIGILL;
463 }
464
465 *insn_ptr = mips32_insn;
466 return 0;
467 }
468
469 int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
470 unsigned long *contpc)
471 {
472 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
473 int bc_false = 0;
474 unsigned int fcr31;
475 unsigned int bit;
476
477 if (!cpu_has_mmips)
478 return 0;
479
480 switch (insn.mm_i_format.opcode) {
481 case mm_pool32a_op:
482 if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
483 mm_pool32axf_op) {
484 switch (insn.mm_i_format.simmediate >>
485 MM_POOL32A_MINOR_SHIFT) {
486 case mm_jalr_op:
487 case mm_jalrhb_op:
488 case mm_jalrs_op:
489 case mm_jalrshb_op:
490 if (insn.mm_i_format.rt != 0) /* Not mm_jr */
491 regs->regs[insn.mm_i_format.rt] =
492 regs->cp0_epc +
493 dec_insn.pc_inc +
494 dec_insn.next_pc_inc;
495 *contpc = regs->regs[insn.mm_i_format.rs];
496 return 1;
497 }
498 }
499 break;
500 case mm_pool32i_op:
501 switch (insn.mm_i_format.rt) {
502 case mm_bltzals_op:
503 case mm_bltzal_op:
504 regs->regs[31] = regs->cp0_epc +
505 dec_insn.pc_inc +
506 dec_insn.next_pc_inc;
507 /* Fall through */
508 case mm_bltz_op:
509 if ((long)regs->regs[insn.mm_i_format.rs] < 0)
510 *contpc = regs->cp0_epc +
511 dec_insn.pc_inc +
512 (insn.mm_i_format.simmediate << 1);
513 else
514 *contpc = regs->cp0_epc +
515 dec_insn.pc_inc +
516 dec_insn.next_pc_inc;
517 return 1;
518 case mm_bgezals_op:
519 case mm_bgezal_op:
520 regs->regs[31] = regs->cp0_epc +
521 dec_insn.pc_inc +
522 dec_insn.next_pc_inc;
523 /* Fall through */
524 case mm_bgez_op:
525 if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
526 *contpc = regs->cp0_epc +
527 dec_insn.pc_inc +
528 (insn.mm_i_format.simmediate << 1);
529 else
530 *contpc = regs->cp0_epc +
531 dec_insn.pc_inc +
532 dec_insn.next_pc_inc;
533 return 1;
534 case mm_blez_op:
535 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
536 *contpc = regs->cp0_epc +
537 dec_insn.pc_inc +
538 (insn.mm_i_format.simmediate << 1);
539 else
540 *contpc = regs->cp0_epc +
541 dec_insn.pc_inc +
542 dec_insn.next_pc_inc;
543 return 1;
544 case mm_bgtz_op:
545 if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
546 *contpc = regs->cp0_epc +
547 dec_insn.pc_inc +
548 (insn.mm_i_format.simmediate << 1);
549 else
550 *contpc = regs->cp0_epc +
551 dec_insn.pc_inc +
552 dec_insn.next_pc_inc;
553 return 1;
554 case mm_bc2f_op:
555 case mm_bc1f_op:
556 bc_false = 1;
557 /* Fall through */
558 case mm_bc2t_op:
559 case mm_bc1t_op:
560 preempt_disable();
561 if (is_fpu_owner())
562 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
563 else
564 fcr31 = current->thread.fpu.fcr31;
565 preempt_enable();
566
567 if (bc_false)
568 fcr31 = ~fcr31;
569
570 bit = (insn.mm_i_format.rs >> 2);
571 bit += (bit != 0);
572 bit += 23;
573 if (fcr31 & (1 << bit))
574 *contpc = regs->cp0_epc +
575 dec_insn.pc_inc +
576 (insn.mm_i_format.simmediate << 1);
577 else
578 *contpc = regs->cp0_epc +
579 dec_insn.pc_inc + dec_insn.next_pc_inc;
580 return 1;
581 }
582 break;
583 case mm_pool16c_op:
584 switch (insn.mm_i_format.rt) {
585 case mm_jalr16_op:
586 case mm_jalrs16_op:
587 regs->regs[31] = regs->cp0_epc +
588 dec_insn.pc_inc + dec_insn.next_pc_inc;
589 /* Fall through */
590 case mm_jr16_op:
591 *contpc = regs->regs[insn.mm_i_format.rs];
592 return 1;
593 }
594 break;
595 case mm_beqz16_op:
596 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
597 *contpc = regs->cp0_epc +
598 dec_insn.pc_inc +
599 (insn.mm_b1_format.simmediate << 1);
600 else
601 *contpc = regs->cp0_epc +
602 dec_insn.pc_inc + dec_insn.next_pc_inc;
603 return 1;
604 case mm_bnez16_op:
605 if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
606 *contpc = regs->cp0_epc +
607 dec_insn.pc_inc +
608 (insn.mm_b1_format.simmediate << 1);
609 else
610 *contpc = regs->cp0_epc +
611 dec_insn.pc_inc + dec_insn.next_pc_inc;
612 return 1;
613 case mm_b16_op:
614 *contpc = regs->cp0_epc + dec_insn.pc_inc +
615 (insn.mm_b0_format.simmediate << 1);
616 return 1;
617 case mm_beq32_op:
618 if (regs->regs[insn.mm_i_format.rs] ==
619 regs->regs[insn.mm_i_format.rt])
620 *contpc = regs->cp0_epc +
621 dec_insn.pc_inc +
622 (insn.mm_i_format.simmediate << 1);
623 else
624 *contpc = regs->cp0_epc +
625 dec_insn.pc_inc +
626 dec_insn.next_pc_inc;
627 return 1;
628 case mm_bne32_op:
629 if (regs->regs[insn.mm_i_format.rs] !=
630 regs->regs[insn.mm_i_format.rt])
631 *contpc = regs->cp0_epc +
632 dec_insn.pc_inc +
633 (insn.mm_i_format.simmediate << 1);
634 else
635 *contpc = regs->cp0_epc +
636 dec_insn.pc_inc + dec_insn.next_pc_inc;
637 return 1;
638 case mm_jalx32_op:
639 regs->regs[31] = regs->cp0_epc +
640 dec_insn.pc_inc + dec_insn.next_pc_inc;
641 *contpc = regs->cp0_epc + dec_insn.pc_inc;
642 *contpc >>= 28;
643 *contpc <<= 28;
644 *contpc |= (insn.j_format.target << 2);
645 return 1;
646 case mm_jals32_op:
647 case mm_jal32_op:
648 regs->regs[31] = regs->cp0_epc +
649 dec_insn.pc_inc + dec_insn.next_pc_inc;
650 /* Fall through */
651 case mm_j32_op:
652 *contpc = regs->cp0_epc + dec_insn.pc_inc;
653 *contpc >>= 27;
654 *contpc <<= 27;
655 *contpc |= (insn.j_format.target << 1);
656 set_isa16_mode(*contpc);
657 return 1;
658 }
659 return 0;
660 }
661
662 /*
663 * Redundant with logic already in kernel/branch.c,
664 * embedded in compute_return_epc. At some point,
665 * a single subroutine should be used across both
666 * modules.
667 */
668 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
669 unsigned long *contpc)
670 {
671 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
672 unsigned int fcr31;
673 unsigned int bit = 0;
674
675 switch (insn.i_format.opcode) {
676 case spec_op:
677 switch (insn.r_format.func) {
678 case jalr_op:
679 regs->regs[insn.r_format.rd] =
680 regs->cp0_epc + dec_insn.pc_inc +
681 dec_insn.next_pc_inc;
682 /* Fall through */
683 case jr_op:
684 *contpc = regs->regs[insn.r_format.rs];
685 return 1;
686 }
687 break;
688 case bcond_op:
689 switch (insn.i_format.rt) {
690 case bltzal_op:
691 case bltzall_op:
692 regs->regs[31] = regs->cp0_epc +
693 dec_insn.pc_inc +
694 dec_insn.next_pc_inc;
695 /* Fall through */
696 case bltz_op:
697 case bltzl_op:
698 if ((long)regs->regs[insn.i_format.rs] < 0)
699 *contpc = regs->cp0_epc +
700 dec_insn.pc_inc +
701 (insn.i_format.simmediate << 2);
702 else
703 *contpc = regs->cp0_epc +
704 dec_insn.pc_inc +
705 dec_insn.next_pc_inc;
706 return 1;
707 case bgezal_op:
708 case bgezall_op:
709 regs->regs[31] = regs->cp0_epc +
710 dec_insn.pc_inc +
711 dec_insn.next_pc_inc;
712 /* Fall through */
713 case bgez_op:
714 case bgezl_op:
715 if ((long)regs->regs[insn.i_format.rs] >= 0)
716 *contpc = regs->cp0_epc +
717 dec_insn.pc_inc +
718 (insn.i_format.simmediate << 2);
719 else
720 *contpc = regs->cp0_epc +
721 dec_insn.pc_inc +
722 dec_insn.next_pc_inc;
723 return 1;
724 }
725 break;
726 case jalx_op:
727 set_isa16_mode(bit);
728 case jal_op:
729 regs->regs[31] = regs->cp0_epc +
730 dec_insn.pc_inc +
731 dec_insn.next_pc_inc;
732 /* Fall through */
733 case j_op:
734 *contpc = regs->cp0_epc + dec_insn.pc_inc;
735 *contpc >>= 28;
736 *contpc <<= 28;
737 *contpc |= (insn.j_format.target << 2);
738 /* Set microMIPS mode bit: XOR for jalx. */
739 *contpc ^= bit;
740 return 1;
741 case beq_op:
742 case beql_op:
743 if (regs->regs[insn.i_format.rs] ==
744 regs->regs[insn.i_format.rt])
745 *contpc = regs->cp0_epc +
746 dec_insn.pc_inc +
747 (insn.i_format.simmediate << 2);
748 else
749 *contpc = regs->cp0_epc +
750 dec_insn.pc_inc +
751 dec_insn.next_pc_inc;
752 return 1;
753 case bne_op:
754 case bnel_op:
755 if (regs->regs[insn.i_format.rs] !=
756 regs->regs[insn.i_format.rt])
757 *contpc = regs->cp0_epc +
758 dec_insn.pc_inc +
759 (insn.i_format.simmediate << 2);
760 else
761 *contpc = regs->cp0_epc +
762 dec_insn.pc_inc +
763 dec_insn.next_pc_inc;
764 return 1;
765 case blez_op:
766 case blezl_op:
767 if ((long)regs->regs[insn.i_format.rs] <= 0)
768 *contpc = regs->cp0_epc +
769 dec_insn.pc_inc +
770 (insn.i_format.simmediate << 2);
771 else
772 *contpc = regs->cp0_epc +
773 dec_insn.pc_inc +
774 dec_insn.next_pc_inc;
775 return 1;
776 case bgtz_op:
777 case bgtzl_op:
778 if ((long)regs->regs[insn.i_format.rs] > 0)
779 *contpc = regs->cp0_epc +
780 dec_insn.pc_inc +
781 (insn.i_format.simmediate << 2);
782 else
783 *contpc = regs->cp0_epc +
784 dec_insn.pc_inc +
785 dec_insn.next_pc_inc;
786 return 1;
787 #ifdef CONFIG_CPU_CAVIUM_OCTEON
788 case lwc2_op: /* This is bbit0 on Octeon */
789 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
790 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
791 else
792 *contpc = regs->cp0_epc + 8;
793 return 1;
794 case ldc2_op: /* This is bbit032 on Octeon */
795 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
796 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
797 else
798 *contpc = regs->cp0_epc + 8;
799 return 1;
800 case swc2_op: /* This is bbit1 on Octeon */
801 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
802 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
803 else
804 *contpc = regs->cp0_epc + 8;
805 return 1;
806 case sdc2_op: /* This is bbit132 on Octeon */
807 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
808 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
809 else
810 *contpc = regs->cp0_epc + 8;
811 return 1;
812 #endif
813 case cop0_op:
814 case cop1_op:
815 case cop2_op:
816 case cop1x_op:
817 if (insn.i_format.rs == bc_op) {
818 preempt_disable();
819 if (is_fpu_owner())
820 asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
821 else
822 fcr31 = current->thread.fpu.fcr31;
823 preempt_enable();
824
825 bit = (insn.i_format.rt >> 2);
826 bit += (bit != 0);
827 bit += 23;
828 switch (insn.i_format.rt & 3) {
829 case 0: /* bc1f */
830 case 2: /* bc1fl */
831 if (~fcr31 & (1 << bit))
832 *contpc = regs->cp0_epc +
833 dec_insn.pc_inc +
834 (insn.i_format.simmediate << 2);
835 else
836 *contpc = regs->cp0_epc +
837 dec_insn.pc_inc +
838 dec_insn.next_pc_inc;
839 return 1;
840 case 1: /* bc1t */
841 case 3: /* bc1tl */
842 if (fcr31 & (1 << bit))
843 *contpc = regs->cp0_epc +
844 dec_insn.pc_inc +
845 (insn.i_format.simmediate << 2);
846 else
847 *contpc = regs->cp0_epc +
848 dec_insn.pc_inc +
849 dec_insn.next_pc_inc;
850 return 1;
851 }
852 }
853 break;
854 }
855 return 0;
856 }
857
858 /*
859 * In the Linux kernel, we support selection of FPR format on the
860 * basis of the Status.FR bit. If an FPU is not present, the FR bit
861 * is hardwired to zero, which would imply a 32-bit FPU even for
862 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
863 * FPU emu is slow and bulky and optimizing this function offers fairly
864 * sizeable benefits so we try to be clever and make this function return
865 * a constant whenever possible, that is on 64-bit kernels without O32
866 * compatibility enabled and on 32-bit without 64-bit FPU support.
867 */
868 static inline int cop1_64bit(struct pt_regs *xcp)
869 {
870 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
871 return 1;
872 #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
873 return 0;
874 #else
875 return !test_thread_flag(TIF_32BIT_FPREGS);
876 #endif
877 }
878
879 #define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \
880 (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32))
881
882 #define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \
883 cop1_64bit(xcp) || !(x & 1) ? \
884 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
885 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
886
887 #define SIFROMHREG(si, x) ((si) = (int)(ctx->fpr[x] >> 32))
888 #define SITOHREG(si, x) (ctx->fpr[x] = \
889 ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
890
891 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
892 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
893
894 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
895 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
896 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
897 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
898
899 /*
900 * Emulate the single floating point instruction pointed at by EPC.
901 * Two instructions if the instruction is in a branch delay slot.
902 */
903
904 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
905 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
906 {
907 mips_instruction ir;
908 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
909 unsigned int cond;
910 int pc_inc;
911
912 /* XXX NEC Vr54xx bug workaround */
913 if (xcp->cp0_cause & CAUSEF_BD) {
914 if (dec_insn.micro_mips_mode) {
915 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
916 xcp->cp0_cause &= ~CAUSEF_BD;
917 } else {
918 if (!isBranchInstr(xcp, dec_insn, &contpc))
919 xcp->cp0_cause &= ~CAUSEF_BD;
920 }
921 }
922
923 if (xcp->cp0_cause & CAUSEF_BD) {
924 /*
925 * The instruction to be emulated is in a branch delay slot
926 * which means that we have to emulate the branch instruction
927 * BEFORE we do the cop1 instruction.
928 *
929 * This branch could be a COP1 branch, but in that case we
930 * would have had a trap for that instruction, and would not
931 * come through this route.
932 *
933 * Linux MIPS branch emulator operates on context, updating the
934 * cp0_epc.
935 */
936 ir = dec_insn.next_insn; /* process delay slot instr */
937 pc_inc = dec_insn.next_pc_inc;
938 } else {
939 ir = dec_insn.insn; /* process current instr */
940 pc_inc = dec_insn.pc_inc;
941 }
942
943 /*
944 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
945 * instructions, we want to convert microMIPS FPU instructions
946 * into MIPS32 instructions so that we could reuse all of the
947 * FPU emulation code.
948 *
949 * NOTE: We cannot do this for branch instructions since they
950 * are not a subset. Example: Cannot emulate a 16-bit
951 * aligned target address with a MIPS32 instruction.
952 */
953 if (dec_insn.micro_mips_mode) {
954 /*
955 * If next instruction is a 16-bit instruction, then it
956 * it cannot be a FPU instruction. This could happen
957 * since we can be called for non-FPU instructions.
958 */
959 if ((pc_inc == 2) ||
960 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
961 == SIGILL))
962 return SIGILL;
963 }
964
965 emul:
966 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
967 MIPS_FPU_EMU_INC_STATS(emulated);
968 switch (MIPSInst_OPCODE(ir)) {
969 case ldc1_op:{
970 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
971 MIPSInst_SIMM(ir));
972 u64 val;
973
974 MIPS_FPU_EMU_INC_STATS(loads);
975
976 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
977 MIPS_FPU_EMU_INC_STATS(errors);
978 *fault_addr = va;
979 return SIGBUS;
980 }
981 if (__get_user(val, va)) {
982 MIPS_FPU_EMU_INC_STATS(errors);
983 *fault_addr = va;
984 return SIGSEGV;
985 }
986 DITOREG(val, MIPSInst_RT(ir));
987 break;
988 }
989
990 case sdc1_op:{
991 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
992 MIPSInst_SIMM(ir));
993 u64 val;
994
995 MIPS_FPU_EMU_INC_STATS(stores);
996 DIFROMREG(val, MIPSInst_RT(ir));
997 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
998 MIPS_FPU_EMU_INC_STATS(errors);
999 *fault_addr = va;
1000 return SIGBUS;
1001 }
1002 if (__put_user(val, va)) {
1003 MIPS_FPU_EMU_INC_STATS(errors);
1004 *fault_addr = va;
1005 return SIGSEGV;
1006 }
1007 break;
1008 }
1009
1010 case lwc1_op:{
1011 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1012 MIPSInst_SIMM(ir));
1013 u32 val;
1014
1015 MIPS_FPU_EMU_INC_STATS(loads);
1016 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1017 MIPS_FPU_EMU_INC_STATS(errors);
1018 *fault_addr = va;
1019 return SIGBUS;
1020 }
1021 if (__get_user(val, va)) {
1022 MIPS_FPU_EMU_INC_STATS(errors);
1023 *fault_addr = va;
1024 return SIGSEGV;
1025 }
1026 SITOREG(val, MIPSInst_RT(ir));
1027 break;
1028 }
1029
1030 case swc1_op:{
1031 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1032 MIPSInst_SIMM(ir));
1033 u32 val;
1034
1035 MIPS_FPU_EMU_INC_STATS(stores);
1036 SIFROMREG(val, MIPSInst_RT(ir));
1037 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1038 MIPS_FPU_EMU_INC_STATS(errors);
1039 *fault_addr = va;
1040 return SIGBUS;
1041 }
1042 if (__put_user(val, va)) {
1043 MIPS_FPU_EMU_INC_STATS(errors);
1044 *fault_addr = va;
1045 return SIGSEGV;
1046 }
1047 break;
1048 }
1049
1050 case cop1_op:
1051 switch (MIPSInst_RS(ir)) {
1052
1053 #if defined(__mips64)
1054 case dmfc_op:
1055 /* copregister fs -> gpr[rt] */
1056 if (MIPSInst_RT(ir) != 0) {
1057 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1058 MIPSInst_RD(ir));
1059 }
1060 break;
1061
1062 case dmtc_op:
1063 /* copregister fs <- rt */
1064 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1065 break;
1066 #endif
1067
1068 case mfhc_op:
1069 if (!cpu_has_mips_r2)
1070 goto sigill;
1071
1072 /* copregister rd -> gpr[rt] */
1073 if (MIPSInst_RT(ir) != 0) {
1074 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1075 MIPSInst_RD(ir));
1076 }
1077 break;
1078
1079 case mthc_op:
1080 if (!cpu_has_mips_r2)
1081 goto sigill;
1082
1083 /* copregister rd <- gpr[rt] */
1084 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1085 break;
1086
1087 case mfc_op:
1088 /* copregister rd -> gpr[rt] */
1089 if (MIPSInst_RT(ir) != 0) {
1090 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1091 MIPSInst_RD(ir));
1092 }
1093 break;
1094
1095 case mtc_op:
1096 /* copregister rd <- rt */
1097 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1098 break;
1099
1100 case cfc_op:{
1101 /* cop control register rd -> gpr[rt] */
1102 u32 value;
1103
1104 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1105 value = ctx->fcr31;
1106 value = (value & ~FPU_CSR_RM) |
1107 mips_rm[modeindex(value)];
1108 #ifdef CSRTRACE
1109 printk("%p gpr[%d]<-csr=%08x\n",
1110 (void *) (xcp->cp0_epc),
1111 MIPSInst_RT(ir), value);
1112 #endif
1113 }
1114 else if (MIPSInst_RD(ir) == FPCREG_RID)
1115 value = 0;
1116 else
1117 value = 0;
1118 if (MIPSInst_RT(ir))
1119 xcp->regs[MIPSInst_RT(ir)] = value;
1120 break;
1121 }
1122
1123 case ctc_op:{
1124 /* copregister rd <- rt */
1125 u32 value;
1126
1127 if (MIPSInst_RT(ir) == 0)
1128 value = 0;
1129 else
1130 value = xcp->regs[MIPSInst_RT(ir)];
1131
1132 /* we only have one writable control reg
1133 */
1134 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1135 #ifdef CSRTRACE
1136 printk("%p gpr[%d]->csr=%08x\n",
1137 (void *) (xcp->cp0_epc),
1138 MIPSInst_RT(ir), value);
1139 #endif
1140
1141 /*
1142 * Don't write reserved bits,
1143 * and convert to ieee library modes
1144 */
1145 ctx->fcr31 = (value &
1146 ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
1147 ieee_rm[modeindex(value)];
1148 }
1149 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1150 return SIGFPE;
1151 }
1152 break;
1153 }
1154
1155 case bc_op:{
1156 int likely = 0;
1157
1158 if (xcp->cp0_cause & CAUSEF_BD)
1159 return SIGILL;
1160
1161 #if __mips >= 4
1162 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
1163 #else
1164 cond = ctx->fcr31 & FPU_CSR_COND;
1165 #endif
1166 switch (MIPSInst_RT(ir) & 3) {
1167 case bcfl_op:
1168 likely = 1;
1169 case bcf_op:
1170 cond = !cond;
1171 break;
1172 case bctl_op:
1173 likely = 1;
1174 case bct_op:
1175 break;
1176 default:
1177 /* thats an illegal instruction */
1178 return SIGILL;
1179 }
1180
1181 xcp->cp0_cause |= CAUSEF_BD;
1182 if (cond) {
1183 /* branch taken: emulate dslot
1184 * instruction
1185 */
1186 xcp->cp0_epc += dec_insn.pc_inc;
1187
1188 contpc = MIPSInst_SIMM(ir);
1189 ir = dec_insn.next_insn;
1190 if (dec_insn.micro_mips_mode) {
1191 contpc = (xcp->cp0_epc + (contpc << 1));
1192
1193 /* If 16-bit instruction, not FPU. */
1194 if ((dec_insn.next_pc_inc == 2) ||
1195 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1196
1197 /*
1198 * Since this instruction will
1199 * be put on the stack with
1200 * 32-bit words, get around
1201 * this problem by putting a
1202 * NOP16 as the second one.
1203 */
1204 if (dec_insn.next_pc_inc == 2)
1205 ir = (ir & (~0xffff)) | MM_NOP16;
1206
1207 /*
1208 * Single step the non-CP1
1209 * instruction in the dslot.
1210 */
1211 return mips_dsemul(xcp, ir, contpc);
1212 }
1213 } else
1214 contpc = (xcp->cp0_epc + (contpc << 2));
1215
1216 switch (MIPSInst_OPCODE(ir)) {
1217 case lwc1_op:
1218 case swc1_op:
1219 #if (__mips >= 2 || defined(__mips64))
1220 case ldc1_op:
1221 case sdc1_op:
1222 #endif
1223 case cop1_op:
1224 #if __mips >= 4 && __mips != 32
1225 case cop1x_op:
1226 #endif
1227 /* its one of ours */
1228 goto emul;
1229 #if __mips >= 4
1230 case spec_op:
1231 if (MIPSInst_FUNC(ir) == movc_op)
1232 goto emul;
1233 break;
1234 #endif
1235 }
1236
1237 /*
1238 * Single step the non-cp1
1239 * instruction in the dslot
1240 */
1241 return mips_dsemul(xcp, ir, contpc);
1242 }
1243 else {
1244 /* branch not taken */
1245 if (likely) {
1246 /*
1247 * branch likely nullifies
1248 * dslot if not taken
1249 */
1250 xcp->cp0_epc += dec_insn.pc_inc;
1251 contpc += dec_insn.pc_inc;
1252 /*
1253 * else continue & execute
1254 * dslot as normal insn
1255 */
1256 }
1257 }
1258 break;
1259 }
1260
1261 default:
1262 if (!(MIPSInst_RS(ir) & 0x10))
1263 return SIGILL;
1264 {
1265 int sig;
1266
1267 /* a real fpu computation instruction */
1268 if ((sig = fpu_emu(xcp, ctx, ir)))
1269 return sig;
1270 }
1271 }
1272 break;
1273
1274 #if __mips >= 4 && __mips != 32
1275 case cop1x_op:{
1276 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1277 if (sig)
1278 return sig;
1279 break;
1280 }
1281 #endif
1282
1283 #if __mips >= 4
1284 case spec_op:
1285 if (MIPSInst_FUNC(ir) != movc_op)
1286 return SIGILL;
1287 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1288 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1289 xcp->regs[MIPSInst_RD(ir)] =
1290 xcp->regs[MIPSInst_RS(ir)];
1291 break;
1292 #endif
1293
1294 default:
1295 sigill:
1296 return SIGILL;
1297 }
1298
1299 /* we did it !! */
1300 xcp->cp0_epc = contpc;
1301 xcp->cp0_cause &= ~CAUSEF_BD;
1302
1303 return 0;
1304 }
1305
1306 /*
1307 * Conversion table from MIPS compare ops 48-63
1308 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1309 */
1310 static const unsigned char cmptab[8] = {
1311 0, /* cmp_0 (sig) cmp_sf */
1312 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1313 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1314 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1315 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1316 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1317 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1318 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1319 };
1320
1321
1322 #if __mips >= 4 && __mips != 32
1323
1324 /*
1325 * Additional MIPS4 instructions
1326 */
1327
1328 #define DEF3OP(name, p, f1, f2, f3) \
1329 static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
1330 ieee754##p t) \
1331 { \
1332 struct _ieee754_csr ieee754_csr_save; \
1333 s = f1(s, t); \
1334 ieee754_csr_save = ieee754_csr; \
1335 s = f2(s, r); \
1336 ieee754_csr_save.cx |= ieee754_csr.cx; \
1337 ieee754_csr_save.sx |= ieee754_csr.sx; \
1338 s = f3(s); \
1339 ieee754_csr.cx |= ieee754_csr_save.cx; \
1340 ieee754_csr.sx |= ieee754_csr_save.sx; \
1341 return s; \
1342 }
1343
1344 static ieee754dp fpemu_dp_recip(ieee754dp d)
1345 {
1346 return ieee754dp_div(ieee754dp_one(0), d);
1347 }
1348
1349 static ieee754dp fpemu_dp_rsqrt(ieee754dp d)
1350 {
1351 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1352 }
1353
1354 static ieee754sp fpemu_sp_recip(ieee754sp s)
1355 {
1356 return ieee754sp_div(ieee754sp_one(0), s);
1357 }
1358
1359 static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
1360 {
1361 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1362 }
1363
1364 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1365 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1366 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1367 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1368 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1369 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1370 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1371 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1372
1373 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1374 mips_instruction ir, void *__user *fault_addr)
1375 {
1376 unsigned rcsr = 0; /* resulting csr */
1377
1378 MIPS_FPU_EMU_INC_STATS(cp1xops);
1379
1380 switch (MIPSInst_FMA_FFMT(ir)) {
1381 case s_fmt:{ /* 0 */
1382
1383 ieee754sp(*handler) (ieee754sp, ieee754sp, ieee754sp);
1384 ieee754sp fd, fr, fs, ft;
1385 u32 __user *va;
1386 u32 val;
1387
1388 switch (MIPSInst_FUNC(ir)) {
1389 case lwxc1_op:
1390 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1391 xcp->regs[MIPSInst_FT(ir)]);
1392
1393 MIPS_FPU_EMU_INC_STATS(loads);
1394 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1395 MIPS_FPU_EMU_INC_STATS(errors);
1396 *fault_addr = va;
1397 return SIGBUS;
1398 }
1399 if (__get_user(val, va)) {
1400 MIPS_FPU_EMU_INC_STATS(errors);
1401 *fault_addr = va;
1402 return SIGSEGV;
1403 }
1404 SITOREG(val, MIPSInst_FD(ir));
1405 break;
1406
1407 case swxc1_op:
1408 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1409 xcp->regs[MIPSInst_FT(ir)]);
1410
1411 MIPS_FPU_EMU_INC_STATS(stores);
1412
1413 SIFROMREG(val, MIPSInst_FS(ir));
1414 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1415 MIPS_FPU_EMU_INC_STATS(errors);
1416 *fault_addr = va;
1417 return SIGBUS;
1418 }
1419 if (put_user(val, va)) {
1420 MIPS_FPU_EMU_INC_STATS(errors);
1421 *fault_addr = va;
1422 return SIGSEGV;
1423 }
1424 break;
1425
1426 case madd_s_op:
1427 handler = fpemu_sp_madd;
1428 goto scoptop;
1429 case msub_s_op:
1430 handler = fpemu_sp_msub;
1431 goto scoptop;
1432 case nmadd_s_op:
1433 handler = fpemu_sp_nmadd;
1434 goto scoptop;
1435 case nmsub_s_op:
1436 handler = fpemu_sp_nmsub;
1437 goto scoptop;
1438
1439 scoptop:
1440 SPFROMREG(fr, MIPSInst_FR(ir));
1441 SPFROMREG(fs, MIPSInst_FS(ir));
1442 SPFROMREG(ft, MIPSInst_FT(ir));
1443 fd = (*handler) (fr, fs, ft);
1444 SPTOREG(fd, MIPSInst_FD(ir));
1445
1446 copcsr:
1447 if (ieee754_cxtest(IEEE754_INEXACT))
1448 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1449 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1450 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1451 if (ieee754_cxtest(IEEE754_OVERFLOW))
1452 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1453 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1454 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1455
1456 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1457 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1458 /*printk ("SIGFPE: fpu csr = %08x\n",
1459 ctx->fcr31); */
1460 return SIGFPE;
1461 }
1462
1463 break;
1464
1465 default:
1466 return SIGILL;
1467 }
1468 break;
1469 }
1470
1471 case d_fmt:{ /* 1 */
1472 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
1473 ieee754dp fd, fr, fs, ft;
1474 u64 __user *va;
1475 u64 val;
1476
1477 switch (MIPSInst_FUNC(ir)) {
1478 case ldxc1_op:
1479 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1480 xcp->regs[MIPSInst_FT(ir)]);
1481
1482 MIPS_FPU_EMU_INC_STATS(loads);
1483 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1484 MIPS_FPU_EMU_INC_STATS(errors);
1485 *fault_addr = va;
1486 return SIGBUS;
1487 }
1488 if (__get_user(val, va)) {
1489 MIPS_FPU_EMU_INC_STATS(errors);
1490 *fault_addr = va;
1491 return SIGSEGV;
1492 }
1493 DITOREG(val, MIPSInst_FD(ir));
1494 break;
1495
1496 case sdxc1_op:
1497 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1498 xcp->regs[MIPSInst_FT(ir)]);
1499
1500 MIPS_FPU_EMU_INC_STATS(stores);
1501 DIFROMREG(val, MIPSInst_FS(ir));
1502 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1503 MIPS_FPU_EMU_INC_STATS(errors);
1504 *fault_addr = va;
1505 return SIGBUS;
1506 }
1507 if (__put_user(val, va)) {
1508 MIPS_FPU_EMU_INC_STATS(errors);
1509 *fault_addr = va;
1510 return SIGSEGV;
1511 }
1512 break;
1513
1514 case madd_d_op:
1515 handler = fpemu_dp_madd;
1516 goto dcoptop;
1517 case msub_d_op:
1518 handler = fpemu_dp_msub;
1519 goto dcoptop;
1520 case nmadd_d_op:
1521 handler = fpemu_dp_nmadd;
1522 goto dcoptop;
1523 case nmsub_d_op:
1524 handler = fpemu_dp_nmsub;
1525 goto dcoptop;
1526
1527 dcoptop:
1528 DPFROMREG(fr, MIPSInst_FR(ir));
1529 DPFROMREG(fs, MIPSInst_FS(ir));
1530 DPFROMREG(ft, MIPSInst_FT(ir));
1531 fd = (*handler) (fr, fs, ft);
1532 DPTOREG(fd, MIPSInst_FD(ir));
1533 goto copcsr;
1534
1535 default:
1536 return SIGILL;
1537 }
1538 break;
1539 }
1540
1541 case 0x7: /* 7 */
1542 if (MIPSInst_FUNC(ir) != pfetch_op) {
1543 return SIGILL;
1544 }
1545 /* ignore prefx operation */
1546 break;
1547
1548 default:
1549 return SIGILL;
1550 }
1551
1552 return 0;
1553 }
1554 #endif
1555
1556
1557
1558 /*
1559 * Emulate a single COP1 arithmetic instruction.
1560 */
1561 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1562 mips_instruction ir)
1563 {
1564 int rfmt; /* resulting format */
1565 unsigned rcsr = 0; /* resulting csr */
1566 unsigned cond;
1567 union {
1568 ieee754dp d;
1569 ieee754sp s;
1570 int w;
1571 #ifdef __mips64
1572 s64 l;
1573 #endif
1574 } rv; /* resulting value */
1575
1576 MIPS_FPU_EMU_INC_STATS(cp1ops);
1577 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1578 case s_fmt:{ /* 0 */
1579 union {
1580 ieee754sp(*b) (ieee754sp, ieee754sp);
1581 ieee754sp(*u) (ieee754sp);
1582 } handler;
1583
1584 switch (MIPSInst_FUNC(ir)) {
1585 /* binary ops */
1586 case fadd_op:
1587 handler.b = ieee754sp_add;
1588 goto scopbop;
1589 case fsub_op:
1590 handler.b = ieee754sp_sub;
1591 goto scopbop;
1592 case fmul_op:
1593 handler.b = ieee754sp_mul;
1594 goto scopbop;
1595 case fdiv_op:
1596 handler.b = ieee754sp_div;
1597 goto scopbop;
1598
1599 /* unary ops */
1600 #if __mips >= 2 || defined(__mips64)
1601 case fsqrt_op:
1602 handler.u = ieee754sp_sqrt;
1603 goto scopuop;
1604 #endif
1605 #if __mips >= 4 && __mips != 32
1606 case frsqrt_op:
1607 handler.u = fpemu_sp_rsqrt;
1608 goto scopuop;
1609 case frecip_op:
1610 handler.u = fpemu_sp_recip;
1611 goto scopuop;
1612 #endif
1613 #if __mips >= 4
1614 case fmovc_op:
1615 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1616 if (((ctx->fcr31 & cond) != 0) !=
1617 ((MIPSInst_FT(ir) & 1) != 0))
1618 return 0;
1619 SPFROMREG(rv.s, MIPSInst_FS(ir));
1620 break;
1621 case fmovz_op:
1622 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1623 return 0;
1624 SPFROMREG(rv.s, MIPSInst_FS(ir));
1625 break;
1626 case fmovn_op:
1627 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1628 return 0;
1629 SPFROMREG(rv.s, MIPSInst_FS(ir));
1630 break;
1631 #endif
1632 case fabs_op:
1633 handler.u = ieee754sp_abs;
1634 goto scopuop;
1635 case fneg_op:
1636 handler.u = ieee754sp_neg;
1637 goto scopuop;
1638 case fmov_op:
1639 /* an easy one */
1640 SPFROMREG(rv.s, MIPSInst_FS(ir));
1641 goto copcsr;
1642
1643 /* binary op on handler */
1644 scopbop:
1645 {
1646 ieee754sp fs, ft;
1647
1648 SPFROMREG(fs, MIPSInst_FS(ir));
1649 SPFROMREG(ft, MIPSInst_FT(ir));
1650
1651 rv.s = (*handler.b) (fs, ft);
1652 goto copcsr;
1653 }
1654 scopuop:
1655 {
1656 ieee754sp fs;
1657
1658 SPFROMREG(fs, MIPSInst_FS(ir));
1659 rv.s = (*handler.u) (fs);
1660 goto copcsr;
1661 }
1662 copcsr:
1663 if (ieee754_cxtest(IEEE754_INEXACT))
1664 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1665 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1666 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1667 if (ieee754_cxtest(IEEE754_OVERFLOW))
1668 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1669 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1670 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1671 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1672 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1673 break;
1674
1675 /* unary conv ops */
1676 case fcvts_op:
1677 return SIGILL; /* not defined */
1678 case fcvtd_op:{
1679 ieee754sp fs;
1680
1681 SPFROMREG(fs, MIPSInst_FS(ir));
1682 rv.d = ieee754dp_fsp(fs);
1683 rfmt = d_fmt;
1684 goto copcsr;
1685 }
1686 case fcvtw_op:{
1687 ieee754sp fs;
1688
1689 SPFROMREG(fs, MIPSInst_FS(ir));
1690 rv.w = ieee754sp_tint(fs);
1691 rfmt = w_fmt;
1692 goto copcsr;
1693 }
1694
1695 #if __mips >= 2 || defined(__mips64)
1696 case fround_op:
1697 case ftrunc_op:
1698 case fceil_op:
1699 case ffloor_op:{
1700 unsigned int oldrm = ieee754_csr.rm;
1701 ieee754sp fs;
1702
1703 SPFROMREG(fs, MIPSInst_FS(ir));
1704 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1705 rv.w = ieee754sp_tint(fs);
1706 ieee754_csr.rm = oldrm;
1707 rfmt = w_fmt;
1708 goto copcsr;
1709 }
1710 #endif /* __mips >= 2 */
1711
1712 #if defined(__mips64)
1713 case fcvtl_op:{
1714 ieee754sp fs;
1715
1716 SPFROMREG(fs, MIPSInst_FS(ir));
1717 rv.l = ieee754sp_tlong(fs);
1718 rfmt = l_fmt;
1719 goto copcsr;
1720 }
1721
1722 case froundl_op:
1723 case ftruncl_op:
1724 case fceill_op:
1725 case ffloorl_op:{
1726 unsigned int oldrm = ieee754_csr.rm;
1727 ieee754sp fs;
1728
1729 SPFROMREG(fs, MIPSInst_FS(ir));
1730 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1731 rv.l = ieee754sp_tlong(fs);
1732 ieee754_csr.rm = oldrm;
1733 rfmt = l_fmt;
1734 goto copcsr;
1735 }
1736 #endif /* defined(__mips64) */
1737
1738 default:
1739 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1740 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1741 ieee754sp fs, ft;
1742
1743 SPFROMREG(fs, MIPSInst_FS(ir));
1744 SPFROMREG(ft, MIPSInst_FT(ir));
1745 rv.w = ieee754sp_cmp(fs, ft,
1746 cmptab[cmpop & 0x7], cmpop & 0x8);
1747 rfmt = -1;
1748 if ((cmpop & 0x8) && ieee754_cxtest
1749 (IEEE754_INVALID_OPERATION))
1750 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1751 else
1752 goto copcsr;
1753
1754 }
1755 else {
1756 return SIGILL;
1757 }
1758 break;
1759 }
1760 break;
1761 }
1762
1763 case d_fmt:{
1764 union {
1765 ieee754dp(*b) (ieee754dp, ieee754dp);
1766 ieee754dp(*u) (ieee754dp);
1767 } handler;
1768
1769 switch (MIPSInst_FUNC(ir)) {
1770 /* binary ops */
1771 case fadd_op:
1772 handler.b = ieee754dp_add;
1773 goto dcopbop;
1774 case fsub_op:
1775 handler.b = ieee754dp_sub;
1776 goto dcopbop;
1777 case fmul_op:
1778 handler.b = ieee754dp_mul;
1779 goto dcopbop;
1780 case fdiv_op:
1781 handler.b = ieee754dp_div;
1782 goto dcopbop;
1783
1784 /* unary ops */
1785 #if __mips >= 2 || defined(__mips64)
1786 case fsqrt_op:
1787 handler.u = ieee754dp_sqrt;
1788 goto dcopuop;
1789 #endif
1790 #if __mips >= 4 && __mips != 32
1791 case frsqrt_op:
1792 handler.u = fpemu_dp_rsqrt;
1793 goto dcopuop;
1794 case frecip_op:
1795 handler.u = fpemu_dp_recip;
1796 goto dcopuop;
1797 #endif
1798 #if __mips >= 4
1799 case fmovc_op:
1800 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1801 if (((ctx->fcr31 & cond) != 0) !=
1802 ((MIPSInst_FT(ir) & 1) != 0))
1803 return 0;
1804 DPFROMREG(rv.d, MIPSInst_FS(ir));
1805 break;
1806 case fmovz_op:
1807 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1808 return 0;
1809 DPFROMREG(rv.d, MIPSInst_FS(ir));
1810 break;
1811 case fmovn_op:
1812 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1813 return 0;
1814 DPFROMREG(rv.d, MIPSInst_FS(ir));
1815 break;
1816 #endif
1817 case fabs_op:
1818 handler.u = ieee754dp_abs;
1819 goto dcopuop;
1820
1821 case fneg_op:
1822 handler.u = ieee754dp_neg;
1823 goto dcopuop;
1824
1825 case fmov_op:
1826 /* an easy one */
1827 DPFROMREG(rv.d, MIPSInst_FS(ir));
1828 goto copcsr;
1829
1830 /* binary op on handler */
1831 dcopbop:{
1832 ieee754dp fs, ft;
1833
1834 DPFROMREG(fs, MIPSInst_FS(ir));
1835 DPFROMREG(ft, MIPSInst_FT(ir));
1836
1837 rv.d = (*handler.b) (fs, ft);
1838 goto copcsr;
1839 }
1840 dcopuop:{
1841 ieee754dp fs;
1842
1843 DPFROMREG(fs, MIPSInst_FS(ir));
1844 rv.d = (*handler.u) (fs);
1845 goto copcsr;
1846 }
1847
1848 /* unary conv ops */
1849 case fcvts_op:{
1850 ieee754dp fs;
1851
1852 DPFROMREG(fs, MIPSInst_FS(ir));
1853 rv.s = ieee754sp_fdp(fs);
1854 rfmt = s_fmt;
1855 goto copcsr;
1856 }
1857 case fcvtd_op:
1858 return SIGILL; /* not defined */
1859
1860 case fcvtw_op:{
1861 ieee754dp fs;
1862
1863 DPFROMREG(fs, MIPSInst_FS(ir));
1864 rv.w = ieee754dp_tint(fs); /* wrong */
1865 rfmt = w_fmt;
1866 goto copcsr;
1867 }
1868
1869 #if __mips >= 2 || defined(__mips64)
1870 case fround_op:
1871 case ftrunc_op:
1872 case fceil_op:
1873 case ffloor_op:{
1874 unsigned int oldrm = ieee754_csr.rm;
1875 ieee754dp fs;
1876
1877 DPFROMREG(fs, MIPSInst_FS(ir));
1878 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1879 rv.w = ieee754dp_tint(fs);
1880 ieee754_csr.rm = oldrm;
1881 rfmt = w_fmt;
1882 goto copcsr;
1883 }
1884 #endif
1885
1886 #if defined(__mips64)
1887 case fcvtl_op:{
1888 ieee754dp fs;
1889
1890 DPFROMREG(fs, MIPSInst_FS(ir));
1891 rv.l = ieee754dp_tlong(fs);
1892 rfmt = l_fmt;
1893 goto copcsr;
1894 }
1895
1896 case froundl_op:
1897 case ftruncl_op:
1898 case fceill_op:
1899 case ffloorl_op:{
1900 unsigned int oldrm = ieee754_csr.rm;
1901 ieee754dp fs;
1902
1903 DPFROMREG(fs, MIPSInst_FS(ir));
1904 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1905 rv.l = ieee754dp_tlong(fs);
1906 ieee754_csr.rm = oldrm;
1907 rfmt = l_fmt;
1908 goto copcsr;
1909 }
1910 #endif /* __mips >= 3 */
1911
1912 default:
1913 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1914 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1915 ieee754dp fs, ft;
1916
1917 DPFROMREG(fs, MIPSInst_FS(ir));
1918 DPFROMREG(ft, MIPSInst_FT(ir));
1919 rv.w = ieee754dp_cmp(fs, ft,
1920 cmptab[cmpop & 0x7], cmpop & 0x8);
1921 rfmt = -1;
1922 if ((cmpop & 0x8)
1923 &&
1924 ieee754_cxtest
1925 (IEEE754_INVALID_OPERATION))
1926 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1927 else
1928 goto copcsr;
1929
1930 }
1931 else {
1932 return SIGILL;
1933 }
1934 break;
1935 }
1936 break;
1937 }
1938
1939 case w_fmt:{
1940 ieee754sp fs;
1941
1942 switch (MIPSInst_FUNC(ir)) {
1943 case fcvts_op:
1944 /* convert word to single precision real */
1945 SPFROMREG(fs, MIPSInst_FS(ir));
1946 rv.s = ieee754sp_fint(fs.bits);
1947 rfmt = s_fmt;
1948 goto copcsr;
1949 case fcvtd_op:
1950 /* convert word to double precision real */
1951 SPFROMREG(fs, MIPSInst_FS(ir));
1952 rv.d = ieee754dp_fint(fs.bits);
1953 rfmt = d_fmt;
1954 goto copcsr;
1955 default:
1956 return SIGILL;
1957 }
1958 break;
1959 }
1960
1961 #if defined(__mips64)
1962 case l_fmt:{
1963 switch (MIPSInst_FUNC(ir)) {
1964 case fcvts_op:
1965 /* convert long to single precision real */
1966 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1967 rfmt = s_fmt;
1968 goto copcsr;
1969 case fcvtd_op:
1970 /* convert long to double precision real */
1971 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1972 rfmt = d_fmt;
1973 goto copcsr;
1974 default:
1975 return SIGILL;
1976 }
1977 break;
1978 }
1979 #endif
1980
1981 default:
1982 return SIGILL;
1983 }
1984
1985 /*
1986 * Update the fpu CSR register for this operation.
1987 * If an exception is required, generate a tidy SIGFPE exception,
1988 * without updating the result register.
1989 * Note: cause exception bits do not accumulate, they are rewritten
1990 * for each op; only the flag/sticky bits accumulate.
1991 */
1992 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1993 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1994 /*printk ("SIGFPE: fpu csr = %08x\n",ctx->fcr31); */
1995 return SIGFPE;
1996 }
1997
1998 /*
1999 * Now we can safely write the result back to the register file.
2000 */
2001 switch (rfmt) {
2002 case -1:{
2003 #if __mips >= 4
2004 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
2005 #else
2006 cond = FPU_CSR_COND;
2007 #endif
2008 if (rv.w)
2009 ctx->fcr31 |= cond;
2010 else
2011 ctx->fcr31 &= ~cond;
2012 break;
2013 }
2014 case d_fmt:
2015 DPTOREG(rv.d, MIPSInst_FD(ir));
2016 break;
2017 case s_fmt:
2018 SPTOREG(rv.s, MIPSInst_FD(ir));
2019 break;
2020 case w_fmt:
2021 SITOREG(rv.w, MIPSInst_FD(ir));
2022 break;
2023 #if defined(__mips64)
2024 case l_fmt:
2025 DITOREG(rv.l, MIPSInst_FD(ir));
2026 break;
2027 #endif
2028 default:
2029 return SIGILL;
2030 }
2031
2032 return 0;
2033 }
2034
2035 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2036 int has_fpu, void *__user *fault_addr)
2037 {
2038 unsigned long oldepc, prevepc;
2039 struct mm_decoded_insn dec_insn;
2040 u16 instr[4];
2041 u16 *instr_ptr;
2042 int sig = 0;
2043
2044 oldepc = xcp->cp0_epc;
2045 do {
2046 prevepc = xcp->cp0_epc;
2047
2048 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2049 /*
2050 * Get next 2 microMIPS instructions and convert them
2051 * into 32-bit instructions.
2052 */
2053 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2054 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2055 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2056 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2057 MIPS_FPU_EMU_INC_STATS(errors);
2058 return SIGBUS;
2059 }
2060 instr_ptr = instr;
2061
2062 /* Get first instruction. */
2063 if (mm_insn_16bit(*instr_ptr)) {
2064 /* Duplicate the half-word. */
2065 dec_insn.insn = (*instr_ptr << 16) |
2066 (*instr_ptr);
2067 /* 16-bit instruction. */
2068 dec_insn.pc_inc = 2;
2069 instr_ptr += 1;
2070 } else {
2071 dec_insn.insn = (*instr_ptr << 16) |
2072 *(instr_ptr+1);
2073 /* 32-bit instruction. */
2074 dec_insn.pc_inc = 4;
2075 instr_ptr += 2;
2076 }
2077 /* Get second instruction. */
2078 if (mm_insn_16bit(*instr_ptr)) {
2079 /* Duplicate the half-word. */
2080 dec_insn.next_insn = (*instr_ptr << 16) |
2081 (*instr_ptr);
2082 /* 16-bit instruction. */
2083 dec_insn.next_pc_inc = 2;
2084 } else {
2085 dec_insn.next_insn = (*instr_ptr << 16) |
2086 *(instr_ptr+1);
2087 /* 32-bit instruction. */
2088 dec_insn.next_pc_inc = 4;
2089 }
2090 dec_insn.micro_mips_mode = 1;
2091 } else {
2092 if ((get_user(dec_insn.insn,
2093 (mips_instruction __user *) xcp->cp0_epc)) ||
2094 (get_user(dec_insn.next_insn,
2095 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2096 MIPS_FPU_EMU_INC_STATS(errors);
2097 return SIGBUS;
2098 }
2099 dec_insn.pc_inc = 4;
2100 dec_insn.next_pc_inc = 4;
2101 dec_insn.micro_mips_mode = 0;
2102 }
2103
2104 if ((dec_insn.insn == 0) ||
2105 ((dec_insn.pc_inc == 2) &&
2106 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2107 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2108 else {
2109 /*
2110 * The 'ieee754_csr' is an alias of
2111 * ctx->fcr31. No need to copy ctx->fcr31 to
2112 * ieee754_csr. But ieee754_csr.rm is ieee
2113 * library modes. (not mips rounding mode)
2114 */
2115 /* convert to ieee library modes */
2116 ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
2117 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2118 /* revert to mips rounding mode */
2119 ieee754_csr.rm = mips_rm[ieee754_csr.rm];
2120 }
2121
2122 if (has_fpu)
2123 break;
2124 if (sig)
2125 break;
2126
2127 cond_resched();
2128 } while (xcp->cp0_epc > prevepc);
2129
2130 /* SIGILL indicates a non-fpu instruction */
2131 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2132 /* but if epc has advanced, then ignore it */
2133 sig = 0;
2134
2135 return sig;
2136 }
2137
2138 #ifdef CONFIG_DEBUG_FS
2139
2140 static int fpuemu_stat_get(void *data, u64 *val)
2141 {
2142 int cpu;
2143 unsigned long sum = 0;
2144 for_each_online_cpu(cpu) {
2145 struct mips_fpu_emulator_stats *ps;
2146 local_t *pv;
2147 ps = &per_cpu(fpuemustats, cpu);
2148 pv = (void *)ps + (unsigned long)data;
2149 sum += local_read(pv);
2150 }
2151 *val = sum;
2152 return 0;
2153 }
2154 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
2155
2156 extern struct dentry *mips_debugfs_dir;
2157 static int __init debugfs_fpuemu(void)
2158 {
2159 struct dentry *d, *dir;
2160
2161 if (!mips_debugfs_dir)
2162 return -ENODEV;
2163 dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
2164 if (!dir)
2165 return -ENOMEM;
2166
2167 #define FPU_STAT_CREATE(M) \
2168 do { \
2169 d = debugfs_create_file(#M , S_IRUGO, dir, \
2170 (void *)offsetof(struct mips_fpu_emulator_stats, M), \
2171 &fops_fpuemu_stat); \
2172 if (!d) \
2173 return -ENOMEM; \
2174 } while (0)
2175
2176 FPU_STAT_CREATE(emulated);
2177 FPU_STAT_CREATE(loads);
2178 FPU_STAT_CREATE(stores);
2179 FPU_STAT_CREATE(cp1ops);
2180 FPU_STAT_CREATE(cp1xops);
2181 FPU_STAT_CREATE(errors);
2182
2183 return 0;
2184 }
2185 __initcall(debugfs_fpuemu);
2186 #endif
Linux with added FPC-III support