drivers/pci/host/pci-imx6.c

   1 /*
   2  * PCIe host controller driver for Freescale i.MX6 SoCs
   3  *
   4  * Copyright (C) 2013 Kosagi
   5  *              http://www.kosagi.com
   6  *
   7  * Author: Sean Cross <xobs@kosagi.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/resource.h>
  26 #include <linux/signal.h>
  27 #include <linux/types.h>
  28
  29 #include "pcie-designware.h"
  30
  31 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
  32
  33 struct imx6_pcie {
  34         int                     reset_gpio;
  35         int                     power_on_gpio;
  36         int                     wake_up_gpio;
  37         int                     disable_gpio;
  38         struct clk              *lvds_gate;
  39         struct clk              *sata_ref_100m;
  40         struct clk              *pcie_ref_125m;
  41         struct clk              *pcie_axi;
  42         struct pcie_port        pp;
  43         struct regmap           *iomuxc_gpr;
  44         void __iomem            *mem_base;
  45 };
  46
  47 /* PCIe Root Complex registers (memory-mapped) */
  48 #define PCIE_RC_LCR                             0x7c
  49 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1        0x1
  50 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2        0x2
  51 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK        0xf
  52
  53 /* PCIe Port Logic registers (memory-mapped) */
  54 #define PL_OFFSET 0x700
  55 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  56 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  57 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
  58 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP          (1 << 4)
  59
  60 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  61 #define PCIE_PHY_CTRL_DATA_LOC 0
  62 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  63 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  64 #define PCIE_PHY_CTRL_WR_LOC 18
  65 #define PCIE_PHY_CTRL_RD_LOC 19
  66
  67 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  68 #define PCIE_PHY_STAT_ACK_LOC 16
  69
  70 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
  71 #define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
  72
  73 /* PHY registers (not memory-mapped) */
  74 #define PCIE_PHY_RX_ASIC_OUT 0x100D
  75
  76 #define PHY_RX_OVRD_IN_LO 0x1005
  77 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  78 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  79
  80 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  81 {
  82         u32 val;
  83         u32 max_iterations = 10;
  84         u32 wait_counter = 0;
  85
  86         do {
  87                 val = readl(dbi_base + PCIE_PHY_STAT);
  88                 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  89                 wait_counter++;
  90
  91                 if (val == exp_val)
  92                         return 0;
  93
  94                 udelay(1);
  95         } while (wait_counter < max_iterations);
  96
  97         return -ETIMEDOUT;
  98 }
  99
 100 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
 101 {
 102         u32 val;
 103         int ret;
 104
 105         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 106         writel(val, dbi_base + PCIE_PHY_CTRL);
 107
 108         val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
 109         writel(val, dbi_base + PCIE_PHY_CTRL);
 110
 111         ret = pcie_phy_poll_ack(dbi_base, 1);
 112         if (ret)
 113                 return ret;
 114
 115         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 116         writel(val, dbi_base + PCIE_PHY_CTRL);
 117
 118         ret = pcie_phy_poll_ack(dbi_base, 0);
 119         if (ret)
 120                 return ret;
 121
 122         return 0;
 123 }
 124
 125 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 126 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
 127 {
 128         u32 val, phy_ctl;
 129         int ret;
 130
 131         ret = pcie_phy_wait_ack(dbi_base, addr);
 132         if (ret)
 133                 return ret;
 134
 135         /* assert Read signal */
 136         phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
 137         writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
 138
 139         ret = pcie_phy_poll_ack(dbi_base, 1);
 140         if (ret)
 141                 return ret;
 142
 143         val = readl(dbi_base + PCIE_PHY_STAT);
 144         *data = val & 0xffff;
 145
 146         /* deassert Read signal */
 147         writel(0x00, dbi_base + PCIE_PHY_CTRL);
 148
 149         ret = pcie_phy_poll_ack(dbi_base, 0);
 150         if (ret)
 151                 return ret;
 152
 153         return 0;
 154 }
 155
 156 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 157 {
 158         u32 var;
 159         int ret;
 160
 161         /* write addr */
 162         /* cap addr */
 163         ret = pcie_phy_wait_ack(dbi_base, addr);
 164         if (ret)
 165                 return ret;
 166
 167         var = data << PCIE_PHY_CTRL_DATA_LOC;
 168         writel(var, dbi_base + PCIE_PHY_CTRL);
 169
 170         /* capture data */
 171         var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
 172         writel(var, dbi_base + PCIE_PHY_CTRL);
 173
 174         ret = pcie_phy_poll_ack(dbi_base, 1);
 175         if (ret)
 176                 return ret;
 177
 178         /* deassert cap data */
 179         var = data << PCIE_PHY_CTRL_DATA_LOC;
 180         writel(var, dbi_base + PCIE_PHY_CTRL);
 181
 182         /* wait for ack de-assertion */
 183         ret = pcie_phy_poll_ack(dbi_base, 0);
 184         if (ret)
 185                 return ret;
 186
 187         /* assert wr signal */
 188         var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
 189         writel(var, dbi_base + PCIE_PHY_CTRL);
 190
 191         /* wait for ack */
 192         ret = pcie_phy_poll_ack(dbi_base, 1);
 193         if (ret)
 194                 return ret;
 195
 196         /* deassert wr signal */
 197         var = data << PCIE_PHY_CTRL_DATA_LOC;
 198         writel(var, dbi_base + PCIE_PHY_CTRL);
 199
 200         /* wait for ack de-assertion */
 201         ret = pcie_phy_poll_ack(dbi_base, 0);
 202         if (ret)
 203                 return ret;
 204
 205         writel(0x0, dbi_base + PCIE_PHY_CTRL);
 206
 207         return 0;
 208 }
 209
 210 /*  Added for PCI abort handling */
 211 static int imx6q_pcie_abort_handler(unsigned long addr,
 212                 unsigned int fsr, struct pt_regs *regs)
 213 {
 214         return 0;
 215 }
 216
 217 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 218 {
 219         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 220
 221         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 222                         IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 223         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 224                         IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 225
 226         return 0;
 227 }
 228
 229 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 230 {
 231         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 232         int ret;
 233
 234         if (gpio_is_valid(imx6_pcie->power_on_gpio))
 235                 gpio_set_value(imx6_pcie->power_on_gpio, 1);
 236
 237         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 238                         IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 239         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 240                         IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 241
 242         ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
 243         if (ret) {
 244                 dev_err(pp->dev, "unable to enable sata_ref_100m\n");
 245                 goto err_sata_ref;
 246         }
 247
 248         ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
 249         if (ret) {
 250                 dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
 251                 goto err_pcie_ref;
 252         }
 253
 254         ret = clk_prepare_enable(imx6_pcie->lvds_gate);
 255         if (ret) {
 256                 dev_err(pp->dev, "unable to enable lvds_gate\n");
 257                 goto err_lvds_gate;
 258         }
 259
 260         ret = clk_prepare_enable(imx6_pcie->pcie_axi);
 261         if (ret) {
 262                 dev_err(pp->dev, "unable to enable pcie_axi\n");
 263                 goto err_pcie_axi;
 264         }
 265
 266         /* allow the clocks to stabilize */
 267         usleep_range(200, 500);
 268
 269         /* Some boards don't have PCIe reset GPIO. */
 270         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 271                 gpio_set_value(imx6_pcie->reset_gpio, 0);
 272                 msleep(100);
 273                 gpio_set_value(imx6_pcie->reset_gpio, 1);
 274         }
 275         return 0;
 276
 277 err_pcie_axi:
 278         clk_disable_unprepare(imx6_pcie->lvds_gate);
 279 err_lvds_gate:
 280         clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
 281 err_pcie_ref:
 282         clk_disable_unprepare(imx6_pcie->sata_ref_100m);
 283 err_sata_ref:
 284         return ret;
 285
 286 }
 287
 288 static void imx6_pcie_init_phy(struct pcie_port *pp)
 289 {
 290         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 291
 292         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 293                         IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 294
 295         /* configure constant input signal to the pcie ctrl and phy */
 296         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 297                         IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 298         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 299                         IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 300
 301         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 302                         IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
 303         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 304                         IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
 305         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 306                         IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
 307         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 308                         IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
 309         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 310                         IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
 311 }
 312
 313 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
 314 {
 315         int count = 200;
 316
 317         while (!dw_pcie_link_up(pp)) {
 318                 usleep_range(100, 1000);
 319                 if (--count)
 320                         continue;
 321
 322                 dev_err(pp->dev, "phy link never came up\n");
 323                 dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 324                         readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
 325                         readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
 326                 return -EINVAL;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static int imx6_pcie_start_link(struct pcie_port *pp)
 333 {
 334         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 335         uint32_t tmp;
 336         int ret, count;
 337
 338         /*
 339          * Force Gen1 operation when starting the link.  In case the link is
 340          * started in Gen2 mode, there is a possibility the devices on the
 341          * bus will not be detected at all.  This happens with PCIe switches.
 342          */
 343         tmp = readl(pp->dbi_base + PCIE_RC_LCR);
 344         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 345         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
 346         writel(tmp, pp->dbi_base + PCIE_RC_LCR);
 347
 348         /* Start LTSSM. */
 349         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 350                         IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
 351
 352         ret = imx6_pcie_wait_for_link(pp);
 353         if (ret)
 354                 return ret;
 355
 356         /* Allow Gen2 mode after the link is up. */
 357         tmp = readl(pp->dbi_base + PCIE_RC_LCR);
 358         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 359         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
 360         writel(tmp, pp->dbi_base + PCIE_RC_LCR);
 361
 362         /*
 363          * Start Directed Speed Change so the best possible speed both link
 364          * partners support can be negotiated.
 365          */
 366         tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 367         tmp |= PORT_LOGIC_SPEED_CHANGE;
 368         writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 369
 370         count = 200;
 371         while (count--) {
 372                 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 373                 /* Test if the speed change finished. */
 374                 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 375                         break;
 376                 usleep_range(100, 1000);
 377         }
 378
 379         /* Make sure link training is finished as well! */
 380         if (count)
 381                 ret = imx6_pcie_wait_for_link(pp);
 382         else
 383                 ret = -EINVAL;
 384
 385         if (ret) {
 386                 dev_err(pp->dev, "Failed to bring link up!\n");
 387         } else {
 388                 tmp = readl(pp->dbi_base + 0x80);
 389                 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
 390         }
 391
 392         return ret;
 393 }
 394
 395 static void imx6_pcie_host_init(struct pcie_port *pp)
 396 {
 397         imx6_pcie_assert_core_reset(pp);
 398
 399         imx6_pcie_init_phy(pp);
 400
 401         imx6_pcie_deassert_core_reset(pp);
 402
 403         dw_pcie_setup_rc(pp);
 404
 405         imx6_pcie_start_link(pp);
 406 }
 407
 408 static void imx6_pcie_reset_phy(struct pcie_port *pp)
 409 {
 410         uint32_t temp;
 411
 412         pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
 413         temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 414                  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 415         pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
 416
 417         usleep_range(2000, 3000);
 418
 419         pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
 420         temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 421                   PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 422         pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
 423 }
 424
 425 static int imx6_pcie_link_up(struct pcie_port *pp)
 426 {
 427         u32 rc, ltssm, rx_valid;
 428
 429         /*
 430          * Test if the PHY reports that the link is up and also that
 431          * the link training finished.  It might happen that the PHY
 432          * reports the link is already up, but the link training bit
 433          * is still set, so make sure to check the training is done
 434          * as well here.
 435          */
 436         rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
 437         if ((rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP) &&
 438             !(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
 439                 return 1;
 440
 441         /*
 442          * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
 443          * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
 444          * If (MAC/LTSSM.state == Recovery.RcvrLock)
 445          * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
 446          * to gen2 is stuck
 447          */
 448         pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
 449         ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
 450
 451         if (rx_valid & 0x01)
 452                 return 0;
 453
 454         if (ltssm != 0x0d)
 455                 return 0;
 456
 457         dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
 458
 459         imx6_pcie_reset_phy(pp);
 460
 461         return 0;
 462 }
 463
 464 static struct pcie_host_ops imx6_pcie_host_ops = {
 465         .link_up = imx6_pcie_link_up,
 466         .host_init = imx6_pcie_host_init,
 467 };
 468
 469 static int imx6_add_pcie_port(struct pcie_port *pp,
 470                         struct platform_device *pdev)
 471 {
 472         int ret;
 473
 474         pp->irq = platform_get_irq(pdev, 0);
 475         if (!pp->irq) {
 476                 dev_err(&pdev->dev, "failed to get irq\n");
 477                 return -ENODEV;
 478         }
 479
 480         pp->root_bus_nr = -1;
 481         pp->ops = &imx6_pcie_host_ops;
 482
 483         spin_lock_init(&pp->conf_lock);
 484         ret = dw_pcie_host_init(pp);
 485         if (ret) {
 486                 dev_err(&pdev->dev, "failed to initialize host\n");
 487                 return ret;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int __init imx6_pcie_probe(struct platform_device *pdev)
 494 {
 495         struct imx6_pcie *imx6_pcie;
 496         struct pcie_port *pp;
 497         struct device_node *np = pdev->dev.of_node;
 498         struct resource *dbi_base;
 499         int ret;
 500
 501         imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
 502         if (!imx6_pcie)
 503                 return -ENOMEM;
 504
 505         pp = &imx6_pcie->pp;
 506         pp->dev = &pdev->dev;
 507
 508         /* Added for PCI abort handling */
 509         hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 510                 "imprecise external abort");
 511
 512         dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 513         pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
 514         if (IS_ERR(pp->dbi_base))
 515                 return PTR_ERR(pp->dbi_base);
 516
 517         /* Fetch GPIOs */
 518         imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 519         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 520                 ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
 521                                             GPIOF_OUT_INIT_LOW, "PCIe reset");
 522                 if (ret) {
 523                         dev_err(&pdev->dev, "unable to get reset gpio\n");
 524                         return ret;
 525                 }
 526         }
 527
 528         imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
 529         if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
 530                 ret = devm_gpio_request_one(&pdev->dev,
 531                                         imx6_pcie->power_on_gpio,
 532                                         GPIOF_OUT_INIT_LOW,
 533                                         "PCIe power enable");
 534                 if (ret) {
 535                         dev_err(&pdev->dev, "unable to get power-on gpio\n");
 536                         return ret;
 537                 }
 538         }
 539
 540         imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
 541         if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
 542                 ret = devm_gpio_request_one(&pdev->dev,
 543                                         imx6_pcie->wake_up_gpio,
 544                                         GPIOF_IN,
 545                                         "PCIe wake up");
 546                 if (ret) {
 547                         dev_err(&pdev->dev, "unable to get wake-up gpio\n");
 548                         return ret;
 549                 }
 550         }
 551
 552         imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
 553         if (gpio_is_valid(imx6_pcie->disable_gpio)) {
 554                 ret = devm_gpio_request_one(&pdev->dev,
 555                                         imx6_pcie->disable_gpio,
 556                                         GPIOF_OUT_INIT_HIGH,
 557                                         "PCIe disable endpoint");
 558                 if (ret) {
 559                         dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
 560                         return ret;
 561                 }
 562         }
 563
 564         /* Fetch clocks */
 565         imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
 566         if (IS_ERR(imx6_pcie->lvds_gate)) {
 567                 dev_err(&pdev->dev,
 568                         "lvds_gate clock select missing or invalid\n");
 569                 return PTR_ERR(imx6_pcie->lvds_gate);
 570         }
 571
 572         imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
 573         if (IS_ERR(imx6_pcie->sata_ref_100m)) {
 574                 dev_err(&pdev->dev,
 575                         "sata_ref_100m clock source missing or invalid\n");
 576                 return PTR_ERR(imx6_pcie->sata_ref_100m);
 577         }
 578
 579         imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
 580         if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
 581                 dev_err(&pdev->dev,
 582                         "pcie_ref_125m clock source missing or invalid\n");
 583                 return PTR_ERR(imx6_pcie->pcie_ref_125m);
 584         }
 585
 586         imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
 587         if (IS_ERR(imx6_pcie->pcie_axi)) {
 588                 dev_err(&pdev->dev,
 589                         "pcie_axi clock source missing or invalid\n");
 590                 return PTR_ERR(imx6_pcie->pcie_axi);
 591         }
 592
 593         /* Grab GPR config register range */
 594         imx6_pcie->iomuxc_gpr =
 595                  syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 596         if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 597                 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
 598                 return PTR_ERR(imx6_pcie->iomuxc_gpr);
 599         }
 600
 601         ret = imx6_add_pcie_port(pp, pdev);
 602         if (ret < 0)
 603                 return ret;
 604
 605         platform_set_drvdata(pdev, imx6_pcie);
 606         return 0;
 607 }
 608
 609 static const struct of_device_id imx6_pcie_of_match[] = {
 610         { .compatible = "fsl,imx6q-pcie", },
 611         {},
 612 };
 613 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
 614
 615 static struct platform_driver imx6_pcie_driver = {
 616         .driver = {
 617                 .name   = "imx6q-pcie",
 618                 .owner  = THIS_MODULE,
 619                 .of_match_table = imx6_pcie_of_match,
 620         },
 621 };
 622
 623 /* Freescale PCIe driver does not allow module unload */
 624
 625 static int __init imx6_pcie_init(void)
 626 {
 627         return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
 628 }
 629 fs_initcall(imx6_pcie_init);
 630
 631 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
 632 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
 633 MODULE_LICENSE("GPL v2");