drivers/pci/host/pcie-designware.h

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef _PCIE_DESIGNWARE_H
  15 #define _PCIE_DESIGNWARE_H
  16
  17 struct pcie_port_info {
  18         u32             cfg0_size;
  19         u32             cfg1_size;
  20         u32             io_size;
  21         u32             mem_size;
  22         phys_addr_t     io_bus_addr;
  23         phys_addr_t     mem_bus_addr;
  24 };
  25
  26 /*
  27  * Maximum number of MSI IRQs can be 256 per controller. But keep
  28  * it 32 as of now. Probably we will never need more than 32. If needed,
  29  * then increment it in multiple of 32.
  30  */
  31 #define MAX_MSI_IRQS                    32
  32 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
  33
  34 struct pcie_port {
  35         struct device           *dev;
  36         u8                      root_bus_nr;
  37         void __iomem            *dbi_base;
  38         u64                     cfg0_base;
  39         void __iomem            *va_cfg0_base;
  40         u64                     cfg1_base;
  41         void __iomem            *va_cfg1_base;
  42         u64                     io_base;
  43         u64                     mem_base;
  44         spinlock_t              conf_lock;
  45         struct resource         cfg;
  46         struct resource         io;
  47         struct resource         mem;
  48         struct pcie_port_info   config;
  49         int                     irq;
  50         u32                     lanes;
  51         struct pcie_host_ops    *ops;
  52         int                     msi_irq;
  53         struct irq_domain       *irq_domain;
  54         unsigned long           msi_data;
  55         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
  56 };
  57
  58 struct pcie_host_ops {
  59         void (*readl_rc)(struct pcie_port *pp,
  60                         void __iomem *dbi_base, u32 *val);
  61         void (*writel_rc)(struct pcie_port *pp,
  62                         u32 val, void __iomem *dbi_base);
  63         int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
  64         int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
  65         int (*link_up)(struct pcie_port *pp);
  66         void (*host_init)(struct pcie_port *pp);
  67 };
  68
  69 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
  70 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
  71 void dw_handle_msi_irq(struct pcie_port *pp);
  72 void dw_pcie_msi_init(struct pcie_port *pp);
  73 int dw_pcie_link_up(struct pcie_port *pp);
  74 void dw_pcie_setup_rc(struct pcie_port *pp);
  75 int dw_pcie_host_init(struct pcie_port *pp);
  76
  77 #endif /* _PCIE_DESIGNWARE_H */