drivers/usb/host/fotg210.h

   1 #ifndef __LINUX_FOTG210_H
   2 #define __LINUX_FOTG210_H
   3
   4 /* definitions used for the EHCI driver */
   5
   6 /*
   7  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
   8  * __leXX (normally) or __beXX (given FOTG210_BIG_ENDIAN_DESC), depending on
   9  * the host controller implementation.
  10  *
  11  * To facilitate the strongest possible byte-order checking from "sparse"
  12  * and so on, we use __leXX unless that's not practical.
  13  */
  14 #define __hc32  __le32
  15 #define __hc16  __le16
  16
  17 /* statistics can be kept for tuning/monitoring */
  18 struct fotg210_stats {
  19         /* irq usage */
  20         unsigned long           normal;
  21         unsigned long           error;
  22         unsigned long           iaa;
  23         unsigned long           lost_iaa;
  24
  25         /* termination of urbs from core */
  26         unsigned long           complete;
  27         unsigned long           unlink;
  28 };
  29
  30 /* fotg210_hcd->lock guards shared data against other CPUs:
  31  *   fotg210_hcd:       async, unlink, periodic (and shadow), ...
  32  *   usb_host_endpoint: hcpriv
  33  *   fotg210_qh:        qh_next, qtd_list
  34  *   fotg210_qtd:       qtd_list
  35  *
  36  * Also, hold this lock when talking to HC registers or
  37  * when updating hw_* fields in shared qh/qtd/... structures.
  38  */
  39
  40 #define FOTG210_MAX_ROOT_PORTS  1               /* see HCS_N_PORTS */
  41
  42 /*
  43  * fotg210_rh_state values of FOTG210_RH_RUNNING or above mean that the
  44  * controller may be doing DMA.  Lower values mean there's no DMA.
  45  */
  46 enum fotg210_rh_state {
  47         FOTG210_RH_HALTED,
  48         FOTG210_RH_SUSPENDED,
  49         FOTG210_RH_RUNNING,
  50         FOTG210_RH_STOPPING
  51 };
  52
  53 /*
  54  * Timer events, ordered by increasing delay length.
  55  * Always update event_delays_ns[] and event_handlers[] (defined in
  56  * ehci-timer.c) in parallel with this list.
  57  */
  58 enum fotg210_hrtimer_event {
  59         FOTG210_HRTIMER_POLL_ASS,       /* Poll for async schedule off */
  60         FOTG210_HRTIMER_POLL_PSS,       /* Poll for periodic schedule off */
  61         FOTG210_HRTIMER_POLL_DEAD,      /* Wait for dead controller to stop */
  62         FOTG210_HRTIMER_UNLINK_INTR,    /* Wait for interrupt QH unlink */
  63         FOTG210_HRTIMER_FREE_ITDS,      /* Wait for unused iTDs and siTDs */
  64         FOTG210_HRTIMER_ASYNC_UNLINKS,  /* Unlink empty async QHs */
  65         FOTG210_HRTIMER_IAA_WATCHDOG,   /* Handle lost IAA interrupts */
  66         FOTG210_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
  67         FOTG210_HRTIMER_DISABLE_ASYNC,  /* Wait to disable async sched */
  68         FOTG210_HRTIMER_IO_WATCHDOG,    /* Check for missing IRQs */
  69         FOTG210_HRTIMER_NUM_EVENTS      /* Must come last */
  70 };
  71 #define FOTG210_HRTIMER_NO_EVENT        99
  72
  73 struct fotg210_hcd {                    /* one per controller */
  74         /* timing support */
  75         enum fotg210_hrtimer_event      next_hrtimer_event;
  76         unsigned                enabled_hrtimer_events;
  77         ktime_t                 hr_timeouts[FOTG210_HRTIMER_NUM_EVENTS];
  78         struct hrtimer          hrtimer;
  79
  80         int                     PSS_poll_count;
  81         int                     ASS_poll_count;
  82         int                     died_poll_count;
  83
  84         /* glue to PCI and HCD framework */
  85         struct fotg210_caps __iomem *caps;
  86         struct fotg210_regs __iomem *regs;
  87         struct fotg210_dbg_port __iomem *debug;
  88
  89         __u32                   hcs_params;     /* cached register copy */
  90         spinlock_t              lock;
  91         enum fotg210_rh_state   rh_state;
  92
  93         /* general schedule support */
  94         bool                    scanning:1;
  95         bool                    need_rescan:1;
  96         bool                    intr_unlinking:1;
  97         bool                    async_unlinking:1;
  98         bool                    shutdown:1;
  99         struct fotg210_qh               *qh_scan_next;
 100
 101         /* async schedule support */
 102         struct fotg210_qh               *async;
 103         struct fotg210_qh               *dummy;         /* For AMD quirk use */
 104         struct fotg210_qh               *async_unlink;
 105         struct fotg210_qh               *async_unlink_last;
 106         struct fotg210_qh               *async_iaa;
 107         unsigned                async_unlink_cycle;
 108         unsigned                async_count;    /* async activity count */
 109
 110         /* periodic schedule support */
 111 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 112         unsigned                periodic_size;
 113         __hc32                  *periodic;      /* hw periodic table */
 114         dma_addr_t              periodic_dma;
 115         struct list_head        intr_qh_list;
 116         unsigned                i_thresh;       /* uframes HC might cache */
 117
 118         union fotg210_shadow    *pshadow;       /* mirror hw periodic table */
 119         struct fotg210_qh               *intr_unlink;
 120         struct fotg210_qh               *intr_unlink_last;
 121         unsigned                intr_unlink_cycle;
 122         unsigned                now_frame;      /* frame from HC hardware */
 123         unsigned                next_frame;     /* scan periodic, start here */
 124         unsigned                intr_count;     /* intr activity count */
 125         unsigned                isoc_count;     /* isoc activity count */
 126         unsigned                periodic_count; /* periodic activity count */
 127         /* max periodic time per uframe */
 128         unsigned                uframe_periodic_max;
 129
 130
 131         /* list of itds completed while now_frame was still active */
 132         struct list_head        cached_itd_list;
 133         struct fotg210_itd      *last_itd_to_free;
 134
 135         /* per root hub port */
 136         unsigned long           reset_done[FOTG210_MAX_ROOT_PORTS];
 137
 138         /* bit vectors (one bit per port) */
 139         unsigned long           bus_suspended;          /* which ports were
 140                         already suspended at the start of a bus suspend */
 141         unsigned long           companion_ports;        /* which ports are
 142                         dedicated to the companion controller */
 143         unsigned long           owned_ports;            /* which ports are
 144                         owned by the companion during a bus suspend */
 145         unsigned long           port_c_suspend;         /* which ports have
 146                         the change-suspend feature turned on */
 147         unsigned long           suspended_ports;        /* which ports are
 148                         suspended */
 149         unsigned long           resuming_ports;         /* which ports have
 150                         started to resume */
 151
 152         /* per-HC memory pools (could be per-bus, but ...) */
 153         struct dma_pool         *qh_pool;       /* qh per active urb */
 154         struct dma_pool         *qtd_pool;      /* one or more per qh */
 155         struct dma_pool         *itd_pool;      /* itd per iso urb */
 156
 157         unsigned                random_frame;
 158         unsigned long           next_statechange;
 159         ktime_t                 last_periodic_enable;
 160         u32                     command;
 161
 162         /* SILICON QUIRKS */
 163         unsigned                need_io_watchdog:1;
 164         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 165
 166         u8                      sbrn;           /* packed release number */
 167
 168         /* irq statistics */
 169 #ifdef FOTG210_STATS
 170         struct fotg210_stats    stats;
 171 #       define COUNT(x) ((x)++)
 172 #else
 173 #       define COUNT(x)
 174 #endif
 175
 176         /* debug files */
 177         struct dentry           *debug_dir;
 178 };
 179
 180 /* convert between an HCD pointer and the corresponding FOTG210_HCD */
 181 static inline struct fotg210_hcd *hcd_to_fotg210(struct usb_hcd *hcd)
 182 {
 183         return (struct fotg210_hcd *)(hcd->hcd_priv);
 184 }
 185 static inline struct usb_hcd *fotg210_to_hcd(struct fotg210_hcd *fotg210)
 186 {
 187         return container_of((void *) fotg210, struct usb_hcd, hcd_priv);
 188 }
 189
 190 /*-------------------------------------------------------------------------*/
 191
 192 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 193
 194 /* Section 2.2 Host Controller Capability Registers */
 195 struct fotg210_caps {
 196         /* these fields are specified as 8 and 16 bit registers,
 197          * but some hosts can't perform 8 or 16 bit PCI accesses.
 198          * some hosts treat caplength and hciversion as parts of a 32-bit
 199          * register, others treat them as two separate registers, this
 200          * affects the memory map for big endian controllers.
 201          */
 202         u32             hc_capbase;
 203 #define HC_LENGTH(fotg210, p)   (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
 204                                 (fotg210_big_endian_capbase(fotg210) ? 24 : 0)))
 205 #define HC_VERSION(fotg210, p)  (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
 206                                 (fotg210_big_endian_capbase(fotg210) ? 0 : 16)))
 207         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 208 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 209
 210         u32             hcc_params;     /* HCCPARAMS - offset 0x8 */
 211 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 212 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 213         u8              portroute[8];    /* nibbles for routing - offset 0xC */
 214 };
 215
 216
 217 /* Section 2.3 Host Controller Operational Registers */
 218 struct fotg210_regs {
 219
 220         /* USBCMD: offset 0x00 */
 221         u32             command;
 222
 223 /* EHCI 1.1 addendum */
 224 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 225 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 226 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 227 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 228 #define CMD_ASE         (1<<5)          /* async schedule enable */
 229 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 230 /* 3:2 is periodic frame list size */
 231 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 232 #define CMD_RUN         (1<<0)          /* start/stop HC */
 233
 234         /* USBSTS: offset 0x04 */
 235         u32             status;
 236 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 237 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 238 #define STS_RECL        (1<<13)         /* Reclamation */
 239 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 240 /* some bits reserved */
 241         /* these STS_* flags are also intr_enable bits (USBINTR) */
 242 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 243 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 244 #define STS_FLR         (1<<3)          /* frame list rolled over */
 245 #define STS_PCD         (1<<2)          /* port change detect */
 246 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 247 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 248
 249         /* USBINTR: offset 0x08 */
 250         u32             intr_enable;
 251
 252         /* FRINDEX: offset 0x0C */
 253         u32             frame_index;    /* current microframe number */
 254         /* CTRLDSSEGMENT: offset 0x10 */
 255         u32             segment;        /* address bits 63:32 if needed */
 256         /* PERIODICLISTBASE: offset 0x14 */
 257         u32             frame_list;     /* points to periodic list */
 258         /* ASYNCLISTADDR: offset 0x18 */
 259         u32             async_next;     /* address of next async queue head */
 260
 261         u32     reserved1;
 262         /* PORTSC: offset 0x20 */
 263         u32     port_status;
 264 /* 31:23 reserved */
 265 #define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
 266 #define PORT_RESET      (1<<8)          /* reset port */
 267 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 268 #define PORT_RESUME     (1<<6)          /* resume it */
 269 #define PORT_PEC        (1<<3)          /* port enable change */
 270 #define PORT_PE         (1<<2)          /* port enable */
 271 #define PORT_CSC        (1<<1)          /* connect status change */
 272 #define PORT_CONNECT    (1<<0)          /* device connected */
 273 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC)
 274         u32     reserved2[19];
 275
 276         /* OTGCSR: offet 0x70 */
 277         u32     otgcsr;
 278 #define OTGCSR_HOST_SPD_TYP     (3 << 22)
 279 #define OTGCSR_A_BUS_DROP       (1 << 5)
 280 #define OTGCSR_A_BUS_REQ        (1 << 4)
 281
 282         /* OTGISR: offset 0x74 */
 283         u32     otgisr;
 284 #define OTGISR_OVC      (1 << 10)
 285
 286         u32     reserved3[15];
 287
 288         /* GMIR: offset 0xB4 */
 289         u32     gmir;
 290 #define GMIR_INT_POLARITY       (1 << 3) /*Active High*/
 291 #define GMIR_MHC_INT            (1 << 2)
 292 #define GMIR_MOTG_INT           (1 << 1)
 293 #define GMIR_MDEV_INT   (1 << 0)
 294 };
 295
 296 /* Appendix C, Debug port ... intended for use with special "debug devices"
 297  * that can help if there's no serial console.  (nonstandard enumeration.)
 298  */
 299 struct fotg210_dbg_port {
 300         u32     control;
 301 #define DBGP_OWNER      (1<<30)
 302 #define DBGP_ENABLED    (1<<28)
 303 #define DBGP_DONE       (1<<16)
 304 #define DBGP_INUSE      (1<<10)
 305 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 306 #       define DBGP_ERR_BAD     1
 307 #       define DBGP_ERR_SIGNAL  2
 308 #define DBGP_ERROR      (1<<6)
 309 #define DBGP_GO         (1<<5)
 310 #define DBGP_OUT        (1<<4)
 311 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 312         u32     pids;
 313 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 314 #define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
 315         u32     data03;
 316         u32     data47;
 317         u32     address;
 318 #define DBGP_EPADDR(dev, ep)    (((dev)<<8)|(ep))
 319 };
 320
 321 #ifdef CONFIG_EARLY_PRINTK_DBGP
 322 #include <linux/init.h>
 323 extern int __init early_dbgp_init(char *s);
 324 extern struct console early_dbgp_console;
 325 #endif /* CONFIG_EARLY_PRINTK_DBGP */
 326
 327 struct usb_hcd;
 328
 329 static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd)
 330 {
 331         return 1; /* Shouldn't this be 0? */
 332 }
 333
 334 static inline int xen_dbgp_external_startup(struct usb_hcd *hcd)
 335 {
 336         return -1;
 337 }
 338
 339 #ifdef CONFIG_EARLY_PRINTK_DBGP
 340 /* Call backs from fotg210 host driver to fotg210 debug driver */
 341 extern int dbgp_external_startup(struct usb_hcd *);
 342 extern int dbgp_reset_prep(struct usb_hcd *hcd);
 343 #else
 344 static inline int dbgp_reset_prep(struct usb_hcd *hcd)
 345 {
 346         return xen_dbgp_reset_prep(hcd);
 347 }
 348 static inline int dbgp_external_startup(struct usb_hcd *hcd)
 349 {
 350         return xen_dbgp_external_startup(hcd);
 351 }
 352 #endif
 353
 354 /*-------------------------------------------------------------------------*/
 355
 356 #define QTD_NEXT(fotg210, dma)  cpu_to_hc32(fotg210, (u32)dma)
 357
 358 /*
 359  * EHCI Specification 0.95 Section 3.5
 360  * QTD: describe data transfer components (buffer, direction, ...)
 361  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 362  *
 363  * These are associated only with "QH" (Queue Head) structures,
 364  * used with control, bulk, and interrupt transfers.
 365  */
 366 struct fotg210_qtd {
 367         /* first part defined by EHCI spec */
 368         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 369         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 370         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 371 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 372 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 373 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 374 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 375 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 376 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 377 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 378 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 379 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 380 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 381 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 382 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 383 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 384
 385 #define ACTIVE_BIT(fotg210)     cpu_to_hc32(fotg210, QTD_STS_ACTIVE)
 386 #define HALT_BIT(fotg210)               cpu_to_hc32(fotg210, QTD_STS_HALT)
 387 #define STATUS_BIT(fotg210)     cpu_to_hc32(fotg210, QTD_STS_STS)
 388
 389         __hc32                  hw_buf[5];      /* see EHCI 3.5.4 */
 390         __hc32                  hw_buf_hi[5];   /* Appendix B */
 391
 392         /* the rest is HCD-private */
 393         dma_addr_t              qtd_dma;                /* qtd address */
 394         struct list_head        qtd_list;               /* sw qtd list */
 395         struct urb              *urb;                   /* qtd's urb */
 396         size_t                  length;                 /* length of buffer */
 397 } __aligned(32);
 398
 399 /* mask NakCnt+T in qh->hw_alt_next */
 400 #define QTD_MASK(fotg210)       cpu_to_hc32(fotg210, ~0x1f)
 401
 402 #define IS_SHORT_READ(token) (QTD_LENGTH(token) != 0 && QTD_PID(token) == 1)
 403
 404 /*-------------------------------------------------------------------------*/
 405
 406 /* type tag from {qh,itd,fstn}->hw_next */
 407 #define Q_NEXT_TYPE(fotg210, dma)       ((dma) & cpu_to_hc32(fotg210, 3 << 1))
 408
 409 /*
 410  * Now the following defines are not converted using the
 411  * cpu_to_le32() macro anymore, since we have to support
 412  * "dynamic" switching between be and le support, so that the driver
 413  * can be used on one system with SoC EHCI controller using big-endian
 414  * descriptors as well as a normal little-endian PCI EHCI controller.
 415  */
 416 /* values for that type tag */
 417 #define Q_TYPE_ITD      (0 << 1)
 418 #define Q_TYPE_QH       (1 << 1)
 419 #define Q_TYPE_SITD     (2 << 1)
 420 #define Q_TYPE_FSTN     (3 << 1)
 421
 422 /* next async queue entry, or pointer to interrupt/periodic QH */
 423 #define QH_NEXT(fotg210, dma) \
 424         (cpu_to_hc32(fotg210, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 425
 426 /* for periodic/async schedules and qtd lists, mark end of list */
 427 #define FOTG210_LIST_END(fotg210) \
 428         cpu_to_hc32(fotg210, 1) /* "null pointer" to hw */
 429
 430 /*
 431  * Entries in periodic shadow table are pointers to one of four kinds
 432  * of data structure.  That's dictated by the hardware; a type tag is
 433  * encoded in the low bits of the hardware's periodic schedule.  Use
 434  * Q_NEXT_TYPE to get the tag.
 435  *
 436  * For entries in the async schedule, the type tag always says "qh".
 437  */
 438 union fotg210_shadow {
 439         struct fotg210_qh       *qh;            /* Q_TYPE_QH */
 440         struct fotg210_itd      *itd;           /* Q_TYPE_ITD */
 441         struct fotg210_fstn     *fstn;          /* Q_TYPE_FSTN */
 442         __hc32                  *hw_next;       /* (all types) */
 443         void                    *ptr;
 444 };
 445
 446 /*-------------------------------------------------------------------------*/
 447
 448 /*
 449  * EHCI Specification 0.95 Section 3.6
 450  * QH: describes control/bulk/interrupt endpoints
 451  * See Fig 3-7 "Queue Head Structure Layout".
 452  *
 453  * These appear in both the async and (for interrupt) periodic schedules.
 454  */
 455
 456 /* first part defined by EHCI spec */
 457 struct fotg210_qh_hw {
 458         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 459         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 460 #define QH_CONTROL_EP   (1 << 27)       /* FS/LS control endpoint */
 461 #define QH_HEAD         (1 << 15)       /* Head of async reclamation list */
 462 #define QH_TOGGLE_CTL   (1 << 14)       /* Data toggle control */
 463 #define QH_HIGH_SPEED   (2 << 12)       /* Endpoint speed */
 464 #define QH_LOW_SPEED    (1 << 12)
 465 #define QH_FULL_SPEED   (0 << 12)
 466 #define QH_INACTIVATE   (1 << 7)        /* Inactivate on next transaction */
 467         __hc32                  hw_info2;       /* see EHCI 3.6.2 */
 468 #define QH_SMASK        0x000000ff
 469 #define QH_CMASK        0x0000ff00
 470 #define QH_HUBADDR      0x007f0000
 471 #define QH_HUBPORT      0x3f800000
 472 #define QH_MULT         0xc0000000
 473         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 474
 475         /* qtd overlay (hardware parts of a struct fotg210_qtd) */
 476         __hc32                  hw_qtd_next;
 477         __hc32                  hw_alt_next;
 478         __hc32                  hw_token;
 479         __hc32                  hw_buf[5];
 480         __hc32                  hw_buf_hi[5];
 481 } __aligned(32);
 482
 483 struct fotg210_qh {
 484         struct fotg210_qh_hw    *hw;            /* Must come first */
 485         /* the rest is HCD-private */
 486         dma_addr_t              qh_dma;         /* address of qh */
 487         union fotg210_shadow    qh_next;        /* ptr to qh; or periodic */
 488         struct list_head        qtd_list;       /* sw qtd list */
 489         struct list_head        intr_node;      /* list of intr QHs */
 490         struct fotg210_qtd      *dummy;
 491         struct fotg210_qh       *unlink_next;   /* next on unlink list */
 492
 493         unsigned                unlink_cycle;
 494
 495         u8                      needs_rescan;   /* Dequeue during giveback */
 496         u8                      qh_state;
 497 #define QH_STATE_LINKED         1               /* HC sees this */
 498 #define QH_STATE_UNLINK         2               /* HC may still see this */
 499 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 500 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on unlink q */
 501 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 502
 503         u8                      xacterrs;       /* XactErr retry counter */
 504 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 505
 506         /* periodic schedule info */
 507         u8                      usecs;          /* intr bandwidth */
 508         u8                      gap_uf;         /* uframes split/csplit gap */
 509         u8                      c_usecs;        /* ... split completion bw */
 510         u16                     tt_usecs;       /* tt downstream bandwidth */
 511         unsigned short          period;         /* polling interval */
 512         unsigned short          start;          /* where polling starts */
 513 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 514
 515         struct usb_device       *dev;           /* access to TT */
 516         unsigned                is_out:1;       /* bulk or intr OUT */
 517         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 518 };
 519
 520 /*-------------------------------------------------------------------------*/
 521
 522 /* description of one iso transaction (up to 3 KB data if highspeed) */
 523 struct fotg210_iso_packet {
 524         /* These will be copied to iTD when scheduling */
 525         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 526         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 527         u8                      cross;          /* buf crosses pages */
 528         /* for full speed OUT splits */
 529         u32                     buf1;
 530 };
 531
 532 /* temporary schedule data for packets from iso urbs (both speeds)
 533  * each packet is one logical usb transaction to the device (not TT),
 534  * beginning at stream->next_uframe
 535  */
 536 struct fotg210_iso_sched {
 537         struct list_head        td_list;
 538         unsigned                span;
 539         struct fotg210_iso_packet       packet[0];
 540 };
 541
 542 /*
 543  * fotg210_iso_stream - groups all (s)itds for this endpoint.
 544  * acts like a qh would, if EHCI had them for ISO.
 545  */
 546 struct fotg210_iso_stream {
 547         /* first field matches fotg210_hq, but is NULL */
 548         struct fotg210_qh_hw    *hw;
 549
 550         u8                      bEndpointAddress;
 551         u8                      highspeed;
 552         struct list_head        td_list;        /* queued itds */
 553         struct list_head        free_list;      /* list of unused itds */
 554         struct usb_device       *udev;
 555         struct usb_host_endpoint *ep;
 556
 557         /* output of (re)scheduling */
 558         int                     next_uframe;
 559         __hc32                  splits;
 560
 561         /* the rest is derived from the endpoint descriptor,
 562          * trusting urb->interval == f(epdesc->bInterval) and
 563          * including the extra info for hw_bufp[0..2]
 564          */
 565         u8                      usecs, c_usecs;
 566         u16                     interval;
 567         u16                     tt_usecs;
 568         u16                     maxp;
 569         u16                     raw_mask;
 570         unsigned                bandwidth;
 571
 572         /* This is used to initialize iTD's hw_bufp fields */
 573         __hc32                  buf0;
 574         __hc32                  buf1;
 575         __hc32                  buf2;
 576
 577         /* this is used to initialize sITD's tt info */
 578         __hc32                  address;
 579 };
 580
 581 /*-------------------------------------------------------------------------*/
 582
 583 /*
 584  * EHCI Specification 0.95 Section 3.3
 585  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 586  *
 587  * Schedule records for high speed iso xfers
 588  */
 589 struct fotg210_itd {
 590         /* first part defined by EHCI spec */
 591         __hc32                  hw_next;        /* see EHCI 3.3.1 */
 592         __hc32                  hw_transaction[8]; /* see EHCI 3.3.2 */
 593 #define FOTG210_ISOC_ACTIVE     (1<<31) /* activate transfer this slot */
 594 #define FOTG210_ISOC_BUF_ERR    (1<<30) /* Data buffer error */
 595 #define FOTG210_ISOC_BABBLE     (1<<29) /* babble detected */
 596 #define FOTG210_ISOC_XACTERR    (1<<28) /* XactErr - transaction error */
 597 #define FOTG210_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
 598 #define FOTG210_ITD_IOC         (1 << 15)       /* interrupt on complete */
 599
 600 #define ITD_ACTIVE(fotg210)     cpu_to_hc32(fotg210, FOTG210_ISOC_ACTIVE)
 601
 602         __hc32                  hw_bufp[7];     /* see EHCI 3.3.3 */
 603         __hc32                  hw_bufp_hi[7];  /* Appendix B */
 604
 605         /* the rest is HCD-private */
 606         dma_addr_t              itd_dma;        /* for this itd */
 607         union fotg210_shadow    itd_next;       /* ptr to periodic q entry */
 608
 609         struct urb              *urb;
 610         struct fotg210_iso_stream       *stream;        /* endpoint's queue */
 611         struct list_head        itd_list;       /* list of stream's itds */
 612
 613         /* any/all hw_transactions here may be used by that urb */
 614         unsigned                frame;          /* where scheduled */
 615         unsigned                pg;
 616         unsigned                index[8];       /* in urb->iso_frame_desc */
 617 } __aligned(32);
 618
 619 /*-------------------------------------------------------------------------*/
 620
 621 /*
 622  * EHCI Specification 0.96 Section 3.7
 623  * Periodic Frame Span Traversal Node (FSTN)
 624  *
 625  * Manages split interrupt transactions (using TT) that span frame boundaries
 626  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 627  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 628  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 629  */
 630 struct fotg210_fstn {
 631         __hc32                  hw_next;        /* any periodic q entry */
 632         __hc32                  hw_prev;        /* qh or FOTG210_LIST_END */
 633
 634         /* the rest is HCD-private */
 635         dma_addr_t              fstn_dma;
 636         union fotg210_shadow    fstn_next;      /* ptr to periodic q entry */
 637 } __aligned(32);
 638
 639 /*-------------------------------------------------------------------------*/
 640
 641 /* Prepare the PORTSC wakeup flags during controller suspend/resume */
 642
 643 #define fotg210_prepare_ports_for_controller_suspend(fotg210, do_wakeup) \
 644                 fotg210_adjust_port_wakeup_flags(fotg210, true, do_wakeup);
 645
 646 #define fotg210_prepare_ports_for_controller_resume(fotg210)            \
 647                 fotg210_adjust_port_wakeup_flags(fotg210, false, false);
 648
 649 /*-------------------------------------------------------------------------*/
 650
 651 /*
 652  * Some EHCI controllers have a Transaction Translator built into the
 653  * root hub. This is a non-standard feature.  Each controller will need
 654  * to add code to the following inline functions, and call them as
 655  * needed (mostly in root hub code).
 656  */
 657
 658 static inline unsigned int
 659 fotg210_get_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
 660 {
 661         return (readl(&fotg210->regs->otgcsr)
 662                 & OTGCSR_HOST_SPD_TYP) >> 22;
 663 }
 664
 665 /* Returns the speed of a device attached to a port on the root hub. */
 666 static inline unsigned int
 667 fotg210_port_speed(struct fotg210_hcd *fotg210, unsigned int portsc)
 668 {
 669         switch (fotg210_get_speed(fotg210, portsc)) {
 670         case 0:
 671                 return 0;
 672         case 1:
 673                 return USB_PORT_STAT_LOW_SPEED;
 674         case 2:
 675         default:
 676                 return USB_PORT_STAT_HIGH_SPEED;
 677         }
 678 }
 679
 680 /*-------------------------------------------------------------------------*/
 681
 682 #define fotg210_has_fsl_portno_bug(e)           (0)
 683
 684 /*
 685  * While most USB host controllers implement their registers in
 686  * little-endian format, a minority (celleb companion chip) implement
 687  * them in big endian format.
 688  *
 689  * This attempts to support either format at compile time without a
 690  * runtime penalty, or both formats with the additional overhead
 691  * of checking a flag bit.
 692  *
 693  */
 694
 695 #define fotg210_big_endian_mmio(e)      0
 696 #define fotg210_big_endian_capbase(e)   0
 697
 698 static inline unsigned int fotg210_readl(const struct fotg210_hcd *fotg210,
 699                 __u32 __iomem *regs)
 700 {
 701         return readl(regs);
 702 }
 703
 704 static inline void fotg210_writel(const struct fotg210_hcd *fotg210,
 705                 const unsigned int val, __u32 __iomem *regs)
 706 {
 707         writel(val, regs);
 708 }
 709
 710 /* cpu to fotg210 */
 711 static inline __hc32 cpu_to_hc32(const struct fotg210_hcd *fotg210, const u32 x)
 712 {
 713         return cpu_to_le32(x);
 714 }
 715
 716 /* fotg210 to cpu */
 717 static inline u32 hc32_to_cpu(const struct fotg210_hcd *fotg210, const __hc32 x)
 718 {
 719         return le32_to_cpu(x);
 720 }
 721
 722 static inline u32 hc32_to_cpup(const struct fotg210_hcd *fotg210,
 723                                const __hc32 *x)
 724 {
 725         return le32_to_cpup(x);
 726 }
 727
 728 /*-------------------------------------------------------------------------*/
 729
 730 static inline unsigned fotg210_read_frame_index(struct fotg210_hcd *fotg210)
 731 {
 732         return fotg210_readl(fotg210, &fotg210->regs->frame_index);
 733 }
 734
 735 #define fotg210_itdlen(urb, desc, t) ({                 \
 736         usb_pipein((urb)->pipe) ?                               \
 737         (desc)->length - FOTG210_ITD_LENGTH(t) :                        \
 738         FOTG210_ITD_LENGTH(t);                                  \
 739 })
 740 /*-------------------------------------------------------------------------*/
 741
 742 #endif /* __LINUX_FOTG210_H */