| blob | ba9499060f639c3bff934d4868ca71cfd6948bb4 |
1 /*
2 * Faraday FUSBH200 EHCI-like driver
3 *
4 * Copyright (c) 2013 Faraday Technology Corporation
5 *
6 * Author: Yuan-Hsin Chen <yhchen@faraday-tech.com>
7 * Feng-Hsin Chiang <john453@faraday-tech.com>
8 * Po-Yu Chuang <ratbert.chuang@gmail.com>
9 *
10 * Most of code borrowed from the Linux-3.7 EHCI driver
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
19 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software Foundation,
24 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/dmapool.h>
30 #include <linux/kernel.h>
31 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/sched.h>
34 #include <linux/vmalloc.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/hrtimer.h>
38 #include <linux/list.h>
39 #include <linux/interrupt.h>
40 #include <linux/usb.h>
41 #include <linux/usb/hcd.h>
42 #include <linux/moduleparam.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/debugfs.h>
45 #include <linux/slab.h>
46 #include <linux/uaccess.h>
47 #include <linux/platform_device.h>
49 #include <asm/byteorder.h>
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <asm/unaligned.h>
54 /*-------------------------------------------------------------------------*/
60 #undef FUSBH200_URB_TRACE
62 /* magic numbers that can affect system performance */
65 #define FUSBH200_TUNE_RL_TT 0
67 #define FUSBH200_TUNE_MULT_TT 1
68 /*
69 * Some drivers think it's safe to schedule isochronous transfers more than
70 * 256 ms into the future (partly as a result of an old bug in the scheduling
71 * code). In an attempt to avoid trouble, we will use a minimum scheduling
72 * length of 512 frames instead of 256.
73 */
76 /* Initial IRQ latency: faster than hw default */
81 /* initial park setting: slower than hw default */
86 /* for link power management(LPM) feature */
91 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
95 /*-------------------------------------------------------------------------*/
97 #define fusbh200_dbg(fusbh200, fmt, args...) \
98 dev_dbg (fusbh200_to_hcd(fusbh200)->self.controller , fmt , ## args )
99 #define fusbh200_err(fusbh200, fmt, args...) \
100 dev_err (fusbh200_to_hcd(fusbh200)->self.controller , fmt , ## args )
101 #define fusbh200_info(fusbh200, fmt, args...) \
102 dev_info (fusbh200_to_hcd(fusbh200)->self.controller , fmt , ## args )
103 #define fusbh200_warn(fusbh200, fmt, args...) \
104 dev_warn (fusbh200_to_hcd(fusbh200)->self.controller , fmt , ## args )
106 /* check the values in the HCSPARAMS register
107 * (host controller _Structural_ parameters)
108 * see EHCI spec, Table 2-4 for each value
109 */
111 {
118 );
119 }
121 /* check the values in the HCCPARAMS register
122 * (host controller _Capability_ parameters)
123 * see EHCI Spec, Table 2-5 for each value
124 * */
126 {
131 label,
132 params,
135 }
137 static void __maybe_unused
139 {
151 }
153 static void __maybe_unused
155 {
161 }
163 static void __maybe_unused
165 {
192 }
194 static int __maybe_unused
196 {
210 );
211 }
213 static int __maybe_unused
215 {
225 );
226 }
231 static int
233 {
235 "%s%scommand %07x %s=%d ithresh=%d%s%s%s "
247 );
248 }
250 static int
252 {
255 /* signaling state */
261 }
264 "%s%sport:%d status %06x %d "
268 sig,
276 }
278 /* functions have the "wrong" filename when they're output... */
279 #define dbg_status(fusbh200, label, status) { \
280 char _buf [80]; \
281 dbg_status_buf (_buf, sizeof _buf, label, status); \
283 }
285 #define dbg_cmd(fusbh200, label, command) { \
286 char _buf [80]; \
287 dbg_command_buf (_buf, sizeof _buf, label, command); \
289 }
291 #define dbg_port(fusbh200, label, port, status) { \
292 char _buf [80]; \
293 dbg_port_buf (_buf, sizeof _buf, label, port, status); \
295 }
297 /*-------------------------------------------------------------------------*/
299 /* troubleshooting help: expose state in debugfs */
315 };
322 };
329 };
340 };
342 #define speed_char(info1) ({ char tmp; \
343 switch (info1 & (3 << 12)) { \
348 } tmp; })
351 {
360 /* tries to advance through hw_alt_next */
362 }
369 )
370 {
371 u32 scratch;
372 u32 hw_curr;
383 else
391 /* else alt_next points to some other qtd */
392 }
408 /* hc may be modifying the list as we read it ... */
421 }
432 scratch,
440 }
448 done:
451 }
454 {
469 /* dumps a snapshot of the async schedule.
470 * usually empty except for long-term bulk reads, or head.
471 * one QH per line, and TDs we know about
472 */
484 }
488 }
490 #define DBG_SCHED_LIMIT 64
492 {
500 __hc32 tag;
515 /* dump a snapshot of the periodic schedule.
516 * iso changes, interrupt usually doesn't.
517 */
539 /* uframe masks */
544 /* don't repeat what follows this qh */
553 }
555 }
556 /* show more info the first time around */
563 /* count tds, get ep direction */
567 qtd_list) {
568 temp++;
570 fusbh200,
574 }
575 }
578 " (%c%d ep%d%s "
584 temp,
607 }
615 }
620 }
621 #undef DBG_SCHED_LIMIT
624 {
634 }
636 }
639 {
664 }
666 /* Capability Registers */
679 // FIXME interpret both types of params
690 /* Operational Registers */
719 }
733 done:
737 }
741 {
751 }
754 }
757 {
766 }
773 }
775 out:
777 }
781 {
791 }
792 }
798 out:
801 }
804 {
810 }
813 }
815 {
819 }
822 {
831 }
834 {
836 fill_registers_buffer);
839 }
842 {
863 file_error:
865 }
868 {
870 }
872 /*-------------------------------------------------------------------------*/
874 /*
875 * handshake - spin reading hc until handshake completes or fails
876 * @ptr: address of hc register to be read
877 * @mask: bits to look at in result of read
878 * @done: value of those bits when handshake succeeds
879 * @usec: timeout in microseconds
880 *
881 * Returns negative errno, or zero on success
882 *
883 * Success happens when the "mask" bits have the specified value (hardware
884 * handshake done). There are two failure modes: "usec" have passed (major
885 * hardware flakeout), or the register reads as all-ones (hardware removed).
886 *
887 * That last failure should_only happen in cases like physical cardbus eject
888 * before driver shutdown. But it also seems to be caused by bugs in cardbus
889 * bridge shutdown: shutting down the bridge before the devices using it.
890 */
893 {
894 u32 result;
904 usec--;
907 }
909 /*
910 * Force HC to halt state from unknown (EHCI spec section 2.3).
911 * Must be called with interrupts enabled and the lock not held.
912 */
914 {
915 u32 temp;
919 /* disable any irqs left enabled by previous code */
922 /*
923 * This routine gets called during probe before fusbh200->command
924 * has been initialized, so we can't rely on its value.
925 */
936 }
938 /*
939 * Reset a non-running (STS_HALT == 1) controller.
940 * Must be called with interrupts enabled and the lock not held.
941 */
943 {
947 /* If the EHCI debug controller is active, special care must be
948 * taken before and after a host controller reset */
969 }
971 /*
972 * Idle the controller (turn off the schedules).
973 * Must be called with interrupts enabled and the lock not held.
974 */
976 {
977 u32 temp;
982 /* wait for any schedule enables/disables to take effect */
986 /* then disable anything that's still active */
992 /* hardware can take 16 microframes to turn off ... */
994 }
996 /*-------------------------------------------------------------------------*/
1004 /*-------------------------------------------------------------------------*/
1006 /* Set a bit in the USBCMD register */
1008 {
1012 /* unblock posted write */
1014 }
1016 /* Clear a bit in the USBCMD register */
1018 {
1022 /* unblock posted write */
1024 }
1026 /*-------------------------------------------------------------------------*/
1028 /*
1029 * EHCI timer support... Now using hrtimers.
1030 *
1031 * Lots of different events are triggered from fusbh200->hrtimer. Whenever
1032 * the timer routine runs, it checks each possible event; events that are
1033 * currently enabled and whose expiration time has passed get handled.
1034 * The set of enabled events is stored as a collection of bitflags in
1035 * fusbh200->enabled_hrtimer_events, and they are numbered in order of
1036 * increasing delay values (ranging between 1 ms and 100 ms).
1037 *
1038 * Rather than implementing a sorted list or tree of all pending events,
1039 * we keep track only of the lowest-numbered pending event, in
1040 * fusbh200->next_hrtimer_event. Whenever fusbh200->hrtimer gets restarted, its
1041 * expiration time is set to the timeout value for this event.
1042 *
1043 * As a result, events might not get handled right away; the actual delay
1044 * could be anywhere up to twice the requested delay. This doesn't
1045 * matter, because none of the events are especially time-critical. The
1046 * ones that matter most all have a delay of 1 ms, so they will be
1047 * handled after 2 ms at most, which is okay. In addition to this, we
1048 * allow for an expiration range of 1 ms.
1049 */
1051 /*
1052 * Delay lengths for the hrtimer event types.
1053 * Keep this list sorted by delay length, in the same order as
1054 * the event types indexed by enum fusbh200_hrtimer_event in fusbh200.h.
1055 */
1067 };
1069 /* Enable a pending hrtimer event */
1072 {
1080 /* Track only the lowest-numbered pending event */
1085 }
1086 }
1089 /* Poll the STS_ASS status bit; see when it agrees with CMD_ASE */
1091 {
1094 /* Don't enable anything if the controller isn't running (e.g., died) */
1103 /* Poll again later, but give up after about 20 ms */
1107 }
1110 }
1113 /* The status is up-to-date; restart or stop the schedule as needed */
1121 /* Turn off the schedule after a while */
1124 }
1125 }
1126 }
1128 /* Turn off the async schedule after a brief delay */
1130 {
1132 }
1135 /* Poll the STS_PSS status bit; see when it agrees with CMD_PSE */
1137 {
1140 /* Don't do anything if the controller isn't running (e.g., died) */
1149 /* Poll again later, but give up after about 20 ms */
1153 }
1154 fusbh200_dbg(fusbh200, "Waited too long for the periodic schedule status (%x/%x), giving up\n",
1156 }
1159 /* The status is up-to-date; restart or stop the schedule as needed */
1167 /* Turn off the schedule after a while */
1170 }
1171 }
1172 }
1174 /* Turn off the periodic schedule after a brief delay */
1176 {
1178 }
1181 /* Poll the STS_HALT status bit; see when a dead controller stops */
1183 {
1186 /* Give up after a few milliseconds */
1188 /* Try again later */
1191 }
1193 }
1195 /* Clean up the mess */
1201 /* Not in process context, so don't try to reset the controller */
1202 }
1205 /* Handle unlinked interrupt QHs once they are gone from the hardware */
1207 {
1210 /*
1211 * Process all the QHs on the intr_unlink list that were added
1212 * before the current unlink cycle began. The list is in
1213 * temporal order, so stop when we reach the first entry in the
1214 * current cycle. But if the root hub isn't running then
1215 * process all the QHs on the list.
1216 */
1226 }
1228 /* Handle remaining entries later */
1232 }
1234 }
1237 /* Start another free-iTDs/siTDs cycle */
1239 {
1245 }
1246 }
1248 /* Wait for controller to stop using old iTDs and siTDs */
1250 {
1255 }
1262 }
1266 }
1269 /* Handle lost (or very late) IAA interrupts */
1271 {
1275 /*
1276 * Lost IAA irqs wedge things badly; seen first with a vt8235.
1277 * So we need this watchdog, but must protect it against both
1278 * (a) SMP races against real IAA firing and retriggering, and
1279 * (b) clean HC shutdown, when IAA watchdog was pending.
1280 */
1284 /* If we get here, IAA is *REALLY* late. It's barely
1285 * conceivable that the system is so busy that CMD_IAAD
1286 * is still legitimately set, so let's be sure it's
1287 * clear before we read STS_IAA. (The HC should clear
1288 * CMD_IAAD when it sets STS_IAA.)
1289 */
1292 /*
1293 * If IAA is set here it either legitimately triggered
1294 * after the watchdog timer expired (_way_ late, so we'll
1295 * still count it as lost) ... or a silicon erratum:
1296 * - VIA seems to set IAA without triggering the IRQ;
1297 * - IAAD potentially cleared without setting IAA.
1298 */
1303 }
1308 }
1309 }
1312 /* Enable the I/O watchdog, if appropriate */
1314 {
1315 /* Not needed if the controller isn't running or it's already enabled */
1321 /*
1322 * Isochronous transfers always need the watchdog.
1323 * For other sorts we use it only if the flag is set.
1324 */
1328 }
1331 /*
1332 * Handler functions for the hrtimer event types.
1333 * Keep this array in the same order as the event types indexed by
1334 * enum fusbh200_hrtimer_event in fusbh200.h.
1335 */
1347 };
1350 {
1352 ktime_t now;
1363 /*
1364 * Check each pending event. If its time has expired, handle
1365 * the event; otherwise re-enable it.
1366 */
1371 else
1373 }
1377 }
1379 /*-------------------------------------------------------------------------*/
1381 #define fusbh200_bus_suspend NULL
1382 #define fusbh200_bus_resume NULL
1384 /*-------------------------------------------------------------------------*/
1390 int port_status
1391 ) {
1395 /* if reset finished and it's still not enabled -- handoff */
1397 /* with integrated TT, there's nobody to hand it to! */
1405 }
1408 }
1410 /*-------------------------------------------------------------------------*/
1413 /* build "status change" packet (one or two bytes) from HC registers */
1415 static int
1417 {
1420 u32 mask;
1424 /* init status to no-changes */
1427 /* Inform the core about resumes-in-progress by returning
1428 * a non-zero value even if there are no status changes.
1429 */
1433 // PORT_RESUME from hardware ~= PORT_STAT_C_SUSPEND
1435 /* no hub change reports (bit 0) for now (power, ...) */
1437 /* port N changes (bit N)? */
1442 /*
1443 * Return status information even for ports with OWNER set.
1444 * Otherwise khubd wouldn't see the disconnect event when a
1445 * high-speed device is switched over to the companion
1446 * controller by the user.
1447 */
1454 }
1455 /* FIXME autosuspend idle root hubs */
1458 }
1460 /*-------------------------------------------------------------------------*/
1462 static void
1466 ) {
1468 u16 temp;
1478 /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
1485 }
1487 /*-------------------------------------------------------------------------*/
1491 u16 typeReq,
1492 u16 wValue,
1493 u16 wIndex,
1495 u16 wLength
1496 ) {
1505 /*
1506 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
1507 * HCS_INDICATOR may say we can change LEDs to off/amber/green.
1508 * (track current state ourselves) ... blink for diagnostics,
1509 * power, "this is the one", etc. EHCI spec supports this.
1510 */
1518 /* no hub-wide feature/status flags */
1522 }
1527 wIndex--;
1531 /*
1532 * Even if OWNER is set, so the port is owned by the
1533 * companion controller, khubd needs to be able to clear
1534 * the port-change status bits (especially
1535 * USB_PORT_STAT_C_CONNECTION).
1536 */
1553 /* resume signaling for 20 msec */
1568 /* GetPortStatus clears reset */
1572 }
1577 buf);
1580 /* no hub-wide feature/status flags */
1582 //cpu_to_le32s ((u32 *) buf);
1587 wIndex--;
1591 // wPortChange bits
1601 /* whoever resumes must GetPortStatus to complete it!! */
1604 /* Remote Wakeup received? */
1606 /* resume signaling for 20 msec */
1609 /* check the port again */
1612 }
1614 /* resume completed? */
1621 /* stop resume signaling */
1625 status_reg);
1634 }
1636 }
1637 }
1639 /* whoever resets must GetPortStatus to complete it!! */
1647 /* force reset to complete */
1649 status_reg);
1650 /* REVISIT: some hardware needs 550+ usec to clear
1651 * this bit; seems too long to spin routinely...
1652 */
1659 }
1661 /* see what we found out */
1664 }
1669 }
1671 /* transfer dedicated ports to the companion hc */
1678 }
1680 /*
1681 * Even if OWNER is set, there's no harm letting khubd
1682 * see the wPortStatus values (they should all be 0 except
1683 * for PORT_POWER anyway).
1684 */
1689 }
1693 /* maybe the port was unsuspended without our knowledge */
1702 }
1720 /* no hub-wide feature/status flags */
1724 }
1732 wIndex--;
1741 /* After above check the port must be connected.
1742 * Set appropriate bit thus could put phy into low power
1743 * mode if we have hostpc feature
1744 */
1751 /* line status bits may report this as low speed,
1752 * which can be fine if this root hub has a
1753 * transaction translator built in.
1754 */
1759 /*
1760 * caller must wait, then call GetPortStatus
1761 * usb 2.0 spec says 50 ms resets on root
1762 */
1768 /* For downstream facing ports (these): one hub port is put
1769 * into test mode according to USB2 11.24.2.13, then the hub
1770 * must be reset (which for root hub now means rmmod+modprobe,
1771 * or else system reboot). See EHCI 2.3.9 and 4.14 for info
1772 * about the EHCI-specific stuff.
1773 */
1781 /* Put all enabled ports into suspend */
1785 status_reg);
1798 }
1803 error:
1804 /* "stall" on error */
1806 }
1809 }
1813 {
1815 }
1819 {
1821 }
1822 /*-------------------------------------------------------------------------*/
1823 /*
1824 * There's basically three types of memory:
1825 * - data used only by the HCD ... kmalloc is fine
1826 * - async and periodic schedules, shared by HC and HCD ... these
1827 * need to use dma_pool or dma_alloc_coherent
1828 * - driver buffers, read/written by HC ... single shot DMA mapped
1829 *
1830 * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
1831 * No memory seen by this driver is pageable.
1832 */
1834 /*-------------------------------------------------------------------------*/
1836 /* Allocate the key transfer structures from the previously allocated pool */
1839 dma_addr_t dma)
1840 {
1847 }
1850 {
1852 dma_addr_t dma;
1857 }
1859 }
1862 {
1864 }
1868 {
1869 /* clean qtds first, and know this is not linked */
1873 }
1878 }
1881 {
1883 dma_addr_t dma;
1894 // INIT_LIST_HEAD (&qh->qh_list);
1897 /* dummy td enables safe urb queuing */
1902 }
1903 done:
1905 fail1:
1907 fail:
1910 }
1912 /*-------------------------------------------------------------------------*/
1914 /* The queue heads and transfer descriptors are managed from pools tied
1915 * to each of the "per device" structures.
1916 * This is the initialisation and cleanup code.
1917 */
1920 {
1929 /* DMA consistent memory and pools */
1937 }
1949 /* shadow periodic table */
1952 }
1954 /* remember to add cleanup code (above) if you add anything here */
1956 {
1959 /* QTDs for control/bulk/intr transfers */
1967 }
1969 /* QHs for control/bulk/intr transfers */
1977 }
1981 }
1983 /* ITD for high speed ISO transfers */
1991 }
1993 /* Hardware periodic table */
2000 }
2005 /* software shadow of hardware table */
2010 fail:
2014 }
2015 /*-------------------------------------------------------------------------*/
2016 /*
2017 * EHCI hardware queue manipulation ... the core. QH/QTD manipulation.
2018 *
2019 * Control, bulk, and interrupt traffic all use "qh" lists. They list "qtd"
2020 * entries describing USB transactions, max 16-20kB/entry (with 4kB-aligned
2021 * buffers needed for the larger number). We use one QH per endpoint, queue
2022 * multiple urbs (all three types) per endpoint. URBs may need several qtds.
2023 *
2024 * ISO traffic uses "ISO TD" (itd) records, and (along with
2025 * interrupts) needs careful scheduling. Performance improvements can be
2026 * an ongoing challenge. That's in "ehci-sched.c".
2027 *
2028 * USB 1.1 devices are handled (a) by "companion" OHCI or UHCI root hubs,
2029 * or otherwise through transaction translators (TTs) in USB 2.0 hubs using
2030 * (b) special fields in qh entries or (c) split iso entries. TTs will
2031 * buffer low/full speed data so the host collects it at high speed.
2032 */
2034 /*-------------------------------------------------------------------------*/
2036 /* fill a qtd, returning how much of the buffer we were able to queue up */
2038 static int
2041 {
2045 /* one buffer entry per 4K ... first might be short or unaligned */
2055 /* per-qtd limit: from 16K to 20K (best alignment) */
2064 else
2066 }
2068 /* short packets may only terminate transfers */
2071 }
2076 }
2078 /*-------------------------------------------------------------------------*/
2082 {
2085 /* writes to an active overlay are unsafe */
2091 /* Except for control endpoints, we make hardware maintain data
2092 * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
2093 * and set the pseudo-toggle in udev. Only usb_clear_halt() will
2094 * ever clear it.
2095 */
2104 }
2105 }
2108 }
2110 /* if it weren't for a common silicon quirk (writing the dummy into the qh
2111 * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
2112 * recovery (including urb dequeue) would need software changes to a QH...
2113 */
2114 static void
2116 {
2124 /*
2125 * first qtd may already be partially processed.
2126 * If we come here during unlink, the QH overlay region
2127 * might have reference to the just unlinked qtd. The
2128 * qtd is updated in qh_completions(). Update the QH
2129 * overlay here.
2130 */
2134 }
2135 }
2139 }
2141 /*-------------------------------------------------------------------------*/
2147 {
2158 }
2162 {
2164 /* If an async split transaction gets an error or is unlinked,
2165 * the TT buffer may be left in an indeterminate state. We
2166 * have to clear the TT buffer.
2167 *
2168 * Note: this routine is never called for Isochronous transfers.
2169 */
2182 }
2183 }
2184 }
2190 u32 token
2191 )
2192 {
2195 /* count IN/OUT bytes, not SETUP (even short packets) */
2199 /* don't modify error codes */
2203 /* force cleanup after short read; not always an error */
2207 /* serious "can't proceed" faults reported by the hardware */
2210 /* FIXME "must" disable babbling device's port too */
2212 /* CERR nonzero + halt --> stall */
2216 /* In theory, more than one of the following bits can be set
2217 * since they are sticky and the transaction is retried.
2218 * Which to test first is rather arbitrary.
2219 */
2221 /* fs/ls interrupt xfer missed the complete-split */
2228 /* timeout, bad CRC, wrong PID, etc */
2236 }
2244 }
2247 }
2249 static void
2253 {
2257 /* S-mask in a QH means it's an interrupt urb */
2260 /* ... update hc-wide periodic stats (for usbfs) */
2262 }
2263 }
2268 /* report non-error and short read status as zero */
2272 }
2274 #ifdef FUSBH200_URB_TRACE
2280 status,
2282 #endif
2284 /* complete() can reenter this HCD */
2289 }
2293 /*
2294 * Process and free completed qtds for a qh, returning URBs to drivers.
2295 * Chases up to qh->hw_current. Returns number of completions called,
2296 * indicating how much "real" work we did.
2297 */
2298 static unsigned
2300 {
2306 u8 state;
2312 /* completions (or tasks on other cpus) must never clobber HALT
2313 * till we've gone through and cleaned everything up, even when
2314 * they add urbs to this qh's queue or mark them for unlinking.
2315 *
2316 * NOTE: unlinking expects to be done in queue order.
2317 *
2318 * It's a bug for qh->qh_state to be anything other than
2319 * QH_STATE_IDLE, unless our caller is scan_async() or
2320 * scan_intr().
2321 */
2326 rescan:
2331 /* remove de-activated QTDs from front of queue.
2332 * after faults (including short reads), cleanup this urb
2333 * then let the queue advance.
2334 * if queue is stopped, handles unlinks.
2335 */
2344 /* clean up any state from previous QTD ...*/
2348 count++;
2350 }
2353 }
2355 /* ignore urbs submitted during completions we reported */
2359 /* hardware copies qtd out of qh overlay */
2363 /* always clean up qtds the hc de-activated */
2364 retry_xacterr:
2367 /* Report Data Buffer Error: non-fatal but useful */
2371 urb,
2375 qtd,
2376 qh);
2378 /* on STALL, error, and short reads this urb must
2379 * complete and all its qtds must be recycled.
2380 */
2383 /* retry transaction errors until we
2384 * reach the software xacterr limit
2385 */
2394 /* reset the token in the qtd and the
2395 * qh overlay (which still contains
2396 * the qtd) so that we pick up from
2397 * where we left off
2398 */
2403 token);
2406 token);
2408 }
2411 /* magic dummy for some short reads; qh won't advance.
2412 * that silicon quirk can kick in with this dummy too.
2413 *
2414 * other short reads won't stop the queue, including
2415 * control transfers (status stage handles that) or
2416 * most other single-qtd reads ... the queue stops if
2417 * URB_SHORT_NOT_OK was set so the driver submitting
2418 * the urbs could clean it up.
2419 */
2424 }
2426 /* stop scanning when we reach qtds the hc is using */
2431 /* scan the whole queue for unlinks whenever it stops */
2435 /* cancel everything if we halt, suspend, etc */
2439 /* this qtd is active; skip it unless a previous qtd
2440 * for its urb faulted, or its urb was canceled.
2441 */
2445 /* qh unlinked; token in overlay may be most current */
2451 /* An unlink may leave an incomplete
2452 * async transaction in the TT buffer.
2453 * We have to clear it.
2454 */
2456 }
2457 }
2459 /* unless we already know the urb's status, collect qtd status
2460 * and update count of bytes transferred. in common short read
2461 * cases with only one data qtd (including control transfers),
2462 * queue processing won't halt. but with two or more qtds (for
2463 * example, with a 32 KB transfer), when the first qtd gets a
2464 * short read the second must be removed by hand.
2465 */
2474 /* As part of low/full-speed endpoint-halt processing
2475 * we must clear the TT buffer (11.17.5).
2476 */
2479 /* The TT's in some hubs malfunction when they
2480 * receive this request following a STALL (they
2481 * stop sending isochronous packets). Since a
2482 * STALL can't leave the TT buffer in a busy
2483 * state (if you believe Figures 11-48 - 11-51
2484 * in the USB 2.0 spec), we won't clear the TT
2485 * buffer in this case. Strictly speaking this
2486 * is a violation of the spec.
2487 */
2490 token);
2491 }
2492 }
2494 /* if we're removing something not at the queue head,
2495 * patch the hardware queue pointer.
2496 */
2501 }
2503 /* remove qtd; it's recycled after possible urb completion */
2507 /* reinit the xacterr counter for the next qtd */
2509 }
2511 /* last urb's completion might still need calling */
2514 count++;
2516 }
2518 /* Do we need to rescan for URBs dequeued during a giveback? */
2520 /* If the QH is already unlinked, do the rescan now. */
2524 /* Otherwise we have to wait until the QH is fully unlinked.
2525 * Our caller will start an unlink if qh->needs_rescan is
2526 * set. But if an unlink has already started, nothing needs
2527 * to be done.
2528 */
2531 }
2533 /* restore original state; caller must unlink or relink */
2536 /* be sure the hardware's done with the qh before refreshing
2537 * it after fault cleanup, or recovering from silicon wrongly
2538 * overlaying the dummy qtd (which reduces DMA chatter).
2539 */
2546 /* We won't refresh a QH that's linked (after the HC
2547 * stopped the queue). That avoids a race:
2548 * - HC reads first part of QH;
2549 * - CPU updates that first part and the token;
2550 * - HC reads rest of that QH, including token
2551 * Result: HC gets an inconsistent image, and then
2552 * DMAs to/from the wrong memory (corrupting it).
2553 *
2554 * That should be rare for interrupt transfers,
2555 * except maybe high bandwidth ...
2556 */
2558 /* Tell the caller to start an unlink */
2561 /* otherwise, unlink already started */
2562 }
2563 }
2566 }
2568 /*-------------------------------------------------------------------------*/
2570 // high bandwidth multiplier, as encoded in highspeed endpoint descriptors
2571 #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
2572 // ... and packet size, for any kind of endpoint descriptor
2573 #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
2575 /*
2576 * reverse of qh_urb_transaction: free a list of TDs.
2577 * used for cleanup after errors, before HC sees an URB's TDs.
2578 */
2583 ) {
2592 }
2593 }
2595 /*
2596 * create a list of filled qtds for this URB; won't link into qh.
2597 */
2603 gfp_t flags
2604 ) {
2606 dma_addr_t buf;
2609 u32 token;
2613 /*
2614 * URBs map to sequences of QTDs: one logical transaction
2615 */
2624 /* for split transactions, SplitXState initialized to zero */
2629 /* SETUP pid */
2634 /* ... and always at least one more pid */
2644 /* for zero length DATA stages, STATUS is always IN */
2647 }
2649 /*
2650 * data transfer stage: buffer setup
2651 */
2657 /* urb->transfer_buffer_length may be smaller than the
2658 * size of the scatterlist (or vice versa)
2659 */
2665 }
2669 /* else it's already initted to "out" pid (0 << 8) */
2673 /*
2674 * buffer gets wrapped in one or more qtds;
2675 * last one may be "short" (including zero len)
2676 * and may serve as a control status ack
2677 */
2682 maxpacket);
2687 /*
2688 * short reads advance to a "magic" dummy instead of the next
2689 * qtd ... that forces the queue to stop, for manual cleanup.
2690 * (this will usually be overridden later.)
2691 */
2695 /* qh makes control packets use qtd toggle; maybe switch it */
2705 }
2714 }
2716 /*
2717 * unless the caller requires manual cleanup after short reads,
2718 * have the alt_next mechanism keep the queue running after the
2719 * last data qtd (the only one, for control and most other cases).
2720 */
2725 /*
2726 * control requests may need a terminating data "status" ack;
2727 * other OUT ones may need a terminating short packet
2728 * (zero length).
2729 */
2741 }
2751 /* never any data in such packets */
2753 }
2754 }
2756 /* by default, enable interrupt on urb completion */
2761 cleanup:
2764 }
2766 /*-------------------------------------------------------------------------*/
2768 // Would be best to create all qh's from config descriptors,
2769 // when each interface/altsetting is established. Unlink
2770 // any previous qh and cancel its urbs first; endpoints are
2771 // implicitly reset then (data toggle too).
2772 // That'd mean updating how usbcore talks to HCDs. (2.7?)
2775 /*
2776 * Each QH holds a qtd list; a QH is used for everything except iso.
2777 *
2778 * For interrupt urbs, the scheduler must set the microframe scheduling
2779 * mask(s) each time the QH gets scheduled. For highspeed, that's
2780 * just one microframe in the s-mask. For split interrupt transactions
2781 * there are additional complications: c-mask, maybe FSTNs.
2782 */
2787 gfp_t flags
2788 ) {
2799 /*
2800 * init endpoint/device data for this QH
2801 */
2809 /* 1024 byte maxpacket is a hardware ceiling. High bandwidth
2810 * acts like up to 3KB, but is built from smaller packets.
2811 */
2815 }
2817 /* Compute interrupt scheduling parameters just once, and save.
2818 * - allowing for high bandwidth, how many nsec/uframe are used?
2819 * - split transactions need a second CSPLIT uframe; same question
2820 * - splits also need a schedule gap (for full/low speed I/O)
2821 * - qh has a polling interval
2822 *
2823 * For control/bulk requests, the HC or TT handles these.
2824 */
2837 /* NOTE interval 2 or 4 uframes could work.
2838 * But interval 1 scheduling is simpler, and
2839 * includes high bandwidth.
2840 */
2845 }
2849 /* gap is f(FS/LS transfer times) */
2853 /* FIXME this just approximates SPLIT/CSPLIT times */
2860 }
2870 }
2871 }
2872 }
2874 /* support for tt scheduling, and access to toggles */
2877 /* using TT? */
2881 /* FALL THROUGH */
2884 /* EPS 0 means "full" */
2890 }
2895 /* Some Freescale processors have an erratum in which the
2896 * port number in the queue head was 0..N-1 instead of 1..N.
2897 */
2900 else
2903 /* set the address of the TT; for TDI's integrated
2904 * root hub tt, leave it zeroed.
2905 */
2909 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
2922 /* The USB spec says that high speed bulk endpoints
2923 * always use 512 byte maxpacket. But some device
2924 * vendors decided to ignore that, and MSFT is happy
2925 * to help them do so. So now people expect to use
2926 * such nonconformant devices with Linux too; sigh.
2927 */
2933 }
2938 done:
2941 }
2943 /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
2945 /* init as live, toggle clear, advance to dummy */
2954 }
2956 /*-------------------------------------------------------------------------*/
2959 {
2963 /* Stop waiting to turn off the async schedule */
2966 /* Don't start the schedule until ASS is 0 */
2969 }
2972 {
2976 /* The async schedule and async_unlink list are supposed to be empty */
2979 /* Don't turn off the schedule until ASS is 1 */
2981 }
2983 /* move qh (and its qtds) onto async queue; maybe enable queue. */
2986 {
2990 /* Don't link a QH if there's a Clear-TT-Buffer pending */
2996 /* clear halt and/or toggle; and maybe recover from silicon quirk */
2999 /* splice right after start */
3010 /* qtd completions reported later by interrupt */
3013 }
3015 /*-------------------------------------------------------------------------*/
3017 /*
3018 * For control/bulk/interrupt, return QH with these TDs appended.
3019 * Allocates and initializes the QH if necessary.
3020 * Returns null if it can't allocate a QH it needs to.
3021 * If the QH has TDs (urbs) already, that's great.
3022 */
3029 )
3030 {
3036 /* can't sleep here, we have fusbh200->lock... */
3039 }
3045 else
3047 qtd_list);
3049 /* control qh may need patching ... */
3052 /* usb_reset_device() briefly reverts to address 0 */
3055 }
3057 /* just one way to queue requests: swap with the dummy qtd.
3058 * only hc or qh_refresh() ever modify the overlay.
3059 */
3062 dma_addr_t dma;
3063 __hc32 token;
3065 /* to avoid racing the HC, use the dummy td instead of
3066 * the first td of our list (becomes new dummy). both
3067 * tds stay deactivated until we're done, when the
3068 * HC is allowed to fetch the old dummy (4.10.2).
3069 */
3086 /* hc must see the new dummy at list end */
3092 /* let the hc process these next qtds */
3097 }
3098 }
3100 }
3102 /*-------------------------------------------------------------------------*/
3104 static int
3109 gfp_t mem_flags
3110 ) {
3118 #ifdef FUSBH200_URB_TRACE
3119 {
3128 }
3129 #endif
3135 }
3145 }
3147 /* Control/bulk operations through TTs don't need scheduling,
3148 * the HC and TT handle it when the TT has a buffer ready.
3149 */
3152 done:
3157 }
3159 /*-------------------------------------------------------------------------*/
3162 {
3165 /* Add to the end of the list of QHs waiting for the next IAAD */
3169 else
3173 /* Unlink it from the schedule */
3182 }
3185 {
3186 /*
3187 * Do nothing if an IAA cycle is already running or
3188 * if one will be started shortly.
3189 */
3193 /* Do all the waiting QHs at once */
3197 /* If the controller isn't running, we don't have to wait for it */
3202 /* Otherwise start a new IAA cycle */
3204 /* Make sure the unlinks are all visible to the hardware */
3211 }
3212 }
3214 /* the async qh for the qtds being unlinked are now gone from the HC */
3217 {
3220 /* Process the idle QHs */
3221 restart:
3236 }
3239 /* Start a new IAA cycle if any QHs are waiting for it */
3244 }
3245 }
3248 {
3253 /* Unlink all the async QHs that have been empty for a timer cycle */
3264 else
3266 }
3267 }
3269 /* Start a new IAA cycle if any QHs are waiting for it */
3273 /* QHs that haven't been empty for long enough will be handled later */
3277 }
3278 }
3280 /* makes sure the async qh will become idle */
3281 /* caller must own fusbh200->lock */
3284 {
3285 /*
3286 * If the QH isn't linked then there's nothing we can do
3287 * unless we were called during a giveback, in which case
3288 * qh_completions() has to deal with it.
3289 */
3294 }
3298 }
3300 /*-------------------------------------------------------------------------*/
3303 {
3311 rescan:
3312 /* clean any finished work for this qh */
3316 /*
3317 * Unlinks could happen here; completion reporting
3318 * drops the lock. That's why fusbh200->qh_scan_next
3319 * always holds the next qh to scan; if the next qh
3320 * gets unlinked then fusbh200->qh_scan_next is adjusted
3321 * in single_unlink_async().
3322 */
3332 }
3333 }
3335 /*
3336 * Unlink empty entries, reducing DMA usage as well
3337 * as HCD schedule-scanning costs. Delay for any qh
3338 * we just scanned, there's a not-unusual case that it
3339 * doesn't stay idle for long.
3340 */
3346 }
3347 }
3348 /*-------------------------------------------------------------------------*/
3349 /*
3350 * EHCI scheduled transaction support: interrupt, iso, split iso
3351 * These are called "periodic" transactions in the EHCI spec.
3352 *
3353 * Note that for interrupt transfers, the QH/QTD manipulation is shared
3354 * with the "asynchronous" transaction support (control/bulk transfers).
3355 * The only real difference is in how interrupt transfers are scheduled.
3356 *
3357 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
3358 * It keeps track of every ITD (or SITD) that's linked, and holds enough
3359 * pre-calculated schedule data to make appending to the queue be quick.
3360 */
3364 /*-------------------------------------------------------------------------*/
3366 /*
3367 * periodic_next_shadow - return "next" pointer on shadow list
3368 * @periodic: host pointer to qh/itd
3369 * @tag: hardware tag for type of this record
3370 */
3373 __hc32 tag)
3374 {
3382 }
3383 }
3387 __hc32 tag)
3388 {
3390 /* our fusbh200_shadow.qh is actually software part */
3393 /* others are hw parts */
3396 }
3397 }
3399 /* caller must hold fusbh200->lock */
3401 {
3406 /* find predecessor of "ptr"; hw and shadow lists are in sync */
3413 }
3414 /* an interrupt entry (at list end) could have been shared */
3418 /* update shadow and hardware lists ... the old "next" pointers
3419 * from ptr may still be in use, the caller updates them.
3420 */
3426 }
3428 /* how many of the uframe's 125 usecs are allocated? */
3429 static unsigned short
3431 {
3441 /* is it in the S-mask? */
3444 /* ... or C-mask? */
3451 // case Q_TYPE_FSTN:
3453 /* for "save place" FSTNs, count the relevant INTR
3454 * bandwidth from the previous frame
3455 */
3458 }
3468 }
3469 }
3474 }
3476 /*-------------------------------------------------------------------------*/
3479 {
3486 else
3488 }
3490 /* return true iff the device's transaction translator is available
3491 * for a periodic transfer starting at the specified frame, using
3492 * all the uframes in the mask.
3493 */
3499 u32 uf_mask
3500 )
3501 {
3505 /* note bandwidth wastage: split never follows csplit
3506 * (different dev or endpoint) until the next uframe.
3507 * calling convention doesn't make that distinction.
3508 */
3511 __hc32 type;
3525 u32 mask;
3529 /* "knows" no gap is needed */
3533 }
3537 // case Q_TYPE_FSTN:
3542 }
3544 /* collision or error */
3546 }
3547 }
3549 /* no collision */
3551 }
3553 /*-------------------------------------------------------------------------*/
3556 {
3560 /* Stop waiting to turn off the periodic schedule */
3563 /* Don't start the schedule until PSS is 0 */
3566 }
3569 {
3573 /* Don't turn off the schedule until PSS is 1 */
3575 }
3577 /*-------------------------------------------------------------------------*/
3579 /* periodic schedule slots have iso tds (normal or split) first, then a
3580 * sparse tree for active interrupt transfers.
3581 *
3582 * this just links in a qh; caller guarantees uframe masks are set right.
3583 * no FSTN support (yet; fusbh200 0.96+)
3584 */
3586 {
3596 /* high bandwidth, or otherwise every microframe */
3606 /* skip the iso nodes at list head */
3614 }
3616 /* sorting each branch by period (slow-->fast)
3617 * enables sharing interior tree nodes
3618 */
3625 }
3626 /* link in this qh, unless some earlier pass did that */
3634 }
3635 }
3639 /* update per-qh bandwidth for usbfs */
3646 /* maybe enable periodic schedule processing */
3649 }
3652 {
3656 /*
3657 * If qh is for a low/full-speed device, simply unlinking it
3658 * could interfere with an ongoing split transaction. To unlink
3659 * it safely would require setting the QH_INACTIVATE bit and
3660 * waiting at least one frame, as described in EHCI 4.12.2.5.
3661 *
3662 * We won't bother with any of this. Instead, we assume that the
3663 * only reason for unlinking an interrupt QH while the current URB
3664 * is still active is to dequeue all the URBs (flush the whole
3665 * endpoint queue).
3666 *
3667 * If rebalancing the periodic schedule is ever implemented, this
3668 * approach will no longer be valid.
3669 */
3671 /* high bandwidth, or otherwise part of every microframe */
3678 /* update per-qh bandwidth for usbfs */
3689 /* qh->qh_next still "live" to HC */
3697 }
3700 {
3701 /* If the QH isn't linked then there's nothing we can do
3702 * unless we were called during a giveback, in which case
3703 * qh_completions() has to deal with it.
3704 */
3709 }
3713 /* Make sure the unlinks are visible before starting the timer */
3716 /*
3717 * The EHCI spec doesn't say how long it takes the controller to
3718 * stop accessing an unlinked interrupt QH. The timer delay is
3719 * 9 uframes; presumably that will be long enough.
3720 */
3723 /* New entries go at the end of the intr_unlink list */
3726 else
3737 }
3738 }
3741 {
3750 /* reschedule QH iff another request is queued */
3754 /* An error here likely indicates handshake failure
3755 * or no space left in the schedule. Neither fault
3756 * should happen often ...
3757 *
3758 * FIXME kill the now-dysfunctional queued urbs
3759 */
3763 }
3765 /* maybe turn off periodic schedule */
3768 }
3770 /*-------------------------------------------------------------------------*/
3777 unsigned usecs
3778 ) {
3781 /* complete split running into next frame?
3782 * given FSTN support, we could sometimes check...
3783 */
3787 /* convert "usecs we need" to "max already claimed" */
3790 /* we "know" 2 and 4 uframe intervals were rejected; so
3791 * for period 0, check _every_ microframe in the schedule.
3792 */
3799 }
3802 /* just check the specified uframe, at that period */
3809 }
3811 // success!
3813 }
3820 __hc32 *c_maskp
3821 )
3822 {
3835 }
3837 /* Make sure this tt's buffer is also available for CSPLITs.
3838 * We pessimize a bit; probably the typical full speed case
3839 * doesn't need the second CSPLIT.
3840 *
3841 * NOTE: both SPLIT and CSPLIT could be checked in just
3842 * one smart pass...
3843 */
3856 }
3857 done:
3859 }
3861 /* "first fit" scheduling policy used the first time through,
3862 * or when the previous schedule slot can't be re-used.
3863 */
3865 {
3868 __hc32 c_mask;
3876 /* reuse the previous schedule slots, if we can */
3885 }
3887 /* else scan the schedule to find a group of slots such that all
3888 * uframes have enough periodic bandwidth available.
3889 */
3891 /* "normal" case, uframing flexible except with splits */
3903 }
3904 }
3906 /* qh->period == 0 means every uframe */
3910 }
3915 /* reset S-frame and (maybe) C-frame masks */
3924 /* stuff into the periodic schedule */
3926 done:
3928 }
3934 gfp_t mem_flags
3935 ) {
3942 /* get endpoint and transfer/schedule data */
3950 }
3955 /* get qh and force any scheduling errors */
3961 }
3965 }
3967 /* then queue the urb's tds to the qh */
3971 /* ... update usbfs periodic stats */
3974 done:
3977 done_not_linked:
3983 }
3986 {
3990 intr_node) {
3991 rescan:
3992 /* clean any finished work for this qh */
3996 /*
3997 * Unlinks could happen here; completion reporting
3998 * drops the lock. That's why fusbh200->qh_scan_next
3999 * always holds the next qh to scan; if the next qh
4000 * gets unlinked then fusbh200->qh_scan_next is adjusted
4001 * in qh_unlink_periodic().
4002 */
4010 }
4011 }
4012 }
4014 /*-------------------------------------------------------------------------*/
4016 /* fusbh200_iso_stream ops work with both ITD and SITD */
4020 {
4028 }
4030 }
4032 static void
4038 unsigned interval
4039 )
4040 {
4041 u32 buf1;
4047 /*
4048 * this might be a "high bandwidth" highspeed endpoint,
4049 * as encoded in the ep descriptor's wMaxPacket field
4050 */
4058 }
4069 /* usbfs wants to report the average usecs per frame tied up
4070 * when transfers on this endpoint are scheduled ...
4071 */
4080 }
4089 }
4093 {
4102 else
4115 }
4117 /* if dev->ep [epnum] is a QH, hw is set */
4123 }
4127 }
4129 /*-------------------------------------------------------------------------*/
4131 /* fusbh200_iso_sched ops can be ITD-only or SITD-only */
4135 {
4143 }
4145 }
4153 )
4154 {
4158 /* how many uframes are needed for these transfers */
4161 /* figure out per-uframe itd fields that we'll need later
4162 * when we fit new itds into the schedule.
4163 */
4167 dma_addr_t buf;
4168 u32 trans;
4181 /* might need to cross a buffer page within a uframe */
4186 }
4187 }
4189 static void
4193 )
4194 {
4197 // caller must hold fusbh200->lock!
4200 }
4202 static int
4207 gfp_t mem_flags
4208 )
4209 {
4211 dma_addr_t itd_dma;
4225 else
4228 /* allocate/init ITDs */
4232 /*
4233 * Use iTDs from the free list, but not iTDs that may
4234 * still be in use by the hardware.
4235 */
4244 alloc_itd:
4253 }
4254 }
4259 }
4262 /* temporarily store schedule info in hcpriv */
4266 }
4268 /*-------------------------------------------------------------------------*/
4273 u32 mod,
4274 u32 uframe,
4275 u8 usecs,
4276 u32 period
4277 )
4278 {
4281 /* can't commit more than uframe_periodic_max usec */
4286 /* we know urb->interval is 2^N uframes */
4290 }
4292 /*
4293 * This scheduler plans almost as far into the future as it has actual
4294 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
4295 * "as small as possible" to be cache-friendlier.) That limits the size
4296 * transfers you can stream reliably; avoid more than 64 msec per urb.
4297 * Also avoid queue depths of less than fusbh200's worst irq latency (affected
4298 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
4299 * and other factors); or more than about 230 msec total (for portability,
4300 * given FUSBH200_TUNE_FLS and the slop). Or, write a smarter scheduler!
4301 */
4305 static int
4310 )
4311 {
4324 }
4328 /* Typical case: reuse current schedule, stream is still active.
4329 * Hopefully there are no gaps from the host falling behind
4330 * (irq delays etc), but if there are we'll take the next
4331 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
4332 */
4334 u32 excess;
4336 /* For high speed devices, allow scheduling within the
4337 * isochronous scheduling threshold. For full speed devices
4338 * and Intel PCI-based controllers, don't (work around for
4339 * Intel ICH9 bug).
4340 */
4343 else
4346 /* Fell behind (by up to twice the slop amount)?
4347 * We decide based on the time of the last currently-scheduled
4348 * slot, not the time of the next available slot.
4349 */
4354 else
4359 mod);
4362 }
4363 }
4365 /* need to schedule; when's the next (u)frame we could start?
4366 * this is bigger than fusbh200->i_thresh allows; scheduling itself
4367 * isn't free, the slop should handle reasonably slow cpus. it
4368 * can also help high bandwidth if the dma and irq loads don't
4369 * jump until after the queue is primed.
4370 */
4375 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
4377 /* find a uframe slot with enough bandwidth.
4378 * Early uframes are more precious because full-speed
4379 * iso IN transfers can't use late uframes,
4380 * and therefore they should be allocated last.
4381 */
4385 start--;
4386 /* check schedule: enough space? */
4392 /* no room in the schedule */
4398 }
4399 }
4401 /* Tried to schedule too far into the future? */
4409 }
4413 /* report high speed start in uframes; full speed, in frames */
4418 /* Make sure scan_isoc() sees these */
4423 fail:
4427 }
4429 /*-------------------------------------------------------------------------*/
4434 {
4437 /* it's been recently zeroed */
4446 /* All other fields are filled when scheduling */
4447 }
4455 u16 uframe
4456 )
4457 {
4461 // BUG_ON (pg == 6 && uf->cross);
4471 /* iso_frame_desc[].offset must be strictly increasing */
4478 }
4479 }
4483 {
4489 /* skip any iso nodes which might belong to previous microframes */
4497 }
4505 }
4507 /* fit urb's itds into the selected schedule slot; activate as needed */
4513 )
4514 {
4531 }
4533 /* fill iTDs uframe by uframe */
4536 /* ASSERT: we have all necessary itds */
4537 // BUG_ON (list_empty (&iso_sched->td_list));
4539 /* ASSERT: no itds for this endpoint in this uframe */
4547 }
4556 packet++;
4558 /* link completed itds into the schedule */
4563 }
4564 }
4567 /* don't need that schedule data any more */
4573 }
4575 #define ISO_ERRS (FUSBH200_ISOC_BUF_ERR | FUSBH200_ISOC_BABBLE | FUSBH200_ISOC_XACTERR)
4577 /* Process and recycle a completed ITD. Return true iff its urb completed,
4578 * and hence its completion callback probably added things to the hardware
4579 * schedule.
4580 *
4581 * Note that we carefully avoid recycling this descriptor until after any
4582 * completion callback runs, so that it won't be reused quickly. That is,
4583 * assuming (a) no more than two urbs per frame on this endpoint, and also
4584 * (b) only this endpoint's completions submit URBs. It seems some silicon
4585 * corrupts things if you reuse completed descriptors very quickly...
4586 */
4588 {
4591 u32 t;
4598 /* for each uframe with a packet */
4608 /* report transfer status */
4620 /* HC need not update length with this error */
4624 }
4630 /* URB was too late */
4632 }
4633 }
4635 /* handle completion now? */
4639 /* ASSERT: it's really the last itd for this urb
4640 list_for_each_entry (itd, &stream->td_list, itd_list)
4641 BUG_ON (itd->urb == urb);
4642 */
4644 /* give urb back to the driver; completion often (re)submits */
4660 }
4662 done:
4665 /* Add to the end of the free list for later reuse */
4668 /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */
4673 }
4676 }
4678 /*-------------------------------------------------------------------------*/
4681 gfp_t mem_flags)
4682 {
4687 /* Get iso_stream head */
4692 }
4698 }
4700 #ifdef FUSBH200_URB_TRACE
4708 stream);
4709 #endif
4711 /* allocate ITDs w/o locking anything */
4716 }
4718 /* schedule ... need to lock */
4723 }
4730 else
4732 done_not_linked:
4734 done:
4736 }
4738 /*-------------------------------------------------------------------------*/
4741 {
4746 /*
4747 * When running, scan from last scan point up to "now"
4748 * else clean up by scanning everything that's left.
4749 * Touches as few pages as possible: cache-friendly.
4750 */
4758 }
4766 restart:
4767 /* scan each element in frame's queue for completions */
4777 /* If this ITD is still active, leave it for
4778 * later processing ... check the next entry.
4779 * No need to check for activity unless the
4780 * frame is current.
4781 */
4788 }
4796 }
4797 }
4799 /* Take finished ITDs out of the schedule
4800 * and process them: recycle, maybe report
4801 * URB completion. HC won't cache the
4802 * pointer for much longer, if at all.
4803 */
4814 // BUG ();
4815 /* FALL THROUGH */
4818 /* End of the iTDs and siTDs */
4821 }
4823 /* assume completion callbacks modify the queue */
4826 }
4828 /* Stop when we have reached the current frame */
4832 }
4834 }
4835 /*-------------------------------------------------------------------------*/
4836 /*
4837 * Display / Set uframe_periodic_max
4838 */
4842 {
4849 }
4855 {
4861 ssize_t ret;
4871 }
4875 /*
4876 * lock, so that our checking does not race with possible periodic
4877 * bandwidth allocation through submitting new urbs.
4878 */
4881 /*
4882 * for request to decrease max periodic bandwidth, we have to check
4883 * every microframe in the schedule to see whether the decrease is
4884 * possible.
4885 */
4896 "cannot decrease uframe_periodic_max becase "
4897 "periodic bandwidth is already allocated "
4901 }
4902 }
4904 /* increasing is always ok */
4916 out_unlock:
4919 }
4920 static DEVICE_ATTR(uframe_periodic_max, 0644, show_uframe_periodic_max, store_uframe_periodic_max);
4924 {
4932 out:
4934 }
4937 {
4941 }
4942 /*-------------------------------------------------------------------------*/
4944 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
4945 * The firmware seems to think that powering off is a wakeup event!
4946 * This routine turns off remote wakeup and everything else, on all ports.
4947 */
4949 {
4953 }
4955 /*
4956 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
4957 * Must be called with interrupts enabled and the lock not held.
4958 */
4960 {
4967 }
4969 /* fusbh200_shutdown kick in for silicon on any bus (not just pci, etc).
4970 * This forcibly disables dma and IRQs, helping kexec and other cases
4971 * where the next system software may expect clean state.
4972 */
4974 {
4986 }
4988 /*-------------------------------------------------------------------------*/
4990 /*
4991 * fusbh200_work is called from some interrupts, timers, and so on.
4992 * it calls driver completion functions, after dropping fusbh200->lock.
4993 */
4995 {
4996 /* another CPU may drop fusbh200->lock during a schedule scan while
4997 * it reports urb completions. this flag guards against bogus
4998 * attempts at re-entrant schedule scanning.
4999 */
5003 }
5006 rescan:
5018 /* the IO watchdog guards against hardware or driver bugs that
5019 * misplace IRQs, and should let us run completely without IRQs.
5020 * such lossage has been observed on both VT6202 and VT8235.
5021 */
5023 }
5025 /*
5026 * Called when the fusbh200_hcd module is removed.
5027 */
5029 {
5034 /* no more interrupts ... */
5048 /* root hub is shut down separately (first, when possible) */
5062 }
5064 /* one-time init, only for memory state */
5066 {
5068 u32 temp;
5070 u32 hcc_params;
5075 /*
5076 * keep io watchdog by default, those good HCDs could turn off it later
5077 */
5086 /*
5087 * by default set standard 80% (== 100 usec/uframe) max periodic
5088 * bandwidth as required by USB 2.0
5089 */
5092 /*
5093 * hw default: 1K periodic list heads, one per frame.
5094 * periodic_size can shrink by USBCMD update if hcc_params allows.
5095 */
5101 /* periodic schedule size can be smaller than default */
5107 }
5108 }
5112 /* controllers may cache some of the periodic schedule ... */
5115 /*
5116 * dedicate a qh for the async ring head, since we couldn't unlink
5117 * a 'real' qh without stopping the async schedule [4.8]. use it
5118 * as the 'reclamation list head' too.
5119 * its dummy is used in hw_alt_next of many tds, to prevent the qh
5120 * from automatically advancing to the next td after short reads.
5121 */
5131 /* clear interrupt enables, set irq latency */
5136 /* HW default park == 3, on hardware that supports it (like
5137 * NVidia and ALI silicon), maximizes throughput on the async
5138 * schedule by avoiding QH fetches between transfers.
5139 *
5140 * With fast usb storage devices and NForce2, "park" seems to
5141 * make problems: throughput reduction (!), data errors...
5142 */
5147 }
5149 }
5151 /* periodic schedule size can be smaller than default */
5154 }
5157 /* Accept arbitrarily long scatter-gather lists */
5161 }
5163 /* start HC running; it's halted, hcd_fusbh200_init() has been run (once) */
5165 {
5167 u32 temp;
5168 u32 hcc_params;
5172 /* EHCI spec section 4.1 */
5177 /*
5178 * hcc_params controls whether fusbh200->regs->segment must (!!!)
5179 * be used; it constrains QH/ITD/SITD and QTD locations.
5180 * pci_pool consistent memory always uses segment zero.
5181 * streaming mappings for I/O buffers, like pci_map_single(),
5182 * can return segments above 4GB, if the device allows.
5183 *
5184 * NOTE: the dma mask is visible through dma_supported(), so
5185 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
5186 * Scsi_Host.highmem_io, and so forth. It's readonly to all
5187 * host side drivers though.
5188 */
5191 // Philips, Intel, and maybe others need CMD_RUN before the
5192 // root hub will detect new devices (why?); NEC doesn't
5198 /*
5199 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
5200 * are explicitly handed to companion controller(s), so no TT is
5201 * involved with the root hub. (Except where one is integrated,
5202 * and there's no companion controller unless maybe for USB OTG.)
5203 *
5204 * Turning on the CF flag will transfer ownership of all ports
5205 * from the companions to the EHCI controller. If any of the
5206 * companions are in the middle of a port reset at the time, it
5207 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
5208 * guarantees that no resets are in progress. After we set CF,
5209 * a short delay lets the hardware catch up; new resets shouldn't
5210 * be started before the port switching actions could complete.
5211 */
5228 /* GRR this is run-once init(), being done every time the HC starts.
5229 * So long as they're part of class devices, we can't do it init()
5230 * since the class device isn't created that early.
5231 */
5236 }
5239 {
5248 /* cache this readonly data; minimize chip reads */
5253 /* data structure init */
5265 }
5267 /*-------------------------------------------------------------------------*/
5270 {
5279 /* e.g. cardbus physical eject */
5283 }
5285 /*
5286 * We don't use STS_FLR, but some controllers don't like it to
5287 * remain on, so mask it out along with the other status bits.
5288 */
5291 /* Shared IRQ? */
5295 }
5297 /* clear (just) interrupts */
5302 /* normal [4.15.1.2] or error [4.15.1.1] completion */
5306 else
5309 }
5311 /* complete the unlinking of some qh [4.15.2.3] */
5314 /* Turn off the IAA watchdog */
5317 /*
5318 * Mild optimization: Allow another IAAD to reset the
5319 * hrtimer, if one occurs before the next expiration.
5320 * In theory we could always cancel the hrtimer, but
5321 * tests show that about half the time it will be reset
5322 * for some other event anyway.
5323 */
5327 /* guard against (alleged) silicon errata */
5335 }
5337 /* remote wakeup [4.3.1] */
5342 /* kick root hub later */
5345 /* resume root hub? */
5357 /* start 20 msec resume signaling from this port,
5358 * and make khubd collect PORT_STAT_C_SUSPEND to
5359 * stop that signaling. Use 5 ms extra for safety,
5360 * like usb_port_resume() does.
5361 */
5366 }
5367 }
5369 /* PCI errors [4.15.2.4] */
5374 dead:
5377 /* Don't let the controller do anything more */
5385 /* Handle completions when the controller stops */
5387 }
5395 }
5397 /*-------------------------------------------------------------------------*/
5399 /*
5400 * non-error returns are a promise to giveback() the urb later
5401 * we drop ownership so next owner (or urb unlink) can get it
5402 *
5403 * urb + dev is in hcd.self.controller.urb_list
5404 * we're queueing TDs onto software and hardware lists
5405 *
5406 * hcd-specific init for hcpriv hasn't been done yet
5407 *
5408 * NOTE: control, bulk, and interrupt share the same code to append TDs
5409 * to a (possibly active) QH, and the same QH scanning code.
5410 */
5414 gfp_t mem_flags
5415 ) {
5423 /* qh_completions() code doesn't handle all the fault cases
5424 * in multi-TD control transfers. Even 1KB is rare anyway.
5425 */
5428 /* FALLTHROUGH */
5429 /* case PIPE_BULK: */
5442 }
5443 }
5445 /* remove from hardware lists
5446 * completions normally happen asynchronously
5447 */
5450 {
5462 // case PIPE_CONTROL:
5463 // case PIPE_BULK:
5475 /* already started */
5478 /* QH might be waiting for a Clear-TT-Buffer */
5481 }
5500 }
5504 // itd...
5506 // wait till next completion, do it then.
5507 // completion irqs can wait up to 1024 msec,
5509 }
5510 done:
5513 }
5515 /*-------------------------------------------------------------------------*/
5517 // bulk qh holds the data toggle
5519 static void
5521 {
5526 /* ASSERT: any requests/urbs are being unlinked */
5527 /* ASSERT: nobody can be submitting urbs for this any more */
5529 rescan:
5535 /* endpoints can be iso streams. for now, we don't
5536 * accelerate iso completions ... so spin a while.
5537 */
5544 /* BUG_ON(!list_empty(&stream->free_list)); */
5547 }
5558 /* periodic qh self-unlinks on empty, and a COMPLETING qh
5559 * may already be unlinked.
5560 */
5563 /* FALL THROUGH */
5566 idle_timeout:
5576 }
5577 /* else FALL THROUGH */
5579 /* caller was supposed to have unlinked any requests;
5580 * that's not our job. just leak this memory.
5581 */
5586 }
5587 done:
5590 }
5592 static void
5594 {
5608 /* For Bulk and Interrupt endpoints we maintain the toggle state
5609 * in the hardware; the toggle bits in udev aren't used at all.
5610 * When an endpoint is reset by usb_clear_halt() we must reset
5611 * the toggle bit in the QH.
5612 */
5620 /* The toggle value in the QH can't be updated
5621 * while the QH is active. Unlink it now;
5622 * re-linking will call qh_refresh().
5623 */
5626 else
5628 }
5629 }
5631 }
5634 {
5637 }
5639 /*-------------------------------------------------------------------------*/
5641 /*
5642 * The EHCI in ChipIdea HDRC cannot be a separate module or device,
5643 * because its registers (and irq) are shared between host/gadget/otg
5644 * functions and in order to facilitate role switching we cannot
5645 * give the fusbh200 driver exclusive access to those.
5646 */
5656 /*
5657 * generic hardware linkage
5658 */
5662 /*
5663 * basic lifecycle operations
5664 */
5670 /*
5671 * managing i/o requests and associated device resources
5672 */
5678 /*
5679 * scheduling support
5680 */
5683 /*
5684 * root hub support
5685 */
5695 };
5698 {
5699 u32 reg;
5709 }
5711 /**
5712 * fusbh200_hcd_probe - initialize faraday FUSBH200 HCDs
5713 *
5714 * Allocates basic resources for this USB host controller, and
5715 * then invokes the start() method for the HCD associated with it
5716 * through the hotplug entry's driver_data.
5717 */
5719 {
5738 }
5748 }
5757 }
5768 }
5777 }
5784 }
5800 }
5805 fail_add_hcd:
5807 fail_ioremap:
5809 fail_request_resource:
5811 fail_create_hcd:
5814 }
5816 /**
5817 * fusbh200_hcd_remove - shutdown processing for EHCI HCDs
5818 * @dev: USB Host Controller being removed
5819 *
5820 * Reverses the effect of fotg2xx_usb_hcd_probe(), first invoking
5821 * the HCD's stop() method. It is always called from a thread
5822 * context, normally "rmmod", "apmd", or something similar.
5823 */
5825 {
5838 }
5843 },
5846 };
5849 {
5863 hcd_name,
5871 }
5879 clean:
5882 err_debug:
5885 }
5889 {
5893 }