drivers/pci/dwc/pcie-designware.c

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/of.h>
  16 #include <linux/types.h>
  17
  18 #include "pcie-designware.h"
  19
  20 /* PCIe Port Logic registers */
  21 #define PLR_OFFSET                      0x700
  22 #define PCIE_PHY_DEBUG_R1               (PLR_OFFSET + 0x2c)
  23 #define PCIE_PHY_DEBUG_R1_LINK_UP       (0x1 << 4)
  24 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING      (0x1 << 29)
  25
  26 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
  27 {
  28         if ((uintptr_t)addr & (size - 1)) {
  29                 *val = 0;
  30                 return PCIBIOS_BAD_REGISTER_NUMBER;
  31         }
  32
  33         if (size == 4) {
  34                 *val = readl(addr);
  35         } else if (size == 2) {
  36                 *val = readw(addr);
  37         } else if (size == 1) {
  38                 *val = readb(addr);
  39         } else {
  40                 *val = 0;
  41                 return PCIBIOS_BAD_REGISTER_NUMBER;
  42         }
  43
  44         return PCIBIOS_SUCCESSFUL;
  45 }
  46
  47 int dw_pcie_write(void __iomem *addr, int size, u32 val)
  48 {
  49         if ((uintptr_t)addr & (size - 1))
  50                 return PCIBIOS_BAD_REGISTER_NUMBER;
  51
  52         if (size == 4)
  53                 writel(val, addr);
  54         else if (size == 2)
  55                 writew(val, addr);
  56         else if (size == 1)
  57                 writeb(val, addr);
  58         else
  59                 return PCIBIOS_BAD_REGISTER_NUMBER;
  60
  61         return PCIBIOS_SUCCESSFUL;
  62 }
  63
  64 u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
  65 {
  66         if (pci->ops->readl_dbi)
  67                 return pci->ops->readl_dbi(pci, reg);
  68
  69         return readl(pci->dbi_base + reg);
  70 }
  71
  72 void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
  73 {
  74         if (pci->ops->writel_dbi)
  75                 pci->ops->writel_dbi(pci, reg, val);
  76         else
  77                 writel(val, pci->dbi_base + reg);
  78 }
  79
  80 static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
  81 {
  82         u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  83
  84         return dw_pcie_readl_dbi(pci, offset + reg);
  85 }
  86
  87 static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
  88                                   u32 val)
  89 {
  90         u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  91
  92         dw_pcie_writel_dbi(pci, offset + reg, val);
  93 }
  94
  95 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
  96                                u64 cpu_addr, u64 pci_addr, u32 size)
  97 {
  98         u32 retries, val;
  99
 100         if (pci->iatu_unroll_enabled) {
 101                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
 102                                       lower_32_bits(cpu_addr));
 103                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
 104                                       upper_32_bits(cpu_addr));
 105                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
 106                                       lower_32_bits(cpu_addr + size - 1));
 107                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
 108                                       lower_32_bits(pci_addr));
 109                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
 110                                       upper_32_bits(pci_addr));
 111                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
 112                                       type);
 113                 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
 114                                       PCIE_ATU_ENABLE);
 115         } else {
 116                 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
 117                                    PCIE_ATU_REGION_OUTBOUND | index);
 118                 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
 119                                    lower_32_bits(cpu_addr));
 120                 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
 121                                    upper_32_bits(cpu_addr));
 122                 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
 123                                    lower_32_bits(cpu_addr + size - 1));
 124                 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
 125                                    lower_32_bits(pci_addr));
 126                 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
 127                                    upper_32_bits(pci_addr));
 128                 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
 129                 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
 130         }
 131
 132         /*
 133          * Make sure ATU enable takes effect before any subsequent config
 134          * and I/O accesses.
 135          */
 136         for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
 137                 if (pci->iatu_unroll_enabled)
 138                         val = dw_pcie_readl_unroll(pci, index,
 139                                                    PCIE_ATU_UNR_REGION_CTRL2);
 140                 else
 141                         val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
 142
 143                 if (val == PCIE_ATU_ENABLE)
 144                         return;
 145
 146                 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
 147         }
 148         dev_err(pci->dev, "iATU is not being enabled\n");
 149 }
 150
 151 int dw_pcie_wait_for_link(struct dw_pcie *pci)
 152 {
 153         int retries;
 154
 155         /* check if the link is up or not */
 156         for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
 157                 if (dw_pcie_link_up(pci)) {
 158                         dev_info(pci->dev, "link up\n");
 159                         return 0;
 160                 }
 161                 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
 162         }
 163
 164         dev_err(pci->dev, "phy link never came up\n");
 165
 166         return -ETIMEDOUT;
 167 }
 168
 169 int dw_pcie_link_up(struct dw_pcie *pci)
 170 {
 171         u32 val;
 172
 173         if (pci->ops->link_up)
 174                 return pci->ops->link_up(pci);
 175
 176         val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
 177         return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
 178                 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
 179 }
 180
 181 void dw_pcie_setup(struct dw_pcie *pci)
 182 {
 183         int ret;
 184         u32 val;
 185         u32 lanes;
 186         struct device *dev = pci->dev;
 187         struct device_node *np = dev->of_node;
 188
 189         ret = of_property_read_u32(np, "num-lanes", &lanes);
 190         if (ret)
 191                 lanes = 0;
 192
 193         /* set the number of lanes */
 194         val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
 195         val &= ~PORT_LINK_MODE_MASK;
 196         switch (lanes) {
 197         case 1:
 198                 val |= PORT_LINK_MODE_1_LANES;
 199                 break;
 200         case 2:
 201                 val |= PORT_LINK_MODE_2_LANES;
 202                 break;
 203         case 4:
 204                 val |= PORT_LINK_MODE_4_LANES;
 205                 break;
 206         case 8:
 207                 val |= PORT_LINK_MODE_8_LANES;
 208                 break;
 209         default:
 210                 dev_err(pci->dev, "num-lanes %u: invalid value\n", lanes);
 211                 return;
 212         }
 213         dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
 214
 215         /* set link width speed control register */
 216         val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 217         val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
 218         switch (lanes) {
 219         case 1:
 220                 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
 221                 break;
 222         case 2:
 223                 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
 224                 break;
 225         case 4:
 226                 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
 227                 break;
 228         case 8:
 229                 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
 230                 break;
 231         }
 232         dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
 233 }