drivers/scsi/qla2xxx/qla_dbg.h

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2014 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7
   8 #include "qla_def.h"
   9
  10 /*
  11  * Firmware Dump structure definition
  12  */
  13
  14 struct qla2300_fw_dump {
  15         uint16_t hccr;
  16         uint16_t pbiu_reg[8];
  17         uint16_t risc_host_reg[8];
  18         uint16_t mailbox_reg[32];
  19         uint16_t resp_dma_reg[32];
  20         uint16_t dma_reg[48];
  21         uint16_t risc_hdw_reg[16];
  22         uint16_t risc_gp0_reg[16];
  23         uint16_t risc_gp1_reg[16];
  24         uint16_t risc_gp2_reg[16];
  25         uint16_t risc_gp3_reg[16];
  26         uint16_t risc_gp4_reg[16];
  27         uint16_t risc_gp5_reg[16];
  28         uint16_t risc_gp6_reg[16];
  29         uint16_t risc_gp7_reg[16];
  30         uint16_t frame_buf_hdw_reg[64];
  31         uint16_t fpm_b0_reg[64];
  32         uint16_t fpm_b1_reg[64];
  33         uint16_t risc_ram[0xf800];
  34         uint16_t stack_ram[0x1000];
  35         uint16_t data_ram[1];
  36 };
  37
  38 struct qla2100_fw_dump {
  39         uint16_t hccr;
  40         uint16_t pbiu_reg[8];
  41         uint16_t mailbox_reg[32];
  42         uint16_t dma_reg[48];
  43         uint16_t risc_hdw_reg[16];
  44         uint16_t risc_gp0_reg[16];
  45         uint16_t risc_gp1_reg[16];
  46         uint16_t risc_gp2_reg[16];
  47         uint16_t risc_gp3_reg[16];
  48         uint16_t risc_gp4_reg[16];
  49         uint16_t risc_gp5_reg[16];
  50         uint16_t risc_gp6_reg[16];
  51         uint16_t risc_gp7_reg[16];
  52         uint16_t frame_buf_hdw_reg[16];
  53         uint16_t fpm_b0_reg[64];
  54         uint16_t fpm_b1_reg[64];
  55         uint16_t risc_ram[0xf000];
  56 };
  57
  58 struct qla24xx_fw_dump {
  59         uint32_t host_status;
  60         uint32_t host_reg[32];
  61         uint32_t shadow_reg[7];
  62         uint16_t mailbox_reg[32];
  63         uint32_t xseq_gp_reg[128];
  64         uint32_t xseq_0_reg[16];
  65         uint32_t xseq_1_reg[16];
  66         uint32_t rseq_gp_reg[128];
  67         uint32_t rseq_0_reg[16];
  68         uint32_t rseq_1_reg[16];
  69         uint32_t rseq_2_reg[16];
  70         uint32_t cmd_dma_reg[16];
  71         uint32_t req0_dma_reg[15];
  72         uint32_t resp0_dma_reg[15];
  73         uint32_t req1_dma_reg[15];
  74         uint32_t xmt0_dma_reg[32];
  75         uint32_t xmt1_dma_reg[32];
  76         uint32_t xmt2_dma_reg[32];
  77         uint32_t xmt3_dma_reg[32];
  78         uint32_t xmt4_dma_reg[32];
  79         uint32_t xmt_data_dma_reg[16];
  80         uint32_t rcvt0_data_dma_reg[32];
  81         uint32_t rcvt1_data_dma_reg[32];
  82         uint32_t risc_gp_reg[128];
  83         uint32_t lmc_reg[112];
  84         uint32_t fpm_hdw_reg[192];
  85         uint32_t fb_hdw_reg[176];
  86         uint32_t code_ram[0x2000];
  87         uint32_t ext_mem[1];
  88 };
  89
  90 struct qla25xx_fw_dump {
  91         uint32_t host_status;
  92         uint32_t host_risc_reg[32];
  93         uint32_t pcie_regs[4];
  94         uint32_t host_reg[32];
  95         uint32_t shadow_reg[11];
  96         uint32_t risc_io_reg;
  97         uint16_t mailbox_reg[32];
  98         uint32_t xseq_gp_reg[128];
  99         uint32_t xseq_0_reg[48];
 100         uint32_t xseq_1_reg[16];
 101         uint32_t rseq_gp_reg[128];
 102         uint32_t rseq_0_reg[32];
 103         uint32_t rseq_1_reg[16];
 104         uint32_t rseq_2_reg[16];
 105         uint32_t aseq_gp_reg[128];
 106         uint32_t aseq_0_reg[32];
 107         uint32_t aseq_1_reg[16];
 108         uint32_t aseq_2_reg[16];
 109         uint32_t cmd_dma_reg[16];
 110         uint32_t req0_dma_reg[15];
 111         uint32_t resp0_dma_reg[15];
 112         uint32_t req1_dma_reg[15];
 113         uint32_t xmt0_dma_reg[32];
 114         uint32_t xmt1_dma_reg[32];
 115         uint32_t xmt2_dma_reg[32];
 116         uint32_t xmt3_dma_reg[32];
 117         uint32_t xmt4_dma_reg[32];
 118         uint32_t xmt_data_dma_reg[16];
 119         uint32_t rcvt0_data_dma_reg[32];
 120         uint32_t rcvt1_data_dma_reg[32];
 121         uint32_t risc_gp_reg[128];
 122         uint32_t lmc_reg[128];
 123         uint32_t fpm_hdw_reg[192];
 124         uint32_t fb_hdw_reg[192];
 125         uint32_t code_ram[0x2000];
 126         uint32_t ext_mem[1];
 127 };
 128
 129 struct qla81xx_fw_dump {
 130         uint32_t host_status;
 131         uint32_t host_risc_reg[32];
 132         uint32_t pcie_regs[4];
 133         uint32_t host_reg[32];
 134         uint32_t shadow_reg[11];
 135         uint32_t risc_io_reg;
 136         uint16_t mailbox_reg[32];
 137         uint32_t xseq_gp_reg[128];
 138         uint32_t xseq_0_reg[48];
 139         uint32_t xseq_1_reg[16];
 140         uint32_t rseq_gp_reg[128];
 141         uint32_t rseq_0_reg[32];
 142         uint32_t rseq_1_reg[16];
 143         uint32_t rseq_2_reg[16];
 144         uint32_t aseq_gp_reg[128];
 145         uint32_t aseq_0_reg[32];
 146         uint32_t aseq_1_reg[16];
 147         uint32_t aseq_2_reg[16];
 148         uint32_t cmd_dma_reg[16];
 149         uint32_t req0_dma_reg[15];
 150         uint32_t resp0_dma_reg[15];
 151         uint32_t req1_dma_reg[15];
 152         uint32_t xmt0_dma_reg[32];
 153         uint32_t xmt1_dma_reg[32];
 154         uint32_t xmt2_dma_reg[32];
 155         uint32_t xmt3_dma_reg[32];
 156         uint32_t xmt4_dma_reg[32];
 157         uint32_t xmt_data_dma_reg[16];
 158         uint32_t rcvt0_data_dma_reg[32];
 159         uint32_t rcvt1_data_dma_reg[32];
 160         uint32_t risc_gp_reg[128];
 161         uint32_t lmc_reg[128];
 162         uint32_t fpm_hdw_reg[224];
 163         uint32_t fb_hdw_reg[208];
 164         uint32_t code_ram[0x2000];
 165         uint32_t ext_mem[1];
 166 };
 167
 168 struct qla83xx_fw_dump {
 169         uint32_t host_status;
 170         uint32_t host_risc_reg[48];
 171         uint32_t pcie_regs[4];
 172         uint32_t host_reg[32];
 173         uint32_t shadow_reg[11];
 174         uint32_t risc_io_reg;
 175         uint16_t mailbox_reg[32];
 176         uint32_t xseq_gp_reg[256];
 177         uint32_t xseq_0_reg[48];
 178         uint32_t xseq_1_reg[16];
 179         uint32_t xseq_2_reg[16];
 180         uint32_t rseq_gp_reg[256];
 181         uint32_t rseq_0_reg[32];
 182         uint32_t rseq_1_reg[16];
 183         uint32_t rseq_2_reg[16];
 184         uint32_t rseq_3_reg[16];
 185         uint32_t aseq_gp_reg[256];
 186         uint32_t aseq_0_reg[32];
 187         uint32_t aseq_1_reg[16];
 188         uint32_t aseq_2_reg[16];
 189         uint32_t aseq_3_reg[16];
 190         uint32_t cmd_dma_reg[64];
 191         uint32_t req0_dma_reg[15];
 192         uint32_t resp0_dma_reg[15];
 193         uint32_t req1_dma_reg[15];
 194         uint32_t xmt0_dma_reg[32];
 195         uint32_t xmt1_dma_reg[32];
 196         uint32_t xmt2_dma_reg[32];
 197         uint32_t xmt3_dma_reg[32];
 198         uint32_t xmt4_dma_reg[32];
 199         uint32_t xmt_data_dma_reg[16];
 200         uint32_t rcvt0_data_dma_reg[32];
 201         uint32_t rcvt1_data_dma_reg[32];
 202         uint32_t risc_gp_reg[128];
 203         uint32_t lmc_reg[128];
 204         uint32_t fpm_hdw_reg[256];
 205         uint32_t rq0_array_reg[256];
 206         uint32_t rq1_array_reg[256];
 207         uint32_t rp0_array_reg[256];
 208         uint32_t rp1_array_reg[256];
 209         uint32_t queue_control_reg[16];
 210         uint32_t fb_hdw_reg[432];
 211         uint32_t at0_array_reg[128];
 212         uint32_t code_ram[0x2400];
 213         uint32_t ext_mem[1];
 214 };
 215
 216 #define EFT_NUM_BUFFERS         4
 217 #define EFT_BYTES_PER_BUFFER    0x4000
 218 #define EFT_SIZE                ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
 219
 220 #define FCE_NUM_BUFFERS         64
 221 #define FCE_BYTES_PER_BUFFER    0x400
 222 #define FCE_SIZE                ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
 223 #define fce_calc_size(b)        ((FCE_BYTES_PER_BUFFER) * (b))
 224
 225 struct qla2xxx_fce_chain {
 226         uint32_t type;
 227         uint32_t chain_size;
 228
 229         uint32_t size;
 230         uint32_t addr_l;
 231         uint32_t addr_h;
 232         uint32_t eregs[8];
 233 };
 234
 235 struct qla2xxx_mq_chain {
 236         uint32_t type;
 237         uint32_t chain_size;
 238
 239         uint32_t count;
 240         uint32_t qregs[4 * QLA_MQ_SIZE];
 241 };
 242
 243 struct qla2xxx_mqueue_header {
 244         uint32_t queue;
 245 #define TYPE_REQUEST_QUEUE      0x1
 246 #define TYPE_RESPONSE_QUEUE     0x2
 247 #define TYPE_ATIO_QUEUE         0x3
 248         uint32_t number;
 249         uint32_t size;
 250 };
 251
 252 struct qla2xxx_mqueue_chain {
 253         uint32_t type;
 254         uint32_t chain_size;
 255 };
 256
 257 #define DUMP_CHAIN_VARIANT      0x80000000
 258 #define DUMP_CHAIN_FCE          0x7FFFFAF0
 259 #define DUMP_CHAIN_MQ           0x7FFFFAF1
 260 #define DUMP_CHAIN_QUEUE        0x7FFFFAF2
 261 #define DUMP_CHAIN_LAST         0x80000000
 262
 263 struct qla2xxx_fw_dump {
 264         uint8_t signature[4];
 265         uint32_t version;
 266
 267         uint32_t fw_major_version;
 268         uint32_t fw_minor_version;
 269         uint32_t fw_subminor_version;
 270         uint32_t fw_attributes;
 271
 272         uint32_t vendor;
 273         uint32_t device;
 274         uint32_t subsystem_vendor;
 275         uint32_t subsystem_device;
 276
 277         uint32_t fixed_size;
 278         uint32_t mem_size;
 279         uint32_t req_q_size;
 280         uint32_t rsp_q_size;
 281
 282         uint32_t eft_size;
 283         uint32_t eft_addr_l;
 284         uint32_t eft_addr_h;
 285
 286         uint32_t header_size;
 287
 288         union {
 289                 struct qla2100_fw_dump isp21;
 290                 struct qla2300_fw_dump isp23;
 291                 struct qla24xx_fw_dump isp24;
 292                 struct qla25xx_fw_dump isp25;
 293                 struct qla81xx_fw_dump isp81;
 294                 struct qla83xx_fw_dump isp83;
 295         } isp;
 296 };
 297
 298 #define QL_MSGHDR "qla2xxx"
 299 #define QL_DBG_DEFAULT1_MASK    0x1e400000
 300
 301 #define ql_log_fatal            0 /* display fatal errors */
 302 #define ql_log_warn             1 /* display critical errors */
 303 #define ql_log_info             2 /* display all recovered errors */
 304 #define ql_log_all              3 /* This value is only used by ql_errlev.
 305                                    * No messages will use this value.
 306                                    * This should be always highest value
 307                                    * as compared to other log levels.
 308                                    */
 309
 310 extern int ql_errlev;
 311
 312 void __attribute__((format (printf, 4, 5)))
 313 ql_dbg(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
 314 void __attribute__((format (printf, 4, 5)))
 315 ql_dbg_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
 316
 317 void __attribute__((format (printf, 4, 5)))
 318 ql_log(uint32_t, scsi_qla_host_t *vha, int32_t, const char *fmt, ...);
 319 void __attribute__((format (printf, 4, 5)))
 320 ql_log_pci(uint32_t, struct pci_dev *pdev, int32_t, const char *fmt, ...);
 321
 322 /* Debug Levels */
 323 /* The 0x40000000 is the max value any debug level can have
 324  * as ql2xextended_error_logging is of type signed int
 325  */
 326 #define ql_dbg_init     0x40000000 /* Init Debug */
 327 #define ql_dbg_mbx      0x20000000 /* MBX Debug */
 328 #define ql_dbg_disc     0x10000000 /* Device Discovery Debug */
 329 #define ql_dbg_io       0x08000000 /* IO Tracing Debug */
 330 #define ql_dbg_dpc      0x04000000 /* DPC Thead Debug */
 331 #define ql_dbg_async    0x02000000 /* Async events Debug */
 332 #define ql_dbg_timer    0x01000000 /* Timer Debug */
 333 #define ql_dbg_user     0x00800000 /* User Space Interations Debug */
 334 #define ql_dbg_taskm    0x00400000 /* Task Management Debug */
 335 #define ql_dbg_aer      0x00200000 /* AER/EEH Debug */
 336 #define ql_dbg_multiq   0x00100000 /* MultiQ Debug */
 337 #define ql_dbg_p3p      0x00080000 /* P3P specific Debug */
 338 #define ql_dbg_vport    0x00040000 /* Virtual Port Debug */
 339 #define ql_dbg_buffer   0x00020000 /* For dumping the buffer/regs */
 340 #define ql_dbg_misc     0x00010000 /* For dumping everything that is not
 341                                     * not covered by upper categories
 342                                     */
 343 #define ql_dbg_verbose  0x00008000 /* More verbosity for each level
 344                                     * This is to be used with other levels where
 345                                     * more verbosity is required. It might not
 346                                     * be applicable to all the levels.
 347                                     */
 348 #define ql_dbg_tgt      0x00004000 /* Target mode */
 349 #define ql_dbg_tgt_mgt  0x00002000 /* Target mode management */
 350 #define ql_dbg_tgt_tmr  0x00001000 /* Target mode task management */
 351
 352 extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
 353         uint32_t, void **);
 354 extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, uint32_t *,
 355         uint32_t, void **);
 356 extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
 357         struct qla_hw_data *);
 358 extern int qla24xx_soft_reset(struct qla_hw_data *);