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ocfs2: fix several issues of append dio
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx.h
blob59c477883a7325ba1810dd833e9c03661156ff58
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
9
10 /*
11 * Following are the states of the Phantom. Phantom will set them and
12 * Host will read to check if the fields are correct.
13 */
14 #define PHAN_INITIALIZE_FAILED 0xffff
15 #define PHAN_INITIALIZE_COMPLETE 0xff01
16
17 /* Host writes the following to notify that it has done the init-handshake */
18 #define PHAN_INITIALIZE_ACK 0xf00f
19 #define PHAN_PEG_RCV_INITIALIZED 0xff01
20
21 /*CRB_RELATED*/
22 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
24
25 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
26 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
27 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
28 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
29 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
30 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555
31
32 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
33 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
34 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
35 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
36 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
37 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
38 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
39
40 /* Hub 0 */
41 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
42 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
43
44 /* Hub 1 */
45 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
46 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
47 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
48 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
49 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
50 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
51 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
52 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
53 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
54 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
55 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
56 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
57 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
58 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
59 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
60
61 /* Hub 2 */
62 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
63 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
64 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
65
66 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
67 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
68 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
69 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
70 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
71 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
72 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
73 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
74 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
75 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
76 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
77 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
78 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
79
80 /* Hub 3 */
81 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
82 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
83 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
84 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
85
86 /* Hub 4 */
87 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
88 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
89 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
90 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
91 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
92 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
93 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
94 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
95 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
96 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
97 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
98 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
99
100 /* Hub 5 */
101 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
102 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
103 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
104 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
105 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
106 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
107 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
108
109 /* Hub 6 */
110 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
111 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
112 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
113 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
114 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
115 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
116 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
117 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
118 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
119
120 /* This field defines PCI/X adr [25:20] of agents on the CRB */
121 /* */
122 #define QLA82XX_HW_PX_MAP_CRB_PH 0
123 #define QLA82XX_HW_PX_MAP_CRB_PS 1
124 #define QLA82XX_HW_PX_MAP_CRB_MN 2
125 #define QLA82XX_HW_PX_MAP_CRB_MS 3
126 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
127 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
128 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
129 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
130 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
131 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
132 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
133 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
134 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
135 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
136 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
137 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
138 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
139 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
140 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
141 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
142 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
143 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
144 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
145 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
146 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
147 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
148 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
149 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
150 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
151 #define QLA82XX_HW_PX_MAP_CRB_SN 29
152 #define QLA82XX_HW_PX_MAP_CRB_EG 31
153 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
154 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
155 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
156 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
157 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
158 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
159 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
160 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
161 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
162 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
163 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
164 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
165 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
166 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
167 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
168 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
169 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
170 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
171 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
172 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
173 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
174 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
175 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
176 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
177 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
178 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
179 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
180 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
181 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
182 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
183 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
184 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
185 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
186 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
187
188 /* This field defines CRB adr [31:20] of the agents */
189 /* */
190
191 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
192 QLA82XX_HW_MN_CRB_AGT_ADR)
193 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
194 QLA82XX_HW_PH_CRB_AGT_ADR)
195 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
196 QLA82XX_HW_MS_CRB_AGT_ADR)
197 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
198 QLA82XX_HW_PS_CRB_AGT_ADR)
199 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
200 QLA82XX_HW_SS_CRB_AGT_ADR)
201 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
202 QLA82XX_HW_RPMX3_CRB_AGT_ADR)
203 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
204 QLA82XX_HW_QMS_CRB_AGT_ADR)
205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
206 QLA82XX_HW_SQGS0_CRB_AGT_ADR)
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
208 QLA82XX_HW_SQGS1_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
210 QLA82XX_HW_SQGS2_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
212 QLA82XX_HW_SQGS3_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214 QLA82XX_HW_C2C0_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216 QLA82XX_HW_C2C1_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218 QLA82XX_HW_RPMX2_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220 QLA82XX_HW_RPMX4_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222 QLA82XX_HW_RPMX7_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224 QLA82XX_HW_RPMX9_CRB_AGT_ADR)
225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
226 QLA82XX_HW_SMB_CRB_AGT_ADR)
227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
228 QLA82XX_HW_NIU_CRB_AGT_ADR)
229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
230 QLA82XX_HW_I2C0_CRB_AGT_ADR)
231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
232 QLA82XX_HW_I2C1_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
234 QLA82XX_HW_SRE_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
236 QLA82XX_HW_EG_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
238 QLA82XX_HW_RPMX0_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
240 QLA82XX_HW_QM_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
242 QLA82XX_HW_SQG0_CRB_AGT_ADR)
243 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
244 QLA82XX_HW_SQG1_CRB_AGT_ADR)
245 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
246 QLA82XX_HW_SQG2_CRB_AGT_ADR)
247 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
248 QLA82XX_HW_SQG3_CRB_AGT_ADR)
249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
250 QLA82XX_HW_RPMX1_CRB_AGT_ADR)
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252 QLA82XX_HW_RPMX5_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254 QLA82XX_HW_RPMX6_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256 QLA82XX_HW_RPMX8_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258 QLA82XX_HW_CAS0_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260 QLA82XX_HW_CAS1_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262 QLA82XX_HW_CAS2_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
264 QLA82XX_HW_CAS3_CRB_AGT_ADR)
265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
266 QLA82XX_HW_PEGNI_CRB_AGT_ADR)
267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
268 QLA82XX_HW_PEGND_CRB_AGT_ADR)
269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
270 QLA82XX_HW_PEGN0_CRB_AGT_ADR)
271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
272 QLA82XX_HW_PEGN1_CRB_AGT_ADR)
273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
274 QLA82XX_HW_PEGN2_CRB_AGT_ADR)
275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
276 QLA82XX_HW_PEGN3_CRB_AGT_ADR)
277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
278 QLA82XX_HW_PEGN4_CRB_AGT_ADR)
279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
280 QLA82XX_HW_PEGNC_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
282 QLA82XX_HW_PEGR0_CRB_AGT_ADR)
283 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
284 QLA82XX_HW_PEGR1_CRB_AGT_ADR)
285 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
286 QLA82XX_HW_PEGR2_CRB_AGT_ADR)
287 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
288 QLA82XX_HW_PEGR3_CRB_AGT_ADR)
289 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
290 QLA82XX_HW_PEGSI_CRB_AGT_ADR)
291 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
292 QLA82XX_HW_PEGSD_CRB_AGT_ADR)
293 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
294 QLA82XX_HW_PEGS0_CRB_AGT_ADR)
295 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
296 QLA82XX_HW_PEGS1_CRB_AGT_ADR)
297 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
298 QLA82XX_HW_PEGS2_CRB_AGT_ADR)
299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
300 QLA82XX_HW_PEGS3_CRB_AGT_ADR)
301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
302 QLA82XX_HW_PEGSC_CRB_AGT_ADR)
303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
304 QLA82XX_HW_NCM_CRB_AGT_ADR)
305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
306 QLA82XX_HW_TMR_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
308 QLA82XX_HW_XDMA_CRB_AGT_ADR)
309 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
310 QLA82XX_HW_SN_CRB_AGT_ADR)
311 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
312 QLA82XX_HW_I2Q_CRB_AGT_ADR)
313 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
314 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
315 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
316 QLA82XX_HW_OCM0_CRB_AGT_ADR)
317 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
318 QLA82XX_HW_OCM1_CRB_AGT_ADR)
319 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
320 QLA82XX_HW_LPC_CRB_AGT_ADR)
321
322 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
323 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
324 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
325 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
326 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
327 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
328 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
329 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
330 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
331
332 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
333 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
334 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
335
336 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
337 #define QLA82XX_PCI_CRB_WINDOW(A) \
338 (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
339 #define QLA82XX_CRB_C2C_0 \
340 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
341 #define QLA82XX_CRB_C2C_1 \
342 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
343 #define QLA82XX_CRB_C2C_2 \
344 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
345 #define QLA82XX_CRB_CAM \
346 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
347 #define QLA82XX_CRB_CASPER \
348 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
349 #define QLA82XX_CRB_CASPER_0 \
350 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
351 #define QLA82XX_CRB_CASPER_1 \
352 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
353 #define QLA82XX_CRB_CASPER_2 \
354 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
355 #define QLA82XX_CRB_DDR_MD \
356 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
357 #define QLA82XX_CRB_DDR_NET \
358 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
359 #define QLA82XX_CRB_EPG \
360 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
361 #define QLA82XX_CRB_I2Q \
362 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
363 #define QLA82XX_CRB_NIU \
364 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
365
366 #define QLA82XX_CRB_PCIX_HOST \
367 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
368 #define QLA82XX_CRB_PCIX_HOST2 \
369 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
370 #define QLA82XX_CRB_PCIX_MD \
371 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
372 #define QLA82XX_CRB_PCIE \
373 QLA82XX_CRB_PCIX_MD
374
375 /* window 1 pcie slot */
376 #define QLA82XX_CRB_PCIE2 \
377 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
378 #define QLA82XX_CRB_PEG_MD_0 \
379 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
380 #define QLA82XX_CRB_PEG_MD_1 \
381 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
382 #define QLA82XX_CRB_PEG_MD_2 \
383 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
384 #define QLA82XX_CRB_PEG_MD_3 \
385 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
386 #define QLA82XX_CRB_PEG_MD_3 \
387 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
388 #define QLA82XX_CRB_PEG_MD_D \
389 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
390 #define QLA82XX_CRB_PEG_MD_I \
391 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
392 #define QLA82XX_CRB_PEG_NET_0 \
393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
394 #define QLA82XX_CRB_PEG_NET_1 \
395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
396 #define QLA82XX_CRB_PEG_NET_2 \
397 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
398 #define QLA82XX_CRB_PEG_NET_3 \
399 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
400 #define QLA82XX_CRB_PEG_NET_4 \
401 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
402 #define QLA82XX_CRB_PEG_NET_D \
403 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
404 #define QLA82XX_CRB_PEG_NET_I \
405 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
406 #define QLA82XX_CRB_PQM_MD \
407 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
408 #define QLA82XX_CRB_PQM_NET \
409 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
410 #define QLA82XX_CRB_QDR_MD \
411 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
412 #define QLA82XX_CRB_QDR_NET \
413 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
414 #define QLA82XX_CRB_ROMUSB \
415 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
416 #define QLA82XX_CRB_RPMX_0 \
417 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
418 #define QLA82XX_CRB_RPMX_1 \
419 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
420 #define QLA82XX_CRB_RPMX_2 \
421 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
422 #define QLA82XX_CRB_RPMX_3 \
423 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
424 #define QLA82XX_CRB_RPMX_4 \
425 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
426 #define QLA82XX_CRB_RPMX_5 \
427 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
428 #define QLA82XX_CRB_RPMX_6 \
429 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
430 #define QLA82XX_CRB_RPMX_7 \
431 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
432 #define QLA82XX_CRB_SQM_MD_0 \
433 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
434 #define QLA82XX_CRB_SQM_MD_1 \
435 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
436 #define QLA82XX_CRB_SQM_MD_2 \
437 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
438 #define QLA82XX_CRB_SQM_MD_3 \
439 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
440 #define QLA82XX_CRB_SQM_NET_0 \
441 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
442 #define QLA82XX_CRB_SQM_NET_1 \
443 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
444 #define QLA82XX_CRB_SQM_NET_2 \
445 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
446 #define QLA82XX_CRB_SQM_NET_3 \
447 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
448 #define QLA82XX_CRB_SRE \
449 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
450 #define QLA82XX_CRB_TIMER \
451 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
452 #define QLA82XX_CRB_XDMA \
453 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
454 #define QLA82XX_CRB_I2C0 \
455 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
456 #define QLA82XX_CRB_I2C1 \
457 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
458 #define QLA82XX_CRB_OCM0 \
459 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
460 #define QLA82XX_CRB_SMB \
461 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
462 #define QLA82XX_CRB_MAX \
463 QLA82XX_PCI_CRB_WINDOW(64)
464
465 /*
466 * ====================== BASE ADDRESSES ON-CHIP ======================
467 * Base addresses of major components on-chip.
468 * ====================== BASE ADDRESSES ON-CHIP ======================
469 */
470 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
471 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
472
473 /* Imbus address bit used to indicate a host address. This bit is
474 * eliminated by the pcie bar and bar select before presentation
475 * over pcie. */
476 /* host memory via IMBUS */
477 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
478 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
479 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
480 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
481 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
482 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
483 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
484 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
485 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
486
487 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
488 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
489 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
490 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
491 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
492 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
493 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
494
495 /*
496 * Register offsets for MN
497 */
498 #define MIU_CONTROL (0x000)
499 #define MIU_TAG (0x004)
500 #define MIU_TEST_AGT_CTRL (0x090)
501 #define MIU_TEST_AGT_ADDR_LO (0x094)
502 #define MIU_TEST_AGT_ADDR_HI (0x098)
503 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
504 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
505 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
506 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
507 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
508 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
509 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
510 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
511
512 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
513 #define MIU_TA_CTL_START 1
514 #define MIU_TA_CTL_ENABLE 2
515 #define MIU_TA_CTL_WRITE 4
516 #define MIU_TA_CTL_BUSY 8
517
518 /*CAM RAM */
519 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
520 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
521
522 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
523 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
524 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
525 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
526
527 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
528 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
529
530 #define HALT_STATUS_UNRECOVERABLE 0x80000000
531 #define HALT_STATUS_RECOVERABLE 0x40000000
532
533 /* Driver Coexistence Defines */
534 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
535 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
536 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
537 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
538 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
539 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
540
541 /* Every driver should use these Device State */
542 #define QLA8XXX_DEV_COLD 1
543 #define QLA8XXX_DEV_INITIALIZING 2
544 #define QLA8XXX_DEV_READY 3
545 #define QLA8XXX_DEV_NEED_RESET 4
546 #define QLA8XXX_DEV_NEED_QUIESCENT 5
547 #define QLA8XXX_DEV_FAILED 6
548 #define QLA8XXX_DEV_QUIESCENT 7
549 #define MAX_STATES 8 /* Increment if new state added */
550 #define QLA8XXX_BAD_VALUE 0xbad0bad0
551
552 #define QLA82XX_IDC_VERSION 1
553 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30
554 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10
555
556 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
557 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
558 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
559 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
560 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
561 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
562
563 #define PCIE_SETUP_FUNCTION (0x12040)
564 #define PCIE_SETUP_FUNCTION2 (0x12048)
565
566 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
567 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
568
569 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
570 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
571 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
572 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
573 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
574 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
575
576 /* Different drive state */
577 #define QLA82XX_DRVST_NOT_RDY 0
578 #define QLA82XX_DRVST_RST_RDY 1
579 #define QLA82XX_DRVST_QSNT_RDY 2
580
581 /* Different drive active state */
582 #define QLA82XX_DRV_NOT_ACTIVE 0
583 #define QLA82XX_DRV_ACTIVE 1
584
585 /*
586 * The PCI VendorID and DeviceID for our board.
587 */
588 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
589 #define PCI_DEVICE_ID_QLOGIC_ISP8044 0x8044
590
591 #define QLA82XX_MSIX_TBL_SPACE 8192
592 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
593 #define QLA82XX_PCI_MSIX_CONTROL 0x40
594
595 struct crb_128M_2M_sub_block_map {
596 unsigned valid;
597 unsigned start_128M;
598 unsigned end_128M;
599 unsigned start_2M;
600 };
601
602 struct crb_128M_2M_block_map {
603 struct crb_128M_2M_sub_block_map sub_block[16];
604 };
605
606 struct crb_addr_pair {
607 long addr;
608 long data;
609 };
610
611 #define ADDR_ERROR ((unsigned long) 0xffffffff)
612 #define MAX_CTL_CHECK 1000
613
614 /***************************************************************************
615 * PCI related defines.
616 **************************************************************************/
617
618 /*
619 * Interrupt related defines.
620 */
621 #define PCIX_TARGET_STATUS (0x10118)
622 #define PCIX_TARGET_STATUS_F1 (0x10160)
623 #define PCIX_TARGET_STATUS_F2 (0x10164)
624 #define PCIX_TARGET_STATUS_F3 (0x10168)
625 #define PCIX_TARGET_STATUS_F4 (0x10360)
626 #define PCIX_TARGET_STATUS_F5 (0x10364)
627 #define PCIX_TARGET_STATUS_F6 (0x10368)
628 #define PCIX_TARGET_STATUS_F7 (0x1036c)
629
630 #define PCIX_TARGET_MASK (0x10128)
631 #define PCIX_TARGET_MASK_F1 (0x10170)
632 #define PCIX_TARGET_MASK_F2 (0x10174)
633 #define PCIX_TARGET_MASK_F3 (0x10178)
634 #define PCIX_TARGET_MASK_F4 (0x10370)
635 #define PCIX_TARGET_MASK_F5 (0x10374)
636 #define PCIX_TARGET_MASK_F6 (0x10378)
637 #define PCIX_TARGET_MASK_F7 (0x1037c)
638
639 /*
640 * Message Signaled Interrupts
641 */
642 #define PCIX_MSI_F0 (0x13000)
643 #define PCIX_MSI_F1 (0x13004)
644 #define PCIX_MSI_F2 (0x13008)
645 #define PCIX_MSI_F3 (0x1300c)
646 #define PCIX_MSI_F4 (0x13010)
647 #define PCIX_MSI_F5 (0x13014)
648 #define PCIX_MSI_F6 (0x13018)
649 #define PCIX_MSI_F7 (0x1301c)
650 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
651 #define PCIX_INT_VECTOR (0x10100)
652 #define PCIX_INT_MASK (0x10104)
653
654 /*
655 * Interrupt state machine and other bits.
656 */
657 #define PCIE_MISCCFG_RC (0x1206c)
658
659 #define ISR_INT_TARGET_STATUS \
660 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
661 #define ISR_INT_TARGET_STATUS_F1 \
662 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
663 #define ISR_INT_TARGET_STATUS_F2 \
664 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
665 #define ISR_INT_TARGET_STATUS_F3 \
666 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
667 #define ISR_INT_TARGET_STATUS_F4 \
668 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
669 #define ISR_INT_TARGET_STATUS_F5 \
670 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
671 #define ISR_INT_TARGET_STATUS_F6 \
672 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
673 #define ISR_INT_TARGET_STATUS_F7 \
674 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
675
676 #define ISR_INT_TARGET_MASK \
677 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
678 #define ISR_INT_TARGET_MASK_F1 \
679 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
680 #define ISR_INT_TARGET_MASK_F2 \
681 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
682 #define ISR_INT_TARGET_MASK_F3 \
683 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
684 #define ISR_INT_TARGET_MASK_F4 \
685 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
686 #define ISR_INT_TARGET_MASK_F5 \
687 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
688 #define ISR_INT_TARGET_MASK_F6 \
689 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
690 #define ISR_INT_TARGET_MASK_F7 \
691 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
692
693 #define ISR_INT_VECTOR \
694 (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
695 #define ISR_INT_MASK \
696 (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
697 #define ISR_INT_STATE_REG \
698 (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
699
700 #define ISR_MSI_INT_TRIGGER(FUNC) \
701 (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
702
703 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
704 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
705
706 /*
707 * PCI Interrupt Vector Values.
708 */
709 #define PCIX_INT_VECTOR_BIT_F0 0x0080
710 #define PCIX_INT_VECTOR_BIT_F1 0x0100
711 #define PCIX_INT_VECTOR_BIT_F2 0x0200
712 #define PCIX_INT_VECTOR_BIT_F3 0x0400
713 #define PCIX_INT_VECTOR_BIT_F4 0x0800
714 #define PCIX_INT_VECTOR_BIT_F5 0x1000
715 #define PCIX_INT_VECTOR_BIT_F6 0x2000
716 #define PCIX_INT_VECTOR_BIT_F7 0x4000
717
718 struct qla82xx_legacy_intr_set {
719 uint32_t int_vec_bit;
720 uint32_t tgt_status_reg;
721 uint32_t tgt_mask_reg;
722 uint32_t pci_int_reg;
723 };
724
725 #define QLA82XX_LEGACY_INTR_CONFIG \
726 { \
727 { \
728 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
729 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
730 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
731 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
732 \
733 { \
734 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
735 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
736 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
737 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
738 \
739 { \
740 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
741 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
742 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
743 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
744 \
745 { \
746 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
747 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
748 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
749 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
750 \
751 { \
752 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
753 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
754 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
755 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
756 \
757 { \
758 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
759 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
760 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
761 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
762 \
763 { \
764 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
765 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
766 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
767 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
768 \
769 { \
770 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
771 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
772 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
773 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
774 }
775
776 #define BRDCFG_START 0x4000
777 #define BOOTLD_START 0x10000
778 #define IMAGE_START 0x100000
779 #define FLASH_ADDR_START 0x43000
780
781 /* Magic number to let user know flash is programmed */
782 #define QLA82XX_BDINFO_MAGIC 0x12345678
783 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
784 #define FW_SIZE_OFFSET (0x3e840c)
785 #define QLA82XX_FW_MIN_SIZE 0x3fffff
786
787 /* UNIFIED ROMIMAGE START */
788 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
789 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
790 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
791 #define QLA82XX_URI_DIR_SECT_FW 0x7
792
793 /* Offsets */
794 #define QLA82XX_URI_CHIP_REV_OFF 10
795 #define QLA82XX_URI_FLAGS_OFF 11
796 #define QLA82XX_URI_BIOS_VERSION_OFF 12
797 #define QLA82XX_URI_BOOTLD_IDX_OFF 27
798 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
799
800 struct qla82xx_uri_table_desc{
801 uint32_t findex;
802 uint32_t num_entries;
803 uint32_t entry_size;
804 uint32_t reserved[5];
805 };
806
807 struct qla82xx_uri_data_desc{
808 uint32_t findex;
809 uint32_t size;
810 uint32_t reserved[5];
811 };
812
813 /* UNIFIED ROMIMAGE END */
814
815 #define QLA82XX_UNIFIED_ROMIMAGE 3
816 #define QLA82XX_FLASH_ROMIMAGE 4
817 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
818
819 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
820 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
821
822 #ifndef readq
823 static inline u64 readq(void __iomem *addr)
824 {
825 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
826 }
827 #endif
828
829 #ifndef writeq
830 static inline void writeq(u64 val, void __iomem *addr)
831 {
832 writel(((u32) (val)), (addr));
833 writel(((u32) (val >> 32)), (addr + 4));
834 }
835 #endif
836
837 /* Request and response queue size */
838 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */
839 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/
840
841 /*
842 * ISP 8021 I/O Register Set structure definitions.
843 */
844 struct device_reg_82xx {
845 uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
846 uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
847 uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
848
849 uint16_t mailbox_in[32]; /* Mail box In registers */
850 uint16_t unused_1[32];
851 uint32_t hint; /* Host interrupt register */
852 #define HINT_MBX_INT_PENDING BIT_0
853 uint16_t unused_2[62];
854 uint16_t mailbox_out[32]; /* Mail box Out registers */
855 uint32_t unused_3[48];
856
857 uint32_t host_status; /* host status */
858 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
859 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
860 uint32_t host_int; /* Interrupt status. */
861 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
862 };
863
864 struct fcp_cmnd {
865 struct scsi_lun lun;
866 uint8_t crn;
867 uint8_t task_attribute;
868 uint8_t task_management;
869 uint8_t additional_cdb_len;
870 uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */
871 };
872
873 struct dsd_dma {
874 struct list_head list;
875 dma_addr_t dsd_list_dma;
876 void *dsd_addr;
877 };
878
879 #define QLA_DSDS_PER_IOCB 37
880 #define QLA_DSD_SIZE 12
881 struct ct6_dsd {
882 uint16_t fcp_cmnd_len;
883 dma_addr_t fcp_cmnd_dma;
884 struct fcp_cmnd *fcp_cmnd;
885 int dsd_use_cnt;
886 struct list_head dsd_list;
887 };
888
889 #define MBC_TOGGLE_INTERRUPT 0x10
890 #define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */
891 #define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */
892
893 /* Flash offset */
894 #define FLT_REG_BOOTLOAD_82XX 0x72
895 #define FLT_REG_BOOT_CODE_82XX 0x78
896 #define FLT_REG_FW_82XX 0x74
897 #define FLT_REG_GOLD_FW_82XX 0x75
898 #define FLT_REG_VPD_8XXX 0x81
899
900 #define FA_VPD_SIZE_82XX 0x400
901
902 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
903
904 /******************************************************************************
905 *
906 * Definitions specific to M25P flash
907 *
908 *******************************************************************************
909 * Instructions
910 */
911 #define M25P_INSTR_WREN 0x06
912 #define M25P_INSTR_WRDI 0x04
913 #define M25P_INSTR_RDID 0x9f
914 #define M25P_INSTR_RDSR 0x05
915 #define M25P_INSTR_WRSR 0x01
916 #define M25P_INSTR_READ 0x03
917 #define M25P_INSTR_FAST_READ 0x0b
918 #define M25P_INSTR_PP 0x02
919 #define M25P_INSTR_SE 0xd8
920 #define M25P_INSTR_BE 0xc7
921 #define M25P_INSTR_DP 0xb9
922 #define M25P_INSTR_RES 0xab
923
924 /* Minidump related */
925
926 /*
927 * Version of the template
928 * 4 Bytes
929 * X.Major.Minor.RELEASE
930 */
931 #define QLA82XX_MINIDUMP_VERSION 0x10101
932
933 /*
934 * Entry Type Defines
935 */
936 #define QLA82XX_RDNOP 0
937 #define QLA82XX_RDCRB 1
938 #define QLA82XX_RDMUX 2
939 #define QLA82XX_QUEUE 3
940 #define QLA82XX_BOARD 4
941 #define QLA82XX_RDSRE 5
942 #define QLA82XX_RDOCM 6
943 #define QLA82XX_CACHE 10
944 #define QLA82XX_L1DAT 11
945 #define QLA82XX_L1INS 12
946 #define QLA82XX_L2DTG 21
947 #define QLA82XX_L2ITG 22
948 #define QLA82XX_L2DAT 23
949 #define QLA82XX_L2INS 24
950 #define QLA82XX_RDROM 71
951 #define QLA82XX_RDMEM 72
952 #define QLA82XX_CNTRL 98
953 #define QLA82XX_TLHDR 99
954 #define QLA82XX_RDEND 255
955 #define QLA8044_POLLRD 35
956 #define QLA8044_RDMUX2 36
957 #define QLA8044_L1DTG 8
958 #define QLA8044_L1ITG 9
959 #define QLA8044_POLLRDMWR 37
960
961 /*
962 * Opcodes for Control Entries.
963 * These Flags are bit fields.
964 */
965 #define QLA82XX_DBG_OPCODE_WR 0x01
966 #define QLA82XX_DBG_OPCODE_RW 0x02
967 #define QLA82XX_DBG_OPCODE_AND 0x04
968 #define QLA82XX_DBG_OPCODE_OR 0x08
969 #define QLA82XX_DBG_OPCODE_POLL 0x10
970 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20
971 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40
972 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80
973
974 /*
975 * Template Header and Entry Header definitions start here.
976 */
977
978 /*
979 * Template Header
980 * Parts of the template header can be modified by the driver.
981 * These include the saved_state_array, capture_debug_level, driver_timestamp
982 */
983
984 #define QLA82XX_DBG_STATE_ARRAY_LEN 16
985 #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
986 #define QLA82XX_DBG_RSVD_ARRAY_LEN 8
987
988 /*
989 * Driver Flags
990 */
991 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
992 #define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */
993
994 struct qla82xx_md_template_hdr {
995 uint32_t entry_type;
996 uint32_t first_entry_offset;
997 uint32_t size_of_template;
998 uint32_t capture_debug_level;
999
1000 uint32_t num_of_entries;
1001 uint32_t version;
1002 uint32_t driver_timestamp;
1003 uint32_t template_checksum;
1004
1005 uint32_t driver_capture_mask;
1006 uint32_t driver_info[3];
1007
1008 uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN];
1009 uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN];
1010
1011 /* markers_array used to capture some special locations on board */
1012 uint32_t markers_array[QLA82XX_DBG_RSVD_ARRAY_LEN];
1013 uint32_t num_of_free_entries; /* For internal use */
1014 uint32_t free_entry_offset; /* For internal use */
1015 uint32_t total_table_size; /* For internal use */
1016 uint32_t bkup_table_offset; /* For internal use */
1017 } __packed;
1018
1019 /*
1020 * Entry Header: Common to All Entry Types
1021 */
1022
1023 /*
1024 * Driver Code is for driver to write some info about the entry.
1025 * Currently not used.
1026 */
1027 typedef struct qla82xx_md_entry_hdr {
1028 uint32_t entry_type;
1029 uint32_t entry_size;
1030 uint32_t entry_capture_size;
1031 struct {
1032 uint8_t entry_capture_mask;
1033 uint8_t entry_code;
1034 uint8_t driver_code;
1035 uint8_t driver_flags;
1036 } d_ctrl;
1037 } __packed qla82xx_md_entry_hdr_t;
1038
1039 /*
1040 * Read CRB entry header
1041 */
1042 struct qla82xx_md_entry_crb {
1043 qla82xx_md_entry_hdr_t h;
1044 uint32_t addr;
1045 struct {
1046 uint8_t addr_stride;
1047 uint8_t state_index_a;
1048 uint16_t poll_timeout;
1049 } crb_strd;
1050
1051 uint32_t data_size;
1052 uint32_t op_count;
1053
1054 struct {
1055 uint8_t opcode;
1056 uint8_t state_index_v;
1057 uint8_t shl;
1058 uint8_t shr;
1059 } crb_ctrl;
1060
1061 uint32_t value_1;
1062 uint32_t value_2;
1063 uint32_t value_3;
1064 } __packed;
1065
1066 /*
1067 * Cache entry header
1068 */
1069 struct qla82xx_md_entry_cache {
1070 qla82xx_md_entry_hdr_t h;
1071
1072 uint32_t tag_reg_addr;
1073 struct {
1074 uint16_t tag_value_stride;
1075 uint16_t init_tag_value;
1076 } addr_ctrl;
1077
1078 uint32_t data_size;
1079 uint32_t op_count;
1080
1081 uint32_t control_addr;
1082 struct {
1083 uint16_t write_value;
1084 uint8_t poll_mask;
1085 uint8_t poll_wait;
1086 } cache_ctrl;
1087
1088 uint32_t read_addr;
1089 struct {
1090 uint8_t read_addr_stride;
1091 uint8_t read_addr_cnt;
1092 uint16_t rsvd_1;
1093 } read_ctrl;
1094 } __packed;
1095
1096 /*
1097 * Read OCM
1098 */
1099 struct qla82xx_md_entry_rdocm {
1100 qla82xx_md_entry_hdr_t h;
1101
1102 uint32_t rsvd_0;
1103 uint32_t rsvd_1;
1104 uint32_t data_size;
1105 uint32_t op_count;
1106
1107 uint32_t rsvd_2;
1108 uint32_t rsvd_3;
1109 uint32_t read_addr;
1110 uint32_t read_addr_stride;
1111 uint32_t read_addr_cntrl;
1112 } __packed;
1113
1114 /*
1115 * Read Memory
1116 */
1117 struct qla82xx_md_entry_rdmem {
1118 qla82xx_md_entry_hdr_t h;
1119 uint32_t rsvd[6];
1120 uint32_t read_addr;
1121 uint32_t read_data_size;
1122 } __packed;
1123
1124 /*
1125 * Read ROM
1126 */
1127 struct qla82xx_md_entry_rdrom {
1128 qla82xx_md_entry_hdr_t h;
1129 uint32_t rsvd[6];
1130 uint32_t read_addr;
1131 uint32_t read_data_size;
1132 } __packed;
1133
1134 struct qla82xx_md_entry_mux {
1135 qla82xx_md_entry_hdr_t h;
1136
1137 uint32_t select_addr;
1138 uint32_t rsvd_0;
1139 uint32_t data_size;
1140 uint32_t op_count;
1141
1142 uint32_t select_value;
1143 uint32_t select_value_stride;
1144 uint32_t read_addr;
1145 uint32_t rsvd_1;
1146 } __packed;
1147
1148 struct qla82xx_md_entry_queue {
1149 qla82xx_md_entry_hdr_t h;
1150
1151 uint32_t select_addr;
1152 struct {
1153 uint16_t queue_id_stride;
1154 uint16_t rsvd_0;
1155 } q_strd;
1156
1157 uint32_t data_size;
1158 uint32_t op_count;
1159 uint32_t rsvd_1;
1160 uint32_t rsvd_2;
1161
1162 uint32_t read_addr;
1163 struct {
1164 uint8_t read_addr_stride;
1165 uint8_t read_addr_cnt;
1166 uint16_t rsvd_3;
1167 } rd_strd;
1168 } __packed;
1169
1170 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1171 #define RQST_TMPLT_SIZE 0x0
1172 #define RQST_TMPLT 0x1
1173 #define MD_DIRECT_ROM_WINDOW 0x42110030
1174 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1175 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1176 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1177 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1178
1179 static const int MD_MIU_TEST_AGT_RDDATA[] = { 0x410000A8, 0x410000AC,
1180 0x410000B8, 0x410000BC };
1181
1182 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1183 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
1184
1185 #define qla82xx_get_temp_val(x) ((x) >> 16)
1186 #define qla82xx_get_temp_val1(x) ((x) && 0x0000FFFF)
1187 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
1188 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
1189
1190 /*
1191 * Temperature control.
1192 */
1193 enum {
1194 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
1195 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
1196 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
1197 };
1198
1199 #define LEG_INTR_PTR_OFFSET 0x38C0
1200 #define LEG_INTR_TRIG_OFFSET 0x38C4
1201 #define LEG_INTR_MASK_OFFSET 0x38C8
1202 #endif
Linux with added FPC-III support