drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h

   1 /*
   2  * OMAP5xxx bandgap registers, bitfields and temperature definitions
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   5  * Contact:
   6  *   Eduardo Valentin <eduardo.valentin@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23 #ifndef __OMAP5XXX_BANDGAP_H
  24 #define __OMAP5XXX_BANDGAP_H
  25
  26 /**
  27  * *** OMAP5430 ***
  28  *
  29  * Below, in sequence, are the Register definitions,
  30  * the bitfields and the temperature definitions for OMAP5430.
  31  */
  32
  33 /**
  34  * OMAP5430 register definitions
  35  *
  36  * Registers are defined as offsets. The offsets are
  37  * relative to FUSE_OPP_BGAP_GPU on 5430.
  38  *
  39  * Register below are grouped by domain (not necessarily in offset order)
  40  */
  41
  42 /* OMAP5430.GPU register offsets */
  43 #define OMAP5430_FUSE_OPP_BGAP_GPU                      0x0
  44 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET                 0x150
  45 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET              0x1A8
  46 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET                  0x1B4
  47 #define OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET            0x1C0
  48 #define OMAP5430_BGAP_DTEMP_GPU_0_OFFSET                0x1F4
  49 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET                0x1F8
  50 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET                0x1FC
  51 #define OMAP5430_BGAP_DTEMP_GPU_3_OFFSET                0x200
  52 #define OMAP5430_BGAP_DTEMP_GPU_4_OFFSET                0x204
  53
  54 /* OMAP5430.MPU register offsets */
  55 #define OMAP5430_FUSE_OPP_BGAP_MPU                      0x4
  56 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET                 0x14C
  57 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET              0x1A4
  58 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET                  0x1B0
  59 #define OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET            0x1BC
  60 #define OMAP5430_BGAP_DTEMP_MPU_0_OFFSET                0x1E0
  61 #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET                0x1E4
  62 #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET                0x1E8
  63 #define OMAP5430_BGAP_DTEMP_MPU_3_OFFSET                0x1EC
  64 #define OMAP5430_BGAP_DTEMP_MPU_4_OFFSET                0x1F0
  65
  66 /* OMAP5430.MPU register offsets */
  67 #define OMAP5430_FUSE_OPP_BGAP_CORE                     0x8
  68 #define OMAP5430_TEMP_SENSOR_CORE_OFFSET                0x154
  69 #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET             0x1AC
  70 #define OMAP5430_BGAP_TSHUT_CORE_OFFSET                 0x1B8
  71 #define OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET           0x1C4
  72 #define OMAP5430_BGAP_DTEMP_CORE_0_OFFSET               0x208
  73 #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET               0x20C
  74 #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET               0x210
  75 #define OMAP5430_BGAP_DTEMP_CORE_3_OFFSET               0x214
  76 #define OMAP5430_BGAP_DTEMP_CORE_4_OFFSET               0x218
  77
  78 /* OMAP5430.common register offsets */
  79 #define OMAP5430_BGAP_CTRL_OFFSET                       0x1A0
  80 #define OMAP5430_BGAP_STATUS_OFFSET                     0x1C8
  81
  82 /**
  83  * Register bitfields for OMAP5430
  84  *
  85  * All the macros bellow define the required bits for
  86  * controlling temperature on OMAP5430. Bit defines are
  87  * grouped by register.
  88  */
  89
  90 /* OMAP5430.TEMP_SENSOR */
  91 #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK              BIT(12)
  92 #define OMAP5430_BGAP_TEMPSOFF_MASK                     BIT(11)
  93 #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK             BIT(10)
  94 #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK            (0x3ff << 0)
  95
  96 /* OMAP5430.BANDGAP_CTRL */
  97 #define OMAP5430_MASK_SIDLEMODE_MASK                    (0x3 << 30)
  98 #define OMAP5430_MASK_COUNTER_DELAY_MASK                (0x7 << 27)
  99 #define OMAP5430_MASK_FREEZE_CORE_MASK                  BIT(23)
 100 #define OMAP5430_MASK_FREEZE_GPU_MASK                   BIT(22)
 101 #define OMAP5430_MASK_FREEZE_MPU_MASK                   BIT(21)
 102 #define OMAP5430_MASK_CLEAR_CORE_MASK                   BIT(20)
 103 #define OMAP5430_MASK_CLEAR_GPU_MASK                    BIT(19)
 104 #define OMAP5430_MASK_CLEAR_MPU_MASK                    BIT(18)
 105 #define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK             BIT(17)
 106 #define OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK              BIT(16)
 107 #define OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK              BIT(15)
 108 #define OMAP5430_MASK_HOT_CORE_MASK                     BIT(5)
 109 #define OMAP5430_MASK_COLD_CORE_MASK                    BIT(4)
 110 #define OMAP5430_MASK_HOT_GPU_MASK                      BIT(3)
 111 #define OMAP5430_MASK_COLD_GPU_MASK                     BIT(2)
 112 #define OMAP5430_MASK_HOT_MPU_MASK                      BIT(1)
 113 #define OMAP5430_MASK_COLD_MPU_MASK                     BIT(0)
 114
 115 /* OMAP5430.BANDGAP_COUNTER */
 116 #define OMAP5430_COUNTER_MASK                           (0xffffff << 0)
 117
 118 /* OMAP5430.BANDGAP_THRESHOLD */
 119 #define OMAP5430_T_HOT_MASK                             (0x3ff << 16)
 120 #define OMAP5430_T_COLD_MASK                            (0x3ff << 0)
 121
 122 /* OMAP5430.TSHUT_THRESHOLD */
 123 #define OMAP5430_TSHUT_HOT_MASK                         (0x3ff << 16)
 124 #define OMAP5430_TSHUT_COLD_MASK                        (0x3ff << 0)
 125
 126 /* OMAP5430.BANDGAP_CUMUL_DTEMP_MPU */
 127 #define OMAP5430_CUMUL_DTEMP_MPU_MASK                   (0xffffffff << 0)
 128
 129 /* OMAP5430.BANDGAP_CUMUL_DTEMP_GPU */
 130 #define OMAP5430_CUMUL_DTEMP_GPU_MASK                   (0xffffffff << 0)
 131
 132 /* OMAP5430.BANDGAP_CUMUL_DTEMP_CORE */
 133 #define OMAP5430_CUMUL_DTEMP_CORE_MASK                  (0xffffffff << 0)
 134
 135 /* OMAP5430.BANDGAP_STATUS */
 136 #define OMAP5430_BGAP_ALERT_MASK                        BIT(31)
 137 #define OMAP5430_HOT_CORE_FLAG_MASK                     BIT(5)
 138 #define OMAP5430_COLD_CORE_FLAG_MASK                    BIT(4)
 139 #define OMAP5430_HOT_GPU_FLAG_MASK                      BIT(3)
 140 #define OMAP5430_COLD_GPU_FLAG_MASK                     BIT(2)
 141 #define OMAP5430_HOT_MPU_FLAG_MASK                      BIT(1)
 142 #define OMAP5430_COLD_MPU_FLAG_MASK                     BIT(0)
 143
 144 /**
 145  * Temperature limits and thresholds for OMAP5430
 146  *
 147  * All the macros bellow are definitions for handling the
 148  * ADC conversions and representation of temperature limits
 149  * and thresholds for OMAP5430. Definitions are grouped
 150  * by temperature domain.
 151  */
 152
 153 /* OMAP5430.common temperature definitions */
 154 /* ADC conversion table limits */
 155 #define OMAP5430_ADC_START_VALUE                        540
 156 #define OMAP5430_ADC_END_VALUE                          945
 157
 158 /* OMAP5430.GPU temperature definitions */
 159 /* bandgap clock limits */
 160 #define OMAP5430_GPU_MAX_FREQ                           1500000
 161 #define OMAP5430_GPU_MIN_FREQ                           1000000
 162 /* sensor limits */
 163 #define OMAP5430_GPU_MIN_TEMP                           -40000
 164 #define OMAP5430_GPU_MAX_TEMP                           125000
 165 #define OMAP5430_GPU_HYST_VAL                           5000
 166 /* interrupts thresholds */
 167 #define OMAP5430_GPU_TSHUT_HOT                          915
 168 #define OMAP5430_GPU_TSHUT_COLD                         900
 169 #define OMAP5430_GPU_T_HOT                              800
 170 #define OMAP5430_GPU_T_COLD                             795
 171
 172 /* OMAP5430.MPU temperature definitions */
 173 /* bandgap clock limits */
 174 #define OMAP5430_MPU_MAX_FREQ                           1500000
 175 #define OMAP5430_MPU_MIN_FREQ                           1000000
 176 /* sensor limits */
 177 #define OMAP5430_MPU_MIN_TEMP                           -40000
 178 #define OMAP5430_MPU_MAX_TEMP                           125000
 179 #define OMAP5430_MPU_HYST_VAL                           5000
 180 /* interrupts thresholds */
 181 #define OMAP5430_MPU_TSHUT_HOT                          915
 182 #define OMAP5430_MPU_TSHUT_COLD                         900
 183 #define OMAP5430_MPU_T_HOT                              800
 184 #define OMAP5430_MPU_T_COLD                             795
 185
 186 /* OMAP5430.CORE temperature definitions */
 187 /* bandgap clock limits */
 188 #define OMAP5430_CORE_MAX_FREQ                          1500000
 189 #define OMAP5430_CORE_MIN_FREQ                          1000000
 190 /* sensor limits */
 191 #define OMAP5430_CORE_MIN_TEMP                          -40000
 192 #define OMAP5430_CORE_MAX_TEMP                          125000
 193 #define OMAP5430_CORE_HYST_VAL                          5000
 194 /* interrupts thresholds */
 195 #define OMAP5430_CORE_TSHUT_HOT                         915
 196 #define OMAP5430_CORE_TSHUT_COLD                        900
 197 #define OMAP5430_CORE_T_HOT                             800
 198 #define OMAP5430_CORE_T_COLD                            795
 199
 200 #endif /* __OMAP5XXX_BANDGAP_H */