powerpc/pci: Fix SRIOV not building without EEH enabled
[linux/fpc-iii.git] / arch / mips / include / asm / mach-ralink / mt7621.h
bloba672e06fa5fd065ba492f6da7f45379b28b1e4b5
1 /*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2015 John Crispin <john@phrozen.org>
7 */
9 #ifndef _MT7621_REGS_H_
10 #define _MT7621_REGS_H_
12 #define MT7621_PALMBUS_BASE 0x1C000000
13 #define MT7621_PALMBUS_SIZE 0x03FFFFFF
15 #define MT7621_SYSC_BASE 0x1E000000
17 #define SYSC_REG_CHIP_NAME0 0x00
18 #define SYSC_REG_CHIP_NAME1 0x04
19 #define SYSC_REG_CHIP_REV 0x0c
20 #define SYSC_REG_SYSTEM_CONFIG0 0x10
21 #define SYSC_REG_SYSTEM_CONFIG1 0x14
23 #define CHIP_REV_PKG_MASK 0x1
24 #define CHIP_REV_PKG_SHIFT 16
25 #define CHIP_REV_VER_MASK 0xf
26 #define CHIP_REV_VER_SHIFT 8
27 #define CHIP_REV_ECO_MASK 0xf
29 #define MT7621_DRAM_BASE 0x0
30 #define MT7621_DDR2_SIZE_MIN 32
31 #define MT7621_DDR2_SIZE_MAX 256
33 #define MT7621_CHIP_NAME0 0x3637544D
34 #define MT7621_CHIP_NAME1 0x20203132
36 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
38 #endif