arch/arm/mach-imx/hardware.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
   4  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   5  */
   6
   7 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
   8 #define __ASM_ARCH_MXC_HARDWARE_H__
   9
  10 #ifndef __ASSEMBLY__
  11 #include <asm/io.h>
  12 #include <soc/imx/revision.h>
  13 #endif
  14 #include <linux/sizes.h>
  15
  16 #define addr_in_module(addr, mod) \
  17         ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
  18
  19 #define IMX_IO_P2V_MODULE(addr, module)                                 \
  20         (((addr) - module ## _BASE_ADDR) < module ## _SIZE ?            \
  21          (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
  22
  23 /*
  24  * This is rather complicated for humans and ugly to verify, but for a machine
  25  * it's OK.  Still more as it is usually only applied to constants.  The upsides
  26  * on using this approach are:
  27  *
  28  *  - same mapping on all i.MX machines
  29  *  - works for assembler, too
  30  *  - no need to nurture #defines for virtual addresses
  31  *
  32  * The downside it, it's hard to verify (but I have a script for that).
  33  *
  34  * Obviously this needs to be injective for each SoC.  In general it maps the
  35  * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]
  36  * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
  37  *
  38  * It applies the following mappings for the different SoCs:
  39  *
  40  * mx1:
  41  *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
  42  * mx21:
  43  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
  44  *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  45  *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
  46  * mx25:
  47  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  48  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  49  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  50  * mx27:
  51  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
  52  *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  53  *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
  54  * mx31:
  55  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  56  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  57  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  58  *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  59  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  60  * mx35:
  61  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  62  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  63  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  64  *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  65  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  66  * mx51:
  67  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
  68  *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
  69  *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
  70  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  71  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
  72  *      AIPS2   0x83f00000+0x100000     ->      0xf5300000+0x100000
  73  * mx53:
  74  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
  75  *      DEBUG   0x40000000+0x100000     ->      0xf5000000+0x100000
  76  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  77  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  78  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  79  * mx6q:
  80  *      SCU     0x00a00000+0x004000     ->      0xf4000000+0x004000
  81  *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
  82  *      ANATOP  0x020c8000+0x004000     ->      0xf42c8000+0x004000
  83  *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
  84  */
  85 #define IMX_IO_P2V(x)   (                                               \
  86                         (((x) & 0x80000000) >> 7) |                     \
  87                         (0xf4000000 +                                   \
  88                         (((x) & 0x50000000) >> 6) +                     \
  89                         (((x) & 0x0b000000) >> 4) +                     \
  90                         (((x) & 0x000fffff))))
  91
  92 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
  93
  94 #include "mxc.h"
  95
  96 #include "mx3x.h"
  97 #include "mx31.h"
  98 #include "mx35.h"
  99 #include "mx2x.h"
 100 #include "mx21.h"
 101 #include "mx27.h"
 102
 103 #define imx_map_entry(soc, name, _type) {                               \
 104         .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
 105         .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
 106         .length = soc ## _ ## name ## _SIZE,                            \
 107         .type = _type,                                                  \
 108 }
 109
 110 /* There's an off-by-one between the gpio bank number and the gpiochip */
 111 /* range e.g. GPIO_1_5 is gpio 5 under linux */
 112 #define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
 113
 114 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */