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[linux/fpc-iii.git] / arch / arm / mach-mvebu / platsmp.c
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1 /*
2 * Symmetric Multi Processing (SMP) support for Armada XP
4 * Copyright (C) 2012 Marvell
6 * Lior Amsalem <alior@marvell.com>
7 * Yehuda Yitschak <yehuday@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
15 * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
16 * This file implements the routines for preparing the SMP infrastructure
17 * and waking up the secondary CPUs
20 #include <linux/init.h>
21 #include <linux/smp.h>
22 #include <linux/clk.h>
23 #include <linux/of.h>
24 #include <linux/of_address.h>
25 #include <linux/mbus.h>
26 #include <asm/cacheflush.h>
27 #include <asm/smp_plat.h>
28 #include "common.h"
29 #include "armada-370-xp.h"
30 #include "pmsu.h"
31 #include "coherency.h"
33 #define ARMADA_XP_MAX_CPUS 4
35 #define AXP_BOOTROM_BASE 0xfff00000
36 #define AXP_BOOTROM_SIZE 0x100000
38 static struct clk *boot_cpu_clk;
40 static struct clk *get_cpu_clk(int cpu)
42 struct clk *cpu_clk;
43 struct device_node *np = of_get_cpu_node(cpu, NULL);
45 if (WARN(!np, "missing cpu node\n"))
46 return NULL;
47 cpu_clk = of_clk_get(np, 0);
48 if (WARN_ON(IS_ERR(cpu_clk)))
49 return NULL;
50 return cpu_clk;
53 static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
55 int ret, hw_cpu;
57 pr_info("Booting CPU %d\n", cpu);
59 hw_cpu = cpu_logical_map(cpu);
60 mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
63 * This is needed to wake up CPUs in the offline state after
64 * using CPU hotplug.
66 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
69 * This is needed to take secondary CPUs out of reset on the
70 * initial boot.
72 ret = mvebu_cpu_reset_deassert(hw_cpu);
73 if (ret) {
74 pr_warn("unable to boot CPU: %d\n", ret);
75 return ret;
78 return 0;
82 * When a CPU is brought back online, either through CPU hotplug, or
83 * because of the boot of a kexec'ed kernel, the PMSU configuration
84 * for this CPU might be in the deep idle state, preventing this CPU
85 * from receiving interrupts. Here, we therefore take out the current
86 * CPU from this state, which was entered by armada_xp_cpu_die()
87 * below.
89 static void armada_xp_secondary_init(unsigned int cpu)
91 mvebu_v7_pmsu_idle_exit();
94 static void __init armada_xp_smp_init_cpus(void)
96 unsigned int ncores = num_possible_cpus();
98 if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
99 panic("Invalid number of CPUs in DT\n");
102 static int armada_xp_sync_secondary_clk(unsigned int cpu)
104 struct clk *cpu_clk = get_cpu_clk(cpu);
106 if (!cpu_clk || !boot_cpu_clk)
107 return 0;
109 clk_prepare_enable(cpu_clk);
110 clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));
112 return 0;
115 static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
117 struct device_node *node;
118 struct resource res;
119 int err;
121 flush_cache_all();
122 set_cpu_coherent();
124 boot_cpu_clk = get_cpu_clk(smp_processor_id());
125 if (boot_cpu_clk) {
126 clk_prepare_enable(boot_cpu_clk);
127 cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS,
128 "arm/mvebu/sync_clocks:online",
129 armada_xp_sync_secondary_clk, NULL);
133 * In order to boot the secondary CPUs we need to ensure
134 * the bootROM is mapped at the correct address.
136 node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
137 if (!node)
138 panic("Cannot find 'marvell,bootrom' compatible node");
140 err = of_address_to_resource(node, 0, &res);
141 of_node_put(node);
142 if (err < 0)
143 panic("Cannot get 'bootrom' node address");
145 if (res.start != AXP_BOOTROM_BASE ||
146 resource_size(&res) != AXP_BOOTROM_SIZE)
147 panic("The address for the BootROM is incorrect");
150 #ifdef CONFIG_HOTPLUG_CPU
151 static void armada_xp_cpu_die(unsigned int cpu)
154 * CPU hotplug is implemented by putting offline CPUs into the
155 * deep idle sleep state.
157 armada_370_xp_pmsu_idle_enter(true);
161 * We need a dummy function, so that platform_can_cpu_hotplug() knows
162 * we support CPU hotplug. However, the function does not need to do
163 * anything, because CPUs going offline can enter the deep idle state
164 * by themselves, without any help from a still alive CPU.
166 static int armada_xp_cpu_kill(unsigned int cpu)
168 return 1;
170 #endif
172 const struct smp_operations armada_xp_smp_ops __initconst = {
173 .smp_init_cpus = armada_xp_smp_init_cpus,
174 .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
175 .smp_boot_secondary = armada_xp_boot_secondary,
176 .smp_secondary_init = armada_xp_secondary_init,
177 #ifdef CONFIG_HOTPLUG_CPU
178 .cpu_die = armada_xp_cpu_die,
179 .cpu_kill = armada_xp_cpu_kill,
180 #endif
183 CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
184 &armada_xp_smp_ops);
186 #define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
187 #define MV98DX3236_CPU_RESUME_ADDR_REG 0x04
189 static const struct of_device_id of_mv98dx3236_resume_table[] = {
191 .compatible = "marvell,98dx3336-resume-ctrl",
193 { /* end of list */ },
196 static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
198 struct device_node *np;
199 void __iomem *base;
200 WARN_ON(hw_cpu != 1);
202 np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
203 if (!np)
204 return -ENODEV;
206 base = of_io_request_and_map(np, 0, of_node_full_name(np));
207 of_node_put(np);
208 if (IS_ERR(base))
209 return PTR_ERR(base);
211 writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
212 writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
214 iounmap(base);
216 return 0;
219 static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
221 int ret, hw_cpu;
223 hw_cpu = cpu_logical_map(cpu);
224 mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
225 armada_xp_secondary_startup);
228 * This is needed to wake up CPUs in the offline state after
229 * using CPU hotplug.
231 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
234 * This is needed to take secondary CPUs out of reset on the
235 * initial boot.
237 ret = mvebu_cpu_reset_deassert(hw_cpu);
238 if (ret) {
239 pr_warn("unable to boot CPU: %d\n", ret);
240 return ret;
243 return 0;
246 static const struct smp_operations mv98dx3236_smp_ops __initconst = {
247 .smp_init_cpus = armada_xp_smp_init_cpus,
248 .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
249 .smp_boot_secondary = mv98dx3236_boot_secondary,
250 .smp_secondary_init = armada_xp_secondary_init,
251 #ifdef CONFIG_HOTPLUG_CPU
252 .cpu_die = armada_xp_cpu_die,
253 .cpu_kill = armada_xp_cpu_kill,
254 #endif
257 CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
258 &mv98dx3236_smp_ops);