| blob | 73338cf80d76ca66813931bbdadf32eabb186aa7 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP2/3 System Control Module register access
4 *
5 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007 Nokia Corporation
7 *
8 * Written by Paul Walmsley
9 */
10 #undef DEBUG
12 #include <linux/kernel.h>
13 #include <linux/io.h>
14 #include <linux/of_address.h>
15 #include <linux/regmap.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/cpu_pm.h>
31 /* Used by omap3_ctrl_save_padconf() */
32 #define START_PADCONF_SAVE 0x2
33 #define PADCONF_SAVE_DONE 0x1
38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
40 u32 boot_config_ptr;
41 u32 public_restore_ptr;
42 u32 secure_ram_restore_ptr;
43 u32 sdrc_module_semaphore;
44 u32 prcm_block_offset;
45 u32 sdrc_block_offset;
46 };
51 u32 prcm_block_size;
52 };
55 u16 sysconfig;
56 u16 cs_cfg;
57 u16 sharing;
58 u16 err_type;
59 u32 dll_a_ctrl;
60 u32 dll_b_ctrl;
61 u32 power;
62 u32 cs_0;
63 u32 mcfg_0;
64 u16 mr_0;
65 u16 emr_1_0;
66 u16 emr_2_0;
67 u16 emr_3_0;
68 u32 actim_ctrla_0;
69 u32 actim_ctrlb_0;
70 u32 rfr_ctrl_0;
71 u32 cs_1;
72 u32 mcfg_1;
73 u16 mr_1;
74 u16 emr_1_1;
75 u16 emr_2_1;
76 u16 emr_3_1;
77 u32 actim_ctrla_1;
78 u32 actim_ctrlb_1;
79 u32 rfr_ctrl_1;
80 u16 dcdl_1_ctrl;
81 u16 dcdl_2_ctrl;
82 u32 flags;
83 u32 block_size;
84 };
88 /*
89 * This is used to store ARM registers in SDRAM before attempting
90 * an MPU OFF. The save and restore happens from the SRAM sleep code.
91 * The address is stored in scratchpad, so that it can be used
92 * during the restore path.
93 */
97 u32 sysconfig;
98 u32 devconf0;
99 u32 mem_dftrw0;
100 u32 mem_dftrw1;
101 u32 msuspendmux_0;
102 u32 msuspendmux_1;
103 u32 msuspendmux_2;
104 u32 msuspendmux_3;
105 u32 msuspendmux_4;
106 u32 msuspendmux_5;
107 u32 sec_ctrl;
108 u32 devconf1;
109 u32 csirxfe;
110 u32 iva2_bootaddr;
111 u32 iva2_bootmod;
112 u32 wkup_ctrl;
113 u32 debobs_0;
114 u32 debobs_1;
115 u32 debobs_2;
116 u32 debobs_3;
117 u32 debobs_4;
118 u32 debobs_5;
119 u32 debobs_6;
120 u32 debobs_7;
121 u32 debobs_8;
122 u32 prog_io0;
123 u32 prog_io1;
124 u32 dss_dpll_spreading;
125 u32 core_dpll_spreading;
126 u32 per_dpll_spreading;
127 u32 usbhost_dpll_spreading;
128 u32 pbias_lite;
129 u32 temp_sensor;
130 u32 sramldo4;
131 u32 sramldo5;
132 u32 csi;
133 u32 padconf_sys_nirq;
134 };
140 {
142 }
145 {
146 u32 val;
152 }
155 {
156 u32 val;
162 }
165 {
169 }
172 {
173 u32 tmp;
182 }
185 {
186 u32 tmp;
195 }
198 {
201 }
203 #ifdef CONFIG_ARCH_OMAP3
205 /**
206 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
207 * @bootmode: 8-bit value to pass to some boot code
208 *
209 * Set the bootmode in the scratchpad RAM. This is used after the
210 * system restarts. Not sure what actually uses this - it may be the
211 * bootloader, rather than the boot ROM - contrary to the preserved
212 * comment below. No return value.
213 */
215 {
216 u32 l;
220 /*
221 * Reserve the first word in scratchpad for communicating
222 * with the boot ROM. A pointer to a data structure
223 * describing the boot process can be stored there,
224 * cf. OMAP34xx TRM, Initialization / Software Booting
225 * Configuration.
226 *
227 * XXX This should use some omap_ctrl_writel()-type function
228 */
230 }
232 #endif
234 /**
235 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
236 * @bootaddr: physical address of the boot loader
237 *
238 * Set boot address for the boot loader of a supported processor
239 * when a power ON sequence occurs.
240 */
242 {
252 }
255 }
257 /**
258 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
259 * @bootmode: 8-bit value to pass to some boot code
260 *
261 * Sets boot mode for the boot loader of a supported processor
262 * when a power ON sequence occurs.
263 */
265 {
273 }
276 }
278 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
279 /*
280 * Clears the scratchpad contents in case of cold boot-
281 * called during bootup
282 */
284 {
293 }
294 }
296 /* Populate the scratchpad structure with restore structure */
298 {
300 u32 arm_context_addr;
305 /*
306 * Populate the Scratchpad contents
307 *
308 * The "get_*restore_pointer" functions are used to provide a
309 * physical restore address where the ROM code jumps while waking
310 * up from MPU OFF/OSWR state.
311 * The restore pointer is stored into the scratchpad.
312 */
322 else
328 else
335 /* Populate the PRCM block contents */
341 /* Populate the SDRC block contents */
352 /*
353 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
354 * be programed to issue automatic self refresh on timeout
355 * of AUTO_CNT = 1 prior to any transition to OFF mode.
356 */
361 SDRC_POWER_CLKCTRL_MASK)) |
363 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
364 else
398 /* Copy all the contents to the scratchpad location */
402 /* Scratchpad contents being 32 bits, a divide by 4 done here */
409 /*
410 * Copies the address of the location in SDRAM where ARM
411 * registers get saved during a MPU OFF transition.
412 */
416 }
419 {
474 }
477 {
481 OMAP343X_CONTROL_MEM_DFTRW0);
483 OMAP343X_CONTROL_MEM_DFTRW1);
485 OMAP2_CONTROL_MSUSPENDMUX_0);
487 OMAP2_CONTROL_MSUSPENDMUX_1);
489 OMAP2_CONTROL_MSUSPENDMUX_2);
491 OMAP2_CONTROL_MSUSPENDMUX_3);
493 OMAP2_CONTROL_MSUSPENDMUX_4);
495 OMAP2_CONTROL_MSUSPENDMUX_5);
500 OMAP343X_CONTROL_IVA2_BOOTADDR);
502 OMAP343X_CONTROL_IVA2_BOOTMOD);
516 OMAP343X_CONTROL_DSS_DPLL_SPREADING);
518 OMAP343X_CONTROL_CORE_DPLL_SPREADING);
520 OMAP343X_CONTROL_PER_DPLL_SPREADING);
522 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
524 OMAP343X_CONTROL_PBIAS_LITE);
526 OMAP343X_CONTROL_TEMP_SENSOR);
531 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
532 }
535 {
539 }
541 /**
542 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
543 *
544 * Tell the SCM to start saving the padconf registers, then wait for
545 * the process to complete. Returns 0 unconditionally, although it
546 * should also eventually be able to return -ETIMEDOUT, if the save
547 * does not complete.
548 *
549 * XXX This function is missing a timeout. What should it be?
550 */
552 {
553 u32 cpo;
555 /* Save the padconf registers */
560 /* wait for the save to complete */
566 }
568 /**
569 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
570 *
571 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
572 * force disable IVA2 so that it does not prevent any low-power states.
573 */
575 {
577 OMAP343X_CONTROL_IVA2_BOOTMOD);
578 }
580 /**
581 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
582 *
583 * Sets up the pads controlling the stacked modem in such way that the
584 * device can enter idle.
585 */
587 {
590 /*
591 * In a stand alone OMAP3430 where there is not a stacked
592 * modem for the D2D Idle Ack and D2D MStandby must be pulled
593 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
594 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
595 */
604 }
606 /**
607 * omap3_ctrl_init - does static initializations for control module
608 *
609 * Initializes system control module. This sets up the sysconfig autoidle,
610 * and sets up modem and iva2 so that they can be idled properly.
611 */
613 {
619 }
623 AM33XX_CONTROL_SYSCONFIG_OFFSET,
624 AM33XX_CONTROL_STATUS_OFFSET,
625 AM43XX_CONTROL_MPU_L2_CTRL_OFFSET,
626 AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET,
627 AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET,
628 AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET,
629 AM33XX_CONTROL_BANDGAP_CTRL_OFFSET,
630 AM33XX_CONTROL_BANDGAP_TRIM_OFFSET,
631 AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET,
632 AM33XX_CONTROL_MOSC_CTRL_OFFSET,
633 AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET,
634 AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET,
635 AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET,
636 AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET,
637 AM33XX_CONTROL_TPTC_CFG_OFFSET,
638 AM33XX_CONTROL_USB_CTRL0_OFFSET,
639 AM33XX_CONTROL_USB_CTRL1_OFFSET,
640 AM43XX_CONTROL_USB_CTRL2_OFFSET,
641 AM43XX_CONTROL_GMII_SEL_OFFSET,
642 AM43XX_CONTROL_MPUSS_CTRL_OFFSET,
643 AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET,
644 AM43XX_CONTROL_PWMSS_CTRL_OFFSET,
645 AM33XX_CONTROL_MREQPRIO_0_OFFSET,
646 AM33XX_CONTROL_MREQPRIO_1_OFFSET,
647 AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET,
648 AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET,
649 AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET,
650 AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET,
651 AM33XX_CONTROL_SMRT_CTRL_OFFSET,
652 AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET,
653 AM43XX_CONTROL_CQDETECT_STS_OFFSET,
654 AM43XX_CONTROL_CQDETECT_STS2_OFFSET,
655 AM43XX_CONTROL_VTP_CTRL_OFFSET,
656 AM33XX_CONTROL_VREF_CTRL_OFFSET,
657 AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET,
658 AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET,
659 AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET,
660 AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET,
661 AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET,
662 AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET,
663 AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET,
664 AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET,
665 AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET,
666 AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET,
667 AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET,
668 AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET,
669 AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET,
670 AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET,
671 AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET,
672 AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET,
673 AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET,
674 AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET,
675 AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET,
676 AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET,
677 AM33XX_CONTROL_RESET_ISO_OFFSET,
678 };
682 /**
683 * am43xx_control_save_context - Save the wakeup domain registers
684 *
685 * Save the wkup domain registers
686 */
688 {
694 }
696 /**
697 * am43xx_control_restore_context - Restore the wakeup domain registers
698 *
699 * Restore the wkup domain registers
700 */
702 {
708 }
711 {
721 }
724 }
729 s16 offset;
730 };
734 };
739 };
743 };
756 { }
757 };
759 /**
760 * omap2_control_base_init - initialize iomappings for the control driver
761 *
762 * Detects and initializes the iomappings for the control driver, based
763 * on the DT data. Returns 0 in success, negative error value
764 * otherwise.
765 */
767 {
783 }
786 }
789 }
791 /**
792 * omap_control_init - low level init for the control driver
793 *
794 * Initializes the low level clock infrastructure for control driver.
795 * Returns 0 in success, negative error value in failure.
796 */
798 {
809 /*
810 * Check if we have scm_conf node, if yes, use this to
811 * access clock registers.
812 */
827 }
829 /* No scm_conf found, direct access */
834 }
835 }
837 /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */
841 }
844 }
846 /**
847 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
848 *
849 * Legacy iomap init for clock provider. Needed only by legacy boot mode,
850 * where the base addresses are not parsed from DT, but still required
851 * by the clock driver to be setup properly.
852 */
854 {
856 }