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Linux 5.7.7
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_3xxx_data.c
blob3c8d2b6e887af4461f882ca7aacb6ce699b446c9
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * The data in this file should be completely autogeneratable from
10 * the TI hardware database or other technical documentation.
11 *
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14
15 #include <linux/platform_data/i2c-omap.h>
16 #include <linux/power/smartreflex.h>
17 #include <linux/platform_data/hsmmc-omap.h>
18
19 #include "l3_3xxx.h"
20 #include "l4_3xxx.h"
21
22 #include "soc.h"
23 #include "omap_hwmod.h"
24 #include "omap_hwmod_common_data.h"
25 #include "prm-regbits-34xx.h"
26 #include "cm-regbits-34xx.h"
27
28 #include "i2c.h"
29 #include "wd_timer.h"
30 #include "serial.h"
31
32 /*
33 * OMAP3xxx hardware module integration data
34 *
35 * All of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
38 * elsewhere.
39 */
40
41 #define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
42
43 /*
44 * IP blocks
45 */
46
47 /* L3 */
48
49 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
50 .name = "l3_main",
51 .class = &l3_hwmod_class,
52 .flags = HWMOD_NO_IDLEST,
53 };
54
55 /* L4 CORE */
56 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
57 .name = "l4_core",
58 .class = &l4_hwmod_class,
59 .flags = HWMOD_NO_IDLEST,
60 };
61
62 /* L4 PER */
63 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
64 .name = "l4_per",
65 .class = &l4_hwmod_class,
66 .flags = HWMOD_NO_IDLEST,
67 };
68
69 /* L4 WKUP */
70 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
71 .name = "l4_wkup",
72 .class = &l4_hwmod_class,
73 .flags = HWMOD_NO_IDLEST,
74 };
75
76 /* L4 SEC */
77 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
78 .name = "l4_sec",
79 .class = &l4_hwmod_class,
80 .flags = HWMOD_NO_IDLEST,
81 };
82
83 /* MPU */
84
85 static struct omap_hwmod omap3xxx_mpu_hwmod = {
86 .name = "mpu",
87 .class = &mpu_hwmod_class,
88 .main_clk = "arm_fck",
89 };
90
91 /* IVA2 (IVA2) */
92 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
93 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
94 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
95 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
96 };
97
98 static struct omap_hwmod omap3xxx_iva_hwmod = {
99 .name = "iva",
100 .class = &iva_hwmod_class,
101 .clkdm_name = "iva2_clkdm",
102 .rst_lines = omap3xxx_iva_resets,
103 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
104 .main_clk = "iva2_ck",
105 .prcm = {
106 .omap2 = {
107 .module_offs = OMAP3430_IVA2_MOD,
108 .idlest_reg_id = 1,
109 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
110 },
111 },
112 };
113
114 /*
115 * 'debugss' class
116 * debug and emulation sub system
117 */
118
119 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
120 .name = "debugss",
121 };
122
123 /* debugss */
124 static struct omap_hwmod omap3xxx_debugss_hwmod = {
125 .name = "debugss",
126 .class = &omap3xxx_debugss_hwmod_class,
127 .clkdm_name = "emu_clkdm",
128 .main_clk = "emu_src_ck",
129 .flags = HWMOD_NO_IDLEST,
130 };
131
132 /* timer class */
133 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
134 .rev_offs = 0x0000,
135 .sysc_offs = 0x0010,
136 .syss_offs = 0x0014,
137 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
138 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
139 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
140 SYSS_HAS_RESET_STATUS),
141 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
142 .sysc_fields = &omap_hwmod_sysc_type1,
143 };
144
145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
146 .name = "timer",
147 .sysc = &omap3xxx_timer_sysc,
148 };
149
150 /* timer1 */
151 static struct omap_hwmod omap3xxx_timer1_hwmod = {
152 .name = "timer1",
153 .main_clk = "gpt1_fck",
154 .prcm = {
155 .omap2 = {
156 .module_offs = WKUP_MOD,
157 .idlest_reg_id = 1,
158 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
159 },
160 },
161 .class = &omap3xxx_timer_hwmod_class,
162 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
163 };
164
165 /* timer2 */
166 static struct omap_hwmod omap3xxx_timer2_hwmod = {
167 .name = "timer2",
168 .main_clk = "gpt2_fck",
169 .prcm = {
170 .omap2 = {
171 .module_offs = OMAP3430_PER_MOD,
172 .idlest_reg_id = 1,
173 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
174 },
175 },
176 .class = &omap3xxx_timer_hwmod_class,
177 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
178 };
179
180 /* timer3 */
181 static struct omap_hwmod omap3xxx_timer3_hwmod = {
182 .name = "timer3",
183 .main_clk = "gpt3_fck",
184 .prcm = {
185 .omap2 = {
186 .module_offs = OMAP3430_PER_MOD,
187 .idlest_reg_id = 1,
188 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
189 },
190 },
191 .class = &omap3xxx_timer_hwmod_class,
192 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
193 };
194
195 /* timer4 */
196 static struct omap_hwmod omap3xxx_timer4_hwmod = {
197 .name = "timer4",
198 .main_clk = "gpt4_fck",
199 .prcm = {
200 .omap2 = {
201 .module_offs = OMAP3430_PER_MOD,
202 .idlest_reg_id = 1,
203 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
204 },
205 },
206 .class = &omap3xxx_timer_hwmod_class,
207 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
208 };
209
210 /* timer5 */
211 static struct omap_hwmod omap3xxx_timer5_hwmod = {
212 .name = "timer5",
213 .main_clk = "gpt5_fck",
214 .prcm = {
215 .omap2 = {
216 .module_offs = OMAP3430_PER_MOD,
217 .idlest_reg_id = 1,
218 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
219 },
220 },
221 .class = &omap3xxx_timer_hwmod_class,
222 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
223 };
224
225 /* timer6 */
226 static struct omap_hwmod omap3xxx_timer6_hwmod = {
227 .name = "timer6",
228 .main_clk = "gpt6_fck",
229 .prcm = {
230 .omap2 = {
231 .module_offs = OMAP3430_PER_MOD,
232 .idlest_reg_id = 1,
233 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
234 },
235 },
236 .class = &omap3xxx_timer_hwmod_class,
237 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
238 };
239
240 /* timer7 */
241 static struct omap_hwmod omap3xxx_timer7_hwmod = {
242 .name = "timer7",
243 .main_clk = "gpt7_fck",
244 .prcm = {
245 .omap2 = {
246 .module_offs = OMAP3430_PER_MOD,
247 .idlest_reg_id = 1,
248 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
249 },
250 },
251 .class = &omap3xxx_timer_hwmod_class,
252 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
253 };
254
255 /* timer8 */
256 static struct omap_hwmod omap3xxx_timer8_hwmod = {
257 .name = "timer8",
258 .main_clk = "gpt8_fck",
259 .prcm = {
260 .omap2 = {
261 .module_offs = OMAP3430_PER_MOD,
262 .idlest_reg_id = 1,
263 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
264 },
265 },
266 .class = &omap3xxx_timer_hwmod_class,
267 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
268 };
269
270 /* timer9 */
271 static struct omap_hwmod omap3xxx_timer9_hwmod = {
272 .name = "timer9",
273 .main_clk = "gpt9_fck",
274 .prcm = {
275 .omap2 = {
276 .module_offs = OMAP3430_PER_MOD,
277 .idlest_reg_id = 1,
278 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
279 },
280 },
281 .class = &omap3xxx_timer_hwmod_class,
282 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
283 };
284
285 /* timer10 */
286 static struct omap_hwmod omap3xxx_timer10_hwmod = {
287 .name = "timer10",
288 .main_clk = "gpt10_fck",
289 .prcm = {
290 .omap2 = {
291 .module_offs = CORE_MOD,
292 .idlest_reg_id = 1,
293 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
294 },
295 },
296 .class = &omap3xxx_timer_hwmod_class,
297 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
298 };
299
300 /* timer11 */
301 static struct omap_hwmod omap3xxx_timer11_hwmod = {
302 .name = "timer11",
303 .main_clk = "gpt11_fck",
304 .prcm = {
305 .omap2 = {
306 .module_offs = CORE_MOD,
307 .idlest_reg_id = 1,
308 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
309 },
310 },
311 .class = &omap3xxx_timer_hwmod_class,
312 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
313 };
314
315 /* timer12 */
316 static struct omap_hwmod omap3xxx_timer12_hwmod = {
317 .name = "timer12",
318 .main_clk = "gpt12_fck",
319 .prcm = {
320 .omap2 = {
321 .module_offs = WKUP_MOD,
322 .idlest_reg_id = 1,
323 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
324 },
325 },
326 .class = &omap3xxx_timer_hwmod_class,
327 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
328 };
329
330 /*
331 * 'wd_timer' class
332 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
333 * overflow condition
334 */
335
336 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
337 .rev_offs = 0x0000,
338 .sysc_offs = 0x0010,
339 .syss_offs = 0x0014,
340 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
341 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
342 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
343 SYSS_HAS_RESET_STATUS),
344 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
345 .sysc_fields = &omap_hwmod_sysc_type1,
346 };
347
348 /* I2C common */
349 static struct omap_hwmod_class_sysconfig i2c_sysc = {
350 .rev_offs = 0x00,
351 .sysc_offs = 0x20,
352 .syss_offs = 0x10,
353 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
354 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
355 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
357 .sysc_fields = &omap_hwmod_sysc_type1,
358 };
359
360 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
361 .name = "wd_timer",
362 .sysc = &omap3xxx_wd_timer_sysc,
363 .pre_shutdown = &omap2_wd_timer_disable,
364 .reset = &omap2_wd_timer_reset,
365 };
366
367 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
368 .name = "wd_timer2",
369 .class = &omap3xxx_wd_timer_hwmod_class,
370 .main_clk = "wdt2_fck",
371 .prcm = {
372 .omap2 = {
373 .module_offs = WKUP_MOD,
374 .idlest_reg_id = 1,
375 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
376 },
377 },
378 /*
379 * XXX: Use software supervised mode, HW supervised smartidle seems to
380 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
381 */
382 .flags = HWMOD_SWSUP_SIDLE,
383 };
384
385 /* UART1 */
386 static struct omap_hwmod omap3xxx_uart1_hwmod = {
387 .name = "uart1",
388 .main_clk = "uart1_fck",
389 .flags = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
390 .prcm = {
391 .omap2 = {
392 .module_offs = CORE_MOD,
393 .idlest_reg_id = 1,
394 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
395 },
396 },
397 .class = &omap2_uart_class,
398 };
399
400 /* UART2 */
401 static struct omap_hwmod omap3xxx_uart2_hwmod = {
402 .name = "uart2",
403 .main_clk = "uart2_fck",
404 .flags = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
405 .prcm = {
406 .omap2 = {
407 .module_offs = CORE_MOD,
408 .idlest_reg_id = 1,
409 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
410 },
411 },
412 .class = &omap2_uart_class,
413 };
414
415 /* UART3 */
416 static struct omap_hwmod omap3xxx_uart3_hwmod = {
417 .name = "uart3",
418 .main_clk = "uart3_fck",
419 .flags = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
420 HWMOD_SWSUP_SIDLE,
421 .prcm = {
422 .omap2 = {
423 .module_offs = OMAP3430_PER_MOD,
424 .idlest_reg_id = 1,
425 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
426 },
427 },
428 .class = &omap2_uart_class,
429 };
430
431 /* UART4 */
432
433
434 static struct omap_hwmod omap36xx_uart4_hwmod = {
435 .name = "uart4",
436 .main_clk = "uart4_fck",
437 .flags = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
438 .prcm = {
439 .omap2 = {
440 .module_offs = OMAP3430_PER_MOD,
441 .idlest_reg_id = 1,
442 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
443 },
444 },
445 .class = &omap2_uart_class,
446 };
447
448
449
450 /*
451 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
452 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
453 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
454 * should not be needed. The functional clock structure of the AM35xx
455 * UART4 is extremely unclear and opaque; it is unclear what the role
456 * of uart1/2_fck is for the UART4. Any clarification from either
457 * empirical testing or the AM3505/3517 hardware designers would be
458 * most welcome.
459 */
460 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
461 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
462 };
463
464 static struct omap_hwmod am35xx_uart4_hwmod = {
465 .name = "uart4",
466 .main_clk = "uart4_fck",
467 .prcm = {
468 .omap2 = {
469 .module_offs = CORE_MOD,
470 .idlest_reg_id = 1,
471 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
472 },
473 },
474 .opt_clks = am35xx_uart4_opt_clks,
475 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
476 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
477 .class = &omap2_uart_class,
478 };
479
480 static struct omap_hwmod_class i2c_class = {
481 .name = "i2c",
482 .sysc = &i2c_sysc,
483 .reset = &omap_i2c_reset,
484 };
485
486 /* dss */
487 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
488 /*
489 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
490 * driver does not use these clocks.
491 */
492 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
493 { .role = "tv_clk", .clk = "dss_tv_fck" },
494 /* required only on OMAP3430 */
495 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
496 };
497
498 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
499 .name = "dss_core",
500 .class = &omap2_dss_hwmod_class,
501 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
502 .prcm = {
503 .omap2 = {
504 .module_offs = OMAP3430_DSS_MOD,
505 .idlest_reg_id = 1,
506 },
507 },
508 .opt_clks = dss_opt_clks,
509 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
510 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
511 };
512
513 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
514 .name = "dss_core",
515 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
516 .class = &omap2_dss_hwmod_class,
517 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
518 .prcm = {
519 .omap2 = {
520 .module_offs = OMAP3430_DSS_MOD,
521 .idlest_reg_id = 1,
522 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
523 },
524 },
525 .opt_clks = dss_opt_clks,
526 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
527 };
528
529 /*
530 * 'dispc' class
531 * display controller
532 */
533
534 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
535 .rev_offs = 0x0000,
536 .sysc_offs = 0x0010,
537 .syss_offs = 0x0014,
538 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
539 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
540 SYSC_HAS_ENAWAKEUP),
541 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
542 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
543 .sysc_fields = &omap_hwmod_sysc_type1,
544 };
545
546 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
547 .name = "dispc",
548 .sysc = &omap3_dispc_sysc,
549 };
550
551 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
552 .name = "dss_dispc",
553 .class = &omap3_dispc_hwmod_class,
554 .main_clk = "dss1_alwon_fck",
555 .prcm = {
556 .omap2 = {
557 .module_offs = OMAP3430_DSS_MOD,
558 },
559 },
560 .flags = HWMOD_NO_IDLEST,
561 .dev_attr = &omap2_3_dss_dispc_dev_attr,
562 };
563
564 /*
565 * 'dsi' class
566 * display serial interface controller
567 */
568
569 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
570 .rev_offs = 0x0000,
571 .sysc_offs = 0x0010,
572 .syss_offs = 0x0014,
573 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
574 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
575 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
576 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
577 .sysc_fields = &omap_hwmod_sysc_type1,
578 };
579
580 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
581 .name = "dsi",
582 .sysc = &omap3xxx_dsi_sysc,
583 };
584
585 /* dss_dsi1 */
586 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
587 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
588 };
589
590 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
591 .name = "dss_dsi1",
592 .class = &omap3xxx_dsi_hwmod_class,
593 .main_clk = "dss1_alwon_fck",
594 .prcm = {
595 .omap2 = {
596 .module_offs = OMAP3430_DSS_MOD,
597 },
598 },
599 .opt_clks = dss_dsi1_opt_clks,
600 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
601 .flags = HWMOD_NO_IDLEST,
602 };
603
604 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
605 { .role = "ick", .clk = "dss_ick" },
606 };
607
608 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
609 .name = "dss_rfbi",
610 .class = &omap2_rfbi_hwmod_class,
611 .main_clk = "dss1_alwon_fck",
612 .prcm = {
613 .omap2 = {
614 .module_offs = OMAP3430_DSS_MOD,
615 },
616 },
617 .opt_clks = dss_rfbi_opt_clks,
618 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
619 .flags = HWMOD_NO_IDLEST,
620 };
621
622 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
623 /* required only on OMAP3430 */
624 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
625 };
626
627 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
628 .name = "dss_venc",
629 .class = &omap2_venc_hwmod_class,
630 .main_clk = "dss_tv_fck",
631 .prcm = {
632 .omap2 = {
633 .module_offs = OMAP3430_DSS_MOD,
634 },
635 },
636 .opt_clks = dss_venc_opt_clks,
637 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
638 .flags = HWMOD_NO_IDLEST,
639 };
640
641 /* I2C1 */
642 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
643 .name = "i2c1",
644 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
645 .main_clk = "i2c1_fck",
646 .prcm = {
647 .omap2 = {
648 .module_offs = CORE_MOD,
649 .idlest_reg_id = 1,
650 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
651 },
652 },
653 .class = &i2c_class,
654 };
655
656 /* I2C2 */
657 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
658 .name = "i2c2",
659 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
660 .main_clk = "i2c2_fck",
661 .prcm = {
662 .omap2 = {
663 .module_offs = CORE_MOD,
664 .idlest_reg_id = 1,
665 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
666 },
667 },
668 .class = &i2c_class,
669 };
670
671 /* I2C3 */
672 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
673 .name = "i2c3",
674 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
675 .main_clk = "i2c3_fck",
676 .prcm = {
677 .omap2 = {
678 .module_offs = CORE_MOD,
679 .idlest_reg_id = 1,
680 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
681 },
682 },
683 .class = &i2c_class,
684 };
685
686 /*
687 * 'gpio' class
688 * general purpose io module
689 */
690
691 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
692 .rev_offs = 0x0000,
693 .sysc_offs = 0x0010,
694 .syss_offs = 0x0014,
695 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
696 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
697 SYSS_HAS_RESET_STATUS),
698 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
699 .sysc_fields = &omap_hwmod_sysc_type1,
700 };
701
702 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
703 .name = "gpio",
704 .sysc = &omap3xxx_gpio_sysc,
705 };
706
707 /* gpio1 */
708 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio1_dbck", },
710 };
711
712 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
713 .name = "gpio1",
714 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
715 .main_clk = "gpio1_ick",
716 .opt_clks = gpio1_opt_clks,
717 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
718 .prcm = {
719 .omap2 = {
720 .module_offs = WKUP_MOD,
721 .idlest_reg_id = 1,
722 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
723 },
724 },
725 .class = &omap3xxx_gpio_hwmod_class,
726 };
727
728 /* gpio2 */
729 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
730 { .role = "dbclk", .clk = "gpio2_dbck", },
731 };
732
733 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
734 .name = "gpio2",
735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
736 .main_clk = "gpio2_ick",
737 .opt_clks = gpio2_opt_clks,
738 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
739 .prcm = {
740 .omap2 = {
741 .module_offs = OMAP3430_PER_MOD,
742 .idlest_reg_id = 1,
743 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
744 },
745 },
746 .class = &omap3xxx_gpio_hwmod_class,
747 };
748
749 /* gpio3 */
750 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
751 { .role = "dbclk", .clk = "gpio3_dbck", },
752 };
753
754 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
755 .name = "gpio3",
756 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
757 .main_clk = "gpio3_ick",
758 .opt_clks = gpio3_opt_clks,
759 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
760 .prcm = {
761 .omap2 = {
762 .module_offs = OMAP3430_PER_MOD,
763 .idlest_reg_id = 1,
764 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
765 },
766 },
767 .class = &omap3xxx_gpio_hwmod_class,
768 };
769
770 /* gpio4 */
771 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
772 { .role = "dbclk", .clk = "gpio4_dbck", },
773 };
774
775 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
776 .name = "gpio4",
777 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
778 .main_clk = "gpio4_ick",
779 .opt_clks = gpio4_opt_clks,
780 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
781 .prcm = {
782 .omap2 = {
783 .module_offs = OMAP3430_PER_MOD,
784 .idlest_reg_id = 1,
785 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
786 },
787 },
788 .class = &omap3xxx_gpio_hwmod_class,
789 };
790
791 /* gpio5 */
792
793 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
794 { .role = "dbclk", .clk = "gpio5_dbck", },
795 };
796
797 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
798 .name = "gpio5",
799 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
800 .main_clk = "gpio5_ick",
801 .opt_clks = gpio5_opt_clks,
802 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
803 .prcm = {
804 .omap2 = {
805 .module_offs = OMAP3430_PER_MOD,
806 .idlest_reg_id = 1,
807 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
808 },
809 },
810 .class = &omap3xxx_gpio_hwmod_class,
811 };
812
813 /* gpio6 */
814
815 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
816 { .role = "dbclk", .clk = "gpio6_dbck", },
817 };
818
819 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
820 .name = "gpio6",
821 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
822 .main_clk = "gpio6_ick",
823 .opt_clks = gpio6_opt_clks,
824 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
825 .prcm = {
826 .omap2 = {
827 .module_offs = OMAP3430_PER_MOD,
828 .idlest_reg_id = 1,
829 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
830 },
831 },
832 .class = &omap3xxx_gpio_hwmod_class,
833 };
834
835 /*
836 * 'mcbsp' class
837 * multi channel buffered serial port controller
838 */
839
840 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
841 .rev_offs = -ENODEV,
842 .sysc_offs = 0x008c,
843 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
844 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
845 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
846 .sysc_fields = &omap_hwmod_sysc_type1,
847 };
848
849 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
850 .name = "mcbsp",
851 .sysc = &omap3xxx_mcbsp_sysc,
852 };
853
854 /* McBSP functional clock mapping */
855 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
856 { .role = "pad_fck", .clk = "mcbsp_clks" },
857 { .role = "prcm_fck", .clk = "core_96m_fck" },
858 };
859
860 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
861 { .role = "pad_fck", .clk = "mcbsp_clks" },
862 { .role = "prcm_fck", .clk = "per_96m_fck" },
863 };
864
865 /* mcbsp1 */
866 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
867 .name = "mcbsp1",
868 .class = &omap3xxx_mcbsp_hwmod_class,
869 .main_clk = "mcbsp1_fck",
870 .prcm = {
871 .omap2 = {
872 .module_offs = CORE_MOD,
873 .idlest_reg_id = 1,
874 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
875 },
876 },
877 .opt_clks = mcbsp15_opt_clks,
878 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
879 };
880
881 /* mcbsp2 */
882 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
883 .name = "mcbsp2",
884 .class = &omap3xxx_mcbsp_hwmod_class,
885 .main_clk = "mcbsp2_fck",
886 .prcm = {
887 .omap2 = {
888 .module_offs = OMAP3430_PER_MOD,
889 .idlest_reg_id = 1,
890 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
891 },
892 },
893 .opt_clks = mcbsp234_opt_clks,
894 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
895 };
896
897 /* mcbsp3 */
898 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
899 .name = "mcbsp3",
900 .class = &omap3xxx_mcbsp_hwmod_class,
901 .main_clk = "mcbsp3_fck",
902 .prcm = {
903 .omap2 = {
904 .module_offs = OMAP3430_PER_MOD,
905 .idlest_reg_id = 1,
906 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
907 },
908 },
909 .opt_clks = mcbsp234_opt_clks,
910 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
911 };
912
913 /* mcbsp4 */
914 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
915 .name = "mcbsp4",
916 .class = &omap3xxx_mcbsp_hwmod_class,
917 .main_clk = "mcbsp4_fck",
918 .prcm = {
919 .omap2 = {
920 .module_offs = OMAP3430_PER_MOD,
921 .idlest_reg_id = 1,
922 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
923 },
924 },
925 .opt_clks = mcbsp234_opt_clks,
926 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
927 };
928
929 /* mcbsp5 */
930 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
931 .name = "mcbsp5",
932 .class = &omap3xxx_mcbsp_hwmod_class,
933 .main_clk = "mcbsp5_fck",
934 .prcm = {
935 .omap2 = {
936 .module_offs = CORE_MOD,
937 .idlest_reg_id = 1,
938 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
939 },
940 },
941 .opt_clks = mcbsp15_opt_clks,
942 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
943 };
944
945 /* 'mcbsp sidetone' class */
946 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
947 .rev_offs = -ENODEV,
948 .sysc_offs = 0x0010,
949 .sysc_flags = SYSC_HAS_AUTOIDLE,
950 .sysc_fields = &omap_hwmod_sysc_type1,
951 };
952
953 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
954 .name = "mcbsp_sidetone",
955 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
956 };
957
958 /* mcbsp2_sidetone */
959 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
960 .name = "mcbsp2_sidetone",
961 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
962 .main_clk = "mcbsp2_ick",
963 .flags = HWMOD_NO_IDLEST,
964 };
965
966 /* mcbsp3_sidetone */
967 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
968 .name = "mcbsp3_sidetone",
969 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
970 .main_clk = "mcbsp3_ick",
971 .flags = HWMOD_NO_IDLEST,
972 };
973
974 /* SR common */
975 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
976 .rev_offs = -ENODEV,
977 .sysc_offs = 0x24,
978 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
979 .sysc_fields = &omap34xx_sr_sysc_fields,
980 };
981
982 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
983 .name = "smartreflex",
984 .sysc = &omap34xx_sr_sysc,
985 };
986
987 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
988 .rev_offs = -ENODEV,
989 .sysc_offs = 0x38,
990 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
991 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
992 SYSC_NO_CACHE),
993 .sysc_fields = &omap36xx_sr_sysc_fields,
994 };
995
996 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
997 .name = "smartreflex",
998 .sysc = &omap36xx_sr_sysc,
999 };
1000
1001 /* SR1 */
1002 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1003 .sensor_voltdm_name = "mpu_iva",
1004 };
1005
1006
1007 static struct omap_hwmod omap34xx_sr1_hwmod = {
1008 .name = "smartreflex_mpu_iva",
1009 .class = &omap34xx_smartreflex_hwmod_class,
1010 .main_clk = "sr1_fck",
1011 .prcm = {
1012 .omap2 = {
1013 .module_offs = WKUP_MOD,
1014 .idlest_reg_id = 1,
1015 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1016 },
1017 },
1018 .dev_attr = &sr1_dev_attr,
1019 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1020 };
1021
1022 static struct omap_hwmod omap36xx_sr1_hwmod = {
1023 .name = "smartreflex_mpu_iva",
1024 .class = &omap36xx_smartreflex_hwmod_class,
1025 .main_clk = "sr1_fck",
1026 .prcm = {
1027 .omap2 = {
1028 .module_offs = WKUP_MOD,
1029 .idlest_reg_id = 1,
1030 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1031 },
1032 },
1033 .dev_attr = &sr1_dev_attr,
1034 };
1035
1036 /* SR2 */
1037 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1038 .sensor_voltdm_name = "core",
1039 };
1040
1041
1042 static struct omap_hwmod omap34xx_sr2_hwmod = {
1043 .name = "smartreflex_core",
1044 .class = &omap34xx_smartreflex_hwmod_class,
1045 .main_clk = "sr2_fck",
1046 .prcm = {
1047 .omap2 = {
1048 .module_offs = WKUP_MOD,
1049 .idlest_reg_id = 1,
1050 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1051 },
1052 },
1053 .dev_attr = &sr2_dev_attr,
1054 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1055 };
1056
1057 static struct omap_hwmod omap36xx_sr2_hwmod = {
1058 .name = "smartreflex_core",
1059 .class = &omap36xx_smartreflex_hwmod_class,
1060 .main_clk = "sr2_fck",
1061 .prcm = {
1062 .omap2 = {
1063 .module_offs = WKUP_MOD,
1064 .idlest_reg_id = 1,
1065 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1066 },
1067 },
1068 .dev_attr = &sr2_dev_attr,
1069 };
1070
1071 /*
1072 * 'mailbox' class
1073 * mailbox module allowing communication between the on-chip processors
1074 * using a queued mailbox-interrupt mechanism.
1075 */
1076
1077 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1078 .rev_offs = 0x000,
1079 .sysc_offs = 0x010,
1080 .syss_offs = 0x014,
1081 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1082 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1083 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1084 .sysc_fields = &omap_hwmod_sysc_type1,
1085 };
1086
1087 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1088 .name = "mailbox",
1089 .sysc = &omap3xxx_mailbox_sysc,
1090 };
1091
1092 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1093 .name = "mailbox",
1094 .class = &omap3xxx_mailbox_hwmod_class,
1095 .main_clk = "mailboxes_ick",
1096 .prcm = {
1097 .omap2 = {
1098 .module_offs = CORE_MOD,
1099 .idlest_reg_id = 1,
1100 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1101 },
1102 },
1103 };
1104
1105 /*
1106 * 'mcspi' class
1107 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1108 * bus
1109 */
1110
1111 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1112 .rev_offs = 0x0000,
1113 .sysc_offs = 0x0010,
1114 .syss_offs = 0x0014,
1115 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1116 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1117 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1118 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1119 .sysc_fields = &omap_hwmod_sysc_type1,
1120 };
1121
1122 static struct omap_hwmod_class omap34xx_mcspi_class = {
1123 .name = "mcspi",
1124 .sysc = &omap34xx_mcspi_sysc,
1125 };
1126
1127 /* mcspi1 */
1128 static struct omap_hwmod omap34xx_mcspi1 = {
1129 .name = "mcspi1",
1130 .main_clk = "mcspi1_fck",
1131 .prcm = {
1132 .omap2 = {
1133 .module_offs = CORE_MOD,
1134 .idlest_reg_id = 1,
1135 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1136 },
1137 },
1138 .class = &omap34xx_mcspi_class,
1139 };
1140
1141 /* mcspi2 */
1142 static struct omap_hwmod omap34xx_mcspi2 = {
1143 .name = "mcspi2",
1144 .main_clk = "mcspi2_fck",
1145 .prcm = {
1146 .omap2 = {
1147 .module_offs = CORE_MOD,
1148 .idlest_reg_id = 1,
1149 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1150 },
1151 },
1152 .class = &omap34xx_mcspi_class,
1153 };
1154
1155 /* mcspi3 */
1156 static struct omap_hwmod omap34xx_mcspi3 = {
1157 .name = "mcspi3",
1158 .main_clk = "mcspi3_fck",
1159 .prcm = {
1160 .omap2 = {
1161 .module_offs = CORE_MOD,
1162 .idlest_reg_id = 1,
1163 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1164 },
1165 },
1166 .class = &omap34xx_mcspi_class,
1167 };
1168
1169 /* mcspi4 */
1170 static struct omap_hwmod omap34xx_mcspi4 = {
1171 .name = "mcspi4",
1172 .main_clk = "mcspi4_fck",
1173 .prcm = {
1174 .omap2 = {
1175 .module_offs = CORE_MOD,
1176 .idlest_reg_id = 1,
1177 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1178 },
1179 },
1180 .class = &omap34xx_mcspi_class,
1181 };
1182
1183 /* usbhsotg */
1184 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1185 .rev_offs = 0x0400,
1186 .sysc_offs = 0x0404,
1187 .syss_offs = 0x0408,
1188 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1189 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1190 SYSC_HAS_AUTOIDLE),
1191 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1192 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1193 .sysc_fields = &omap_hwmod_sysc_type1,
1194 };
1195
1196 static struct omap_hwmod_class usbotg_class = {
1197 .name = "usbotg",
1198 .sysc = &omap3xxx_usbhsotg_sysc,
1199 };
1200
1201 /* usb_otg_hs */
1202
1203 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1204 .name = "usb_otg_hs",
1205 .main_clk = "hsotgusb_ick",
1206 .prcm = {
1207 .omap2 = {
1208 .module_offs = CORE_MOD,
1209 .idlest_reg_id = 1,
1210 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1211 },
1212 },
1213 .class = &usbotg_class,
1214
1215 /*
1216 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1217 * broken when autoidle is enabled
1218 * workaround is to disable the autoidle bit at module level.
1219 *
1220 * Enabling the device in any other MIDLEMODE setting but force-idle
1221 * causes core_pwrdm not enter idle states at least on OMAP3630.
1222 * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1223 * signal when MIDLEMODE is set to force-idle.
1224 */
1225 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1226 HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1227 };
1228
1229 /* usb_otg_hs */
1230
1231 static struct omap_hwmod_class am35xx_usbotg_class = {
1232 .name = "am35xx_usbotg",
1233 };
1234
1235 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1236 .name = "am35x_otg_hs",
1237 .main_clk = "hsotgusb_fck",
1238 .class = &am35xx_usbotg_class,
1239 .flags = HWMOD_NO_IDLEST,
1240 };
1241
1242 /* MMC/SD/SDIO common */
1243 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1244 .rev_offs = 0x1fc,
1245 .sysc_offs = 0x10,
1246 .syss_offs = 0x14,
1247 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1248 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1249 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1250 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1251 .sysc_fields = &omap_hwmod_sysc_type1,
1252 };
1253
1254 static struct omap_hwmod_class omap34xx_mmc_class = {
1255 .name = "mmc",
1256 .sysc = &omap34xx_mmc_sysc,
1257 };
1258
1259 /* MMC/SD/SDIO1 */
1260
1261
1262
1263 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1264 { .role = "dbck", .clk = "omap_32k_fck", },
1265 };
1266
1267 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1268 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1269 };
1270
1271 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1272 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1273 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1274 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1275 };
1276
1277 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1278 .name = "mmc1",
1279 .opt_clks = omap34xx_mmc1_opt_clks,
1280 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1281 .main_clk = "mmchs1_fck",
1282 .prcm = {
1283 .omap2 = {
1284 .module_offs = CORE_MOD,
1285 .idlest_reg_id = 1,
1286 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1287 },
1288 },
1289 .dev_attr = &mmc1_pre_es3_dev_attr,
1290 .class = &omap34xx_mmc_class,
1291 };
1292
1293 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1294 .name = "mmc1",
1295 .opt_clks = omap34xx_mmc1_opt_clks,
1296 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1297 .main_clk = "mmchs1_fck",
1298 .prcm = {
1299 .omap2 = {
1300 .module_offs = CORE_MOD,
1301 .idlest_reg_id = 1,
1302 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1303 },
1304 },
1305 .dev_attr = &mmc1_dev_attr,
1306 .class = &omap34xx_mmc_class,
1307 };
1308
1309 /* MMC/SD/SDIO2 */
1310
1311
1312
1313 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1314 { .role = "dbck", .clk = "omap_32k_fck", },
1315 };
1316
1317 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1318 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1319 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1320 };
1321
1322 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1323 .name = "mmc2",
1324 .opt_clks = omap34xx_mmc2_opt_clks,
1325 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1326 .main_clk = "mmchs2_fck",
1327 .prcm = {
1328 .omap2 = {
1329 .module_offs = CORE_MOD,
1330 .idlest_reg_id = 1,
1331 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1332 },
1333 },
1334 .dev_attr = &mmc2_pre_es3_dev_attr,
1335 .class = &omap34xx_mmc_class,
1336 };
1337
1338 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1339 .name = "mmc2",
1340 .opt_clks = omap34xx_mmc2_opt_clks,
1341 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1342 .main_clk = "mmchs2_fck",
1343 .prcm = {
1344 .omap2 = {
1345 .module_offs = CORE_MOD,
1346 .idlest_reg_id = 1,
1347 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1348 },
1349 },
1350 .class = &omap34xx_mmc_class,
1351 };
1352
1353 /* MMC/SD/SDIO3 */
1354
1355
1356
1357 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1358 { .role = "dbck", .clk = "omap_32k_fck", },
1359 };
1360
1361 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1362 .name = "mmc3",
1363 .opt_clks = omap34xx_mmc3_opt_clks,
1364 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1365 .main_clk = "mmchs3_fck",
1366 .prcm = {
1367 .omap2 = {
1368 .module_offs = CORE_MOD,
1369 .idlest_reg_id = 1,
1370 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1371 },
1372 },
1373 .class = &omap34xx_mmc_class,
1374 };
1375
1376 /*
1377 * 'usb_host_hs' class
1378 * high-speed multi-port usb host controller
1379 */
1380
1381 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1382 .rev_offs = 0x0000,
1383 .sysc_offs = 0x0010,
1384 .syss_offs = 0x0014,
1385 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1386 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1387 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1388 SYSS_HAS_RESET_STATUS),
1389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1390 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1391 .sysc_fields = &omap_hwmod_sysc_type1,
1392 };
1393
1394 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1395 .name = "usb_host_hs",
1396 .sysc = &omap3xxx_usb_host_hs_sysc,
1397 };
1398
1399
1400 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1401 .name = "usb_host_hs",
1402 .class = &omap3xxx_usb_host_hs_hwmod_class,
1403 .clkdm_name = "usbhost_clkdm",
1404 .main_clk = "usbhost_48m_fck",
1405 .prcm = {
1406 .omap2 = {
1407 .module_offs = OMAP3430ES2_USBHOST_MOD,
1408 .idlest_reg_id = 1,
1409 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1410 },
1411 },
1412
1413 /*
1414 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1415 * id: i660
1416 *
1417 * Description:
1418 * In the following configuration :
1419 * - USBHOST module is set to smart-idle mode
1420 * - PRCM asserts idle_req to the USBHOST module ( This typically
1421 * happens when the system is going to a low power mode : all ports
1422 * have been suspended, the master part of the USBHOST module has
1423 * entered the standby state, and SW has cut the functional clocks)
1424 * - an USBHOST interrupt occurs before the module is able to answer
1425 * idle_ack, typically a remote wakeup IRQ.
1426 * Then the USB HOST module will enter a deadlock situation where it
1427 * is no more accessible nor functional.
1428 *
1429 * Workaround:
1430 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1431 */
1432
1433 /*
1434 * Errata: USB host EHCI may stall when entering smart-standby mode
1435 * Id: i571
1436 *
1437 * Description:
1438 * When the USBHOST module is set to smart-standby mode, and when it is
1439 * ready to enter the standby state (i.e. all ports are suspended and
1440 * all attached devices are in suspend mode), then it can wrongly assert
1441 * the Mstandby signal too early while there are still some residual OCP
1442 * transactions ongoing. If this condition occurs, the internal state
1443 * machine may go to an undefined state and the USB link may be stuck
1444 * upon the next resume.
1445 *
1446 * Workaround:
1447 * Don't use smart standby; use only force standby,
1448 * hence HWMOD_SWSUP_MSTANDBY
1449 */
1450
1451 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1452 };
1453
1454 /*
1455 * 'usb_tll_hs' class
1456 * usb_tll_hs module is the adapter on the usb_host_hs ports
1457 */
1458 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1459 .rev_offs = 0x0000,
1460 .sysc_offs = 0x0010,
1461 .syss_offs = 0x0014,
1462 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1463 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1464 SYSC_HAS_AUTOIDLE),
1465 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1466 .sysc_fields = &omap_hwmod_sysc_type1,
1467 };
1468
1469 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1470 .name = "usb_tll_hs",
1471 .sysc = &omap3xxx_usb_tll_hs_sysc,
1472 };
1473
1474
1475 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1476 .name = "usb_tll_hs",
1477 .class = &omap3xxx_usb_tll_hs_hwmod_class,
1478 .clkdm_name = "core_l4_clkdm",
1479 .main_clk = "usbtll_fck",
1480 .prcm = {
1481 .omap2 = {
1482 .module_offs = CORE_MOD,
1483 .idlest_reg_id = 3,
1484 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1485 },
1486 },
1487 };
1488
1489 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1490 .name = "hdq1w",
1491 .main_clk = "hdq_fck",
1492 .prcm = {
1493 .omap2 = {
1494 .module_offs = CORE_MOD,
1495 .idlest_reg_id = 1,
1496 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1497 },
1498 },
1499 .class = &omap2_hdq1w_class,
1500 };
1501
1502 /* SAD2D */
1503 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1504 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1505 { .name = "rst_modem_sw", .rst_shift = 1 },
1506 };
1507
1508 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1509 .name = "sad2d",
1510 };
1511
1512 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1513 .name = "sad2d",
1514 .rst_lines = omap3xxx_sad2d_resets,
1515 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
1516 .main_clk = "sad2d_ick",
1517 .prcm = {
1518 .omap2 = {
1519 .module_offs = CORE_MOD,
1520 .idlest_reg_id = 1,
1521 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1522 },
1523 },
1524 .class = &omap3xxx_sad2d_class,
1525 };
1526
1527 /*
1528 * '32K sync counter' class
1529 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1530 */
1531 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1532 .rev_offs = 0x0000,
1533 .sysc_offs = 0x0004,
1534 .sysc_flags = SYSC_HAS_SIDLEMODE,
1535 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
1536 .sysc_fields = &omap_hwmod_sysc_type1,
1537 };
1538
1539 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1540 .name = "counter",
1541 .sysc = &omap3xxx_counter_sysc,
1542 };
1543
1544 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1545 .name = "counter_32k",
1546 .class = &omap3xxx_counter_hwmod_class,
1547 .clkdm_name = "wkup_clkdm",
1548 .flags = HWMOD_SWSUP_SIDLE,
1549 .main_clk = "wkup_32k_fck",
1550 .prcm = {
1551 .omap2 = {
1552 .module_offs = WKUP_MOD,
1553 .idlest_reg_id = 1,
1554 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1555 },
1556 },
1557 };
1558
1559 /*
1560 * 'gpmc' class
1561 * general purpose memory controller
1562 */
1563
1564 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1565 .rev_offs = 0x0000,
1566 .sysc_offs = 0x0010,
1567 .syss_offs = 0x0014,
1568 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1569 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1570 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1571 .sysc_fields = &omap_hwmod_sysc_type1,
1572 };
1573
1574 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1575 .name = "gpmc",
1576 .sysc = &omap3xxx_gpmc_sysc,
1577 };
1578
1579 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1580 .name = "gpmc",
1581 .class = &omap3xxx_gpmc_hwmod_class,
1582 .clkdm_name = "core_l3_clkdm",
1583 .main_clk = "gpmc_fck",
1584 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1585 .flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1586 };
1587
1588 /*
1589 * interfaces
1590 */
1591
1592 /* L3 -> L4_CORE interface */
1593 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1594 .master = &omap3xxx_l3_main_hwmod,
1595 .slave = &omap3xxx_l4_core_hwmod,
1596 .user = OCP_USER_MPU | OCP_USER_SDMA,
1597 };
1598
1599 /* L3 -> L4_PER interface */
1600 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1601 .master = &omap3xxx_l3_main_hwmod,
1602 .slave = &omap3xxx_l4_per_hwmod,
1603 .user = OCP_USER_MPU | OCP_USER_SDMA,
1604 };
1605
1606
1607 /* MPU -> L3 interface */
1608 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1609 .master = &omap3xxx_mpu_hwmod,
1610 .slave = &omap3xxx_l3_main_hwmod,
1611 .user = OCP_USER_MPU,
1612 };
1613
1614
1615 /* l3 -> debugss */
1616 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1617 .master = &omap3xxx_l3_main_hwmod,
1618 .slave = &omap3xxx_debugss_hwmod,
1619 .user = OCP_USER_MPU,
1620 };
1621
1622 /* DSS -> l3 */
1623 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1624 .master = &omap3430es1_dss_core_hwmod,
1625 .slave = &omap3xxx_l3_main_hwmod,
1626 .user = OCP_USER_MPU | OCP_USER_SDMA,
1627 };
1628
1629 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1630 .master = &omap3xxx_dss_core_hwmod,
1631 .slave = &omap3xxx_l3_main_hwmod,
1632 .fw = {
1633 .omap2 = {
1634 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1635 .flags = OMAP_FIREWALL_L3,
1636 },
1637 },
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639 };
1640
1641 /* l3_core -> usbhsotg interface */
1642 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1643 .master = &omap3xxx_usbhsotg_hwmod,
1644 .slave = &omap3xxx_l3_main_hwmod,
1645 .clk = "core_l3_ick",
1646 .user = OCP_USER_MPU,
1647 };
1648
1649 /* l3_core -> am35xx_usbhsotg interface */
1650 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1651 .master = &am35xx_usbhsotg_hwmod,
1652 .slave = &omap3xxx_l3_main_hwmod,
1653 .clk = "hsotgusb_ick",
1654 .user = OCP_USER_MPU,
1655 };
1656
1657 /* l3_core -> sad2d interface */
1658 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1659 .master = &omap3xxx_sad2d_hwmod,
1660 .slave = &omap3xxx_l3_main_hwmod,
1661 .clk = "core_l3_ick",
1662 .user = OCP_USER_MPU,
1663 };
1664
1665 /* L4_CORE -> L4_WKUP interface */
1666 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1667 .master = &omap3xxx_l4_core_hwmod,
1668 .slave = &omap3xxx_l4_wkup_hwmod,
1669 .user = OCP_USER_MPU | OCP_USER_SDMA,
1670 };
1671
1672 /* L4 CORE -> MMC1 interface */
1673 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1674 .master = &omap3xxx_l4_core_hwmod,
1675 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
1676 .clk = "mmchs1_ick",
1677 .user = OCP_USER_MPU | OCP_USER_SDMA,
1678 .flags = OMAP_FIREWALL_L4,
1679 };
1680
1681 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1682 .master = &omap3xxx_l4_core_hwmod,
1683 .slave = &omap3xxx_es3plus_mmc1_hwmod,
1684 .clk = "mmchs1_ick",
1685 .user = OCP_USER_MPU | OCP_USER_SDMA,
1686 .flags = OMAP_FIREWALL_L4,
1687 };
1688
1689 /* L4 CORE -> MMC2 interface */
1690 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1691 .master = &omap3xxx_l4_core_hwmod,
1692 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
1693 .clk = "mmchs2_ick",
1694 .user = OCP_USER_MPU | OCP_USER_SDMA,
1695 .flags = OMAP_FIREWALL_L4,
1696 };
1697
1698 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1699 .master = &omap3xxx_l4_core_hwmod,
1700 .slave = &omap3xxx_es3plus_mmc2_hwmod,
1701 .clk = "mmchs2_ick",
1702 .user = OCP_USER_MPU | OCP_USER_SDMA,
1703 .flags = OMAP_FIREWALL_L4,
1704 };
1705
1706 /* L4 CORE -> MMC3 interface */
1707
1708 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1709 .master = &omap3xxx_l4_core_hwmod,
1710 .slave = &omap3xxx_mmc3_hwmod,
1711 .clk = "mmchs3_ick",
1712 .user = OCP_USER_MPU | OCP_USER_SDMA,
1713 .flags = OMAP_FIREWALL_L4,
1714 };
1715
1716 /* L4 CORE -> UART1 interface */
1717
1718 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1719 .master = &omap3xxx_l4_core_hwmod,
1720 .slave = &omap3xxx_uart1_hwmod,
1721 .clk = "uart1_ick",
1722 .user = OCP_USER_MPU | OCP_USER_SDMA,
1723 };
1724
1725 /* L4 CORE -> UART2 interface */
1726
1727 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1728 .master = &omap3xxx_l4_core_hwmod,
1729 .slave = &omap3xxx_uart2_hwmod,
1730 .clk = "uart2_ick",
1731 .user = OCP_USER_MPU | OCP_USER_SDMA,
1732 };
1733
1734 /* L4 PER -> UART3 interface */
1735
1736 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1737 .master = &omap3xxx_l4_per_hwmod,
1738 .slave = &omap3xxx_uart3_hwmod,
1739 .clk = "uart3_ick",
1740 .user = OCP_USER_MPU | OCP_USER_SDMA,
1741 };
1742
1743 /* L4 PER -> UART4 interface */
1744
1745 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1746 .master = &omap3xxx_l4_per_hwmod,
1747 .slave = &omap36xx_uart4_hwmod,
1748 .clk = "uart4_ick",
1749 .user = OCP_USER_MPU | OCP_USER_SDMA,
1750 };
1751
1752 /* AM35xx: L4 CORE -> UART4 interface */
1753
1754 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1755 .master = &omap3xxx_l4_core_hwmod,
1756 .slave = &am35xx_uart4_hwmod,
1757 .clk = "uart4_ick",
1758 .user = OCP_USER_MPU | OCP_USER_SDMA,
1759 };
1760
1761 /* L4 CORE -> I2C1 interface */
1762 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1763 .master = &omap3xxx_l4_core_hwmod,
1764 .slave = &omap3xxx_i2c1_hwmod,
1765 .clk = "i2c1_ick",
1766 .fw = {
1767 .omap2 = {
1768 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
1769 .l4_prot_group = 7,
1770 .flags = OMAP_FIREWALL_L4,
1771 },
1772 },
1773 .user = OCP_USER_MPU | OCP_USER_SDMA,
1774 };
1775
1776 /* L4 CORE -> I2C2 interface */
1777 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1778 .master = &omap3xxx_l4_core_hwmod,
1779 .slave = &omap3xxx_i2c2_hwmod,
1780 .clk = "i2c2_ick",
1781 .fw = {
1782 .omap2 = {
1783 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
1784 .l4_prot_group = 7,
1785 .flags = OMAP_FIREWALL_L4,
1786 },
1787 },
1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
1789 };
1790
1791 /* L4 CORE -> I2C3 interface */
1792
1793 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1794 .master = &omap3xxx_l4_core_hwmod,
1795 .slave = &omap3xxx_i2c3_hwmod,
1796 .clk = "i2c3_ick",
1797 .fw = {
1798 .omap2 = {
1799 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
1800 .l4_prot_group = 7,
1801 .flags = OMAP_FIREWALL_L4,
1802 },
1803 },
1804 .user = OCP_USER_MPU | OCP_USER_SDMA,
1805 };
1806
1807 /* L4 CORE -> SR1 interface */
1808 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1809 .master = &omap3xxx_l4_core_hwmod,
1810 .slave = &omap34xx_sr1_hwmod,
1811 .clk = "sr_l4_ick",
1812 .user = OCP_USER_MPU,
1813 };
1814
1815 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1816 .master = &omap3xxx_l4_core_hwmod,
1817 .slave = &omap36xx_sr1_hwmod,
1818 .clk = "sr_l4_ick",
1819 .user = OCP_USER_MPU,
1820 };
1821
1822 /* L4 CORE -> SR2 interface */
1823
1824 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1825 .master = &omap3xxx_l4_core_hwmod,
1826 .slave = &omap34xx_sr2_hwmod,
1827 .clk = "sr_l4_ick",
1828 .user = OCP_USER_MPU,
1829 };
1830
1831 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1832 .master = &omap3xxx_l4_core_hwmod,
1833 .slave = &omap36xx_sr2_hwmod,
1834 .clk = "sr_l4_ick",
1835 .user = OCP_USER_MPU,
1836 };
1837
1838
1839 /* l4_core -> usbhsotg */
1840 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
1841 .master = &omap3xxx_l4_core_hwmod,
1842 .slave = &omap3xxx_usbhsotg_hwmod,
1843 .clk = "l4_ick",
1844 .user = OCP_USER_MPU,
1845 };
1846
1847
1848 /* l4_core -> usbhsotg */
1849 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
1850 .master = &omap3xxx_l4_core_hwmod,
1851 .slave = &am35xx_usbhsotg_hwmod,
1852 .clk = "hsotgusb_ick",
1853 .user = OCP_USER_MPU,
1854 };
1855
1856 /* L4_WKUP -> L4_SEC interface */
1857 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1858 .master = &omap3xxx_l4_wkup_hwmod,
1859 .slave = &omap3xxx_l4_sec_hwmod,
1860 .user = OCP_USER_MPU | OCP_USER_SDMA,
1861 };
1862
1863 /* IVA2 <- L3 interface */
1864 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1865 .master = &omap3xxx_l3_main_hwmod,
1866 .slave = &omap3xxx_iva_hwmod,
1867 .clk = "core_l3_ick",
1868 .user = OCP_USER_MPU | OCP_USER_SDMA,
1869 };
1870
1871
1872 /* l4_wkup -> timer1 */
1873 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
1874 .master = &omap3xxx_l4_wkup_hwmod,
1875 .slave = &omap3xxx_timer1_hwmod,
1876 .clk = "gpt1_ick",
1877 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878 };
1879
1880
1881 /* l4_per -> timer2 */
1882 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
1883 .master = &omap3xxx_l4_per_hwmod,
1884 .slave = &omap3xxx_timer2_hwmod,
1885 .clk = "gpt2_ick",
1886 .user = OCP_USER_MPU | OCP_USER_SDMA,
1887 };
1888
1889
1890 /* l4_per -> timer3 */
1891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1892 .master = &omap3xxx_l4_per_hwmod,
1893 .slave = &omap3xxx_timer3_hwmod,
1894 .clk = "gpt3_ick",
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1896 };
1897
1898
1899 /* l4_per -> timer4 */
1900 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1901 .master = &omap3xxx_l4_per_hwmod,
1902 .slave = &omap3xxx_timer4_hwmod,
1903 .clk = "gpt4_ick",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907
1908 /* l4_per -> timer5 */
1909 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1910 .master = &omap3xxx_l4_per_hwmod,
1911 .slave = &omap3xxx_timer5_hwmod,
1912 .clk = "gpt5_ick",
1913 .user = OCP_USER_MPU | OCP_USER_SDMA,
1914 };
1915
1916
1917 /* l4_per -> timer6 */
1918 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1919 .master = &omap3xxx_l4_per_hwmod,
1920 .slave = &omap3xxx_timer6_hwmod,
1921 .clk = "gpt6_ick",
1922 .user = OCP_USER_MPU | OCP_USER_SDMA,
1923 };
1924
1925
1926 /* l4_per -> timer7 */
1927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1928 .master = &omap3xxx_l4_per_hwmod,
1929 .slave = &omap3xxx_timer7_hwmod,
1930 .clk = "gpt7_ick",
1931 .user = OCP_USER_MPU | OCP_USER_SDMA,
1932 };
1933
1934
1935 /* l4_per -> timer8 */
1936 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1937 .master = &omap3xxx_l4_per_hwmod,
1938 .slave = &omap3xxx_timer8_hwmod,
1939 .clk = "gpt8_ick",
1940 .user = OCP_USER_MPU | OCP_USER_SDMA,
1941 };
1942
1943
1944 /* l4_per -> timer9 */
1945 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1946 .master = &omap3xxx_l4_per_hwmod,
1947 .slave = &omap3xxx_timer9_hwmod,
1948 .clk = "gpt9_ick",
1949 .user = OCP_USER_MPU | OCP_USER_SDMA,
1950 };
1951
1952 /* l4_core -> timer10 */
1953 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1954 .master = &omap3xxx_l4_core_hwmod,
1955 .slave = &omap3xxx_timer10_hwmod,
1956 .clk = "gpt10_ick",
1957 .user = OCP_USER_MPU | OCP_USER_SDMA,
1958 };
1959
1960 /* l4_core -> timer11 */
1961 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1962 .master = &omap3xxx_l4_core_hwmod,
1963 .slave = &omap3xxx_timer11_hwmod,
1964 .clk = "gpt11_ick",
1965 .user = OCP_USER_MPU | OCP_USER_SDMA,
1966 };
1967
1968
1969 /* l4_core -> timer12 */
1970 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
1971 .master = &omap3xxx_l4_sec_hwmod,
1972 .slave = &omap3xxx_timer12_hwmod,
1973 .clk = "gpt12_ick",
1974 .user = OCP_USER_MPU | OCP_USER_SDMA,
1975 };
1976
1977 /* l4_wkup -> wd_timer2 */
1978
1979 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1980 .master = &omap3xxx_l4_wkup_hwmod,
1981 .slave = &omap3xxx_wd_timer2_hwmod,
1982 .clk = "wdt2_ick",
1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
1984 };
1985
1986 /* l4_core -> dss */
1987 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1988 .master = &omap3xxx_l4_core_hwmod,
1989 .slave = &omap3430es1_dss_core_hwmod,
1990 .clk = "dss_ick",
1991 .fw = {
1992 .omap2 = {
1993 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1994 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1995 .flags = OMAP_FIREWALL_L4,
1996 },
1997 },
1998 .user = OCP_USER_MPU | OCP_USER_SDMA,
1999 };
2000
2001 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2002 .master = &omap3xxx_l4_core_hwmod,
2003 .slave = &omap3xxx_dss_core_hwmod,
2004 .clk = "dss_ick",
2005 .fw = {
2006 .omap2 = {
2007 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2008 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2009 .flags = OMAP_FIREWALL_L4,
2010 },
2011 },
2012 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013 };
2014
2015 /* l4_core -> dss_dispc */
2016 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2017 .master = &omap3xxx_l4_core_hwmod,
2018 .slave = &omap3xxx_dss_dispc_hwmod,
2019 .clk = "dss_ick",
2020 .fw = {
2021 .omap2 = {
2022 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2023 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2024 .flags = OMAP_FIREWALL_L4,
2025 },
2026 },
2027 .user = OCP_USER_MPU | OCP_USER_SDMA,
2028 };
2029
2030 /* l4_core -> dss_dsi1 */
2031 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2032 .master = &omap3xxx_l4_core_hwmod,
2033 .slave = &omap3xxx_dss_dsi1_hwmod,
2034 .clk = "dss_ick",
2035 .fw = {
2036 .omap2 = {
2037 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2038 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2039 .flags = OMAP_FIREWALL_L4,
2040 },
2041 },
2042 .user = OCP_USER_MPU | OCP_USER_SDMA,
2043 };
2044
2045 /* l4_core -> dss_rfbi */
2046 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2047 .master = &omap3xxx_l4_core_hwmod,
2048 .slave = &omap3xxx_dss_rfbi_hwmod,
2049 .clk = "dss_ick",
2050 .fw = {
2051 .omap2 = {
2052 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2053 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2054 .flags = OMAP_FIREWALL_L4,
2055 },
2056 },
2057 .user = OCP_USER_MPU | OCP_USER_SDMA,
2058 };
2059
2060 /* l4_core -> dss_venc */
2061 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2062 .master = &omap3xxx_l4_core_hwmod,
2063 .slave = &omap3xxx_dss_venc_hwmod,
2064 .clk = "dss_ick",
2065 .fw = {
2066 .omap2 = {
2067 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2068 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2069 .flags = OMAP_FIREWALL_L4,
2070 },
2071 },
2072 .flags = OCPIF_SWSUP_IDLE,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2074 };
2075
2076 /* l4_wkup -> gpio1 */
2077
2078 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2079 .master = &omap3xxx_l4_wkup_hwmod,
2080 .slave = &omap3xxx_gpio1_hwmod,
2081 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082 };
2083
2084 /* l4_per -> gpio2 */
2085
2086 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2087 .master = &omap3xxx_l4_per_hwmod,
2088 .slave = &omap3xxx_gpio2_hwmod,
2089 .user = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 /* l4_per -> gpio3 */
2093
2094 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2095 .master = &omap3xxx_l4_per_hwmod,
2096 .slave = &omap3xxx_gpio3_hwmod,
2097 .user = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2099
2100 /*
2101 * 'mmu' class
2102 * The memory management unit performs virtual to physical address translation
2103 * for its requestors.
2104 */
2105
2106 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2107 .rev_offs = 0x000,
2108 .sysc_offs = 0x010,
2109 .syss_offs = 0x014,
2110 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2111 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2112 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2113 .sysc_fields = &omap_hwmod_sysc_type1,
2114 };
2115
2116 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2117 .name = "mmu",
2118 .sysc = &mmu_sysc,
2119 };
2120
2121 /* mmu isp */
2122 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2123
2124 /* l4_core -> mmu isp */
2125 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2126 .master = &omap3xxx_l4_core_hwmod,
2127 .slave = &omap3xxx_mmu_isp_hwmod,
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129 };
2130
2131 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2132 .name = "mmu_isp",
2133 .class = &omap3xxx_mmu_hwmod_class,
2134 .main_clk = "cam_ick",
2135 .flags = HWMOD_NO_IDLEST,
2136 };
2137
2138 /* mmu iva */
2139
2140 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2141
2142 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2143 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2144 };
2145
2146 /* l3_main -> iva mmu */
2147 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2148 .master = &omap3xxx_l3_main_hwmod,
2149 .slave = &omap3xxx_mmu_iva_hwmod,
2150 .user = OCP_USER_MPU | OCP_USER_SDMA,
2151 };
2152
2153 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2154 .name = "mmu_iva",
2155 .class = &omap3xxx_mmu_hwmod_class,
2156 .clkdm_name = "iva2_clkdm",
2157 .rst_lines = omap3xxx_mmu_iva_resets,
2158 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2159 .main_clk = "iva2_ck",
2160 .prcm = {
2161 .omap2 = {
2162 .module_offs = OMAP3430_IVA2_MOD,
2163 .idlest_reg_id = 1,
2164 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2165 },
2166 },
2167 .flags = HWMOD_NO_IDLEST,
2168 };
2169
2170 /* l4_per -> gpio4 */
2171
2172 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2173 .master = &omap3xxx_l4_per_hwmod,
2174 .slave = &omap3xxx_gpio4_hwmod,
2175 .user = OCP_USER_MPU | OCP_USER_SDMA,
2176 };
2177
2178 /* l4_per -> gpio5 */
2179
2180 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2181 .master = &omap3xxx_l4_per_hwmod,
2182 .slave = &omap3xxx_gpio5_hwmod,
2183 .user = OCP_USER_MPU | OCP_USER_SDMA,
2184 };
2185
2186 /* l4_per -> gpio6 */
2187
2188 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2189 .master = &omap3xxx_l4_per_hwmod,
2190 .slave = &omap3xxx_gpio6_hwmod,
2191 .user = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* l4_core -> mcbsp1 */
2195 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2196 .master = &omap3xxx_l4_core_hwmod,
2197 .slave = &omap3xxx_mcbsp1_hwmod,
2198 .clk = "mcbsp1_ick",
2199 .user = OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201
2202
2203 /* l4_per -> mcbsp2 */
2204 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2205 .master = &omap3xxx_l4_per_hwmod,
2206 .slave = &omap3xxx_mcbsp2_hwmod,
2207 .clk = "mcbsp2_ick",
2208 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209 };
2210
2211
2212 /* l4_per -> mcbsp3 */
2213 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2214 .master = &omap3xxx_l4_per_hwmod,
2215 .slave = &omap3xxx_mcbsp3_hwmod,
2216 .clk = "mcbsp3_ick",
2217 .user = OCP_USER_MPU | OCP_USER_SDMA,
2218 };
2219
2220
2221 /* l4_per -> mcbsp4 */
2222 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2223 .master = &omap3xxx_l4_per_hwmod,
2224 .slave = &omap3xxx_mcbsp4_hwmod,
2225 .clk = "mcbsp4_ick",
2226 .user = OCP_USER_MPU | OCP_USER_SDMA,
2227 };
2228
2229
2230 /* l4_core -> mcbsp5 */
2231 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2232 .master = &omap3xxx_l4_core_hwmod,
2233 .slave = &omap3xxx_mcbsp5_hwmod,
2234 .clk = "mcbsp5_ick",
2235 .user = OCP_USER_MPU | OCP_USER_SDMA,
2236 };
2237
2238
2239 /* l4_per -> mcbsp2_sidetone */
2240 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2241 .master = &omap3xxx_l4_per_hwmod,
2242 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2243 .clk = "mcbsp2_ick",
2244 .user = OCP_USER_MPU,
2245 };
2246
2247
2248 /* l4_per -> mcbsp3_sidetone */
2249 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2250 .master = &omap3xxx_l4_per_hwmod,
2251 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2252 .clk = "mcbsp3_ick",
2253 .user = OCP_USER_MPU,
2254 };
2255
2256 /* l4_core -> mailbox */
2257 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2258 .master = &omap3xxx_l4_core_hwmod,
2259 .slave = &omap3xxx_mailbox_hwmod,
2260 .user = OCP_USER_MPU | OCP_USER_SDMA,
2261 };
2262
2263 /* l4 core -> mcspi1 interface */
2264 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2265 .master = &omap3xxx_l4_core_hwmod,
2266 .slave = &omap34xx_mcspi1,
2267 .clk = "mcspi1_ick",
2268 .user = OCP_USER_MPU | OCP_USER_SDMA,
2269 };
2270
2271 /* l4 core -> mcspi2 interface */
2272 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2273 .master = &omap3xxx_l4_core_hwmod,
2274 .slave = &omap34xx_mcspi2,
2275 .clk = "mcspi2_ick",
2276 .user = OCP_USER_MPU | OCP_USER_SDMA,
2277 };
2278
2279 /* l4 core -> mcspi3 interface */
2280 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2281 .master = &omap3xxx_l4_core_hwmod,
2282 .slave = &omap34xx_mcspi3,
2283 .clk = "mcspi3_ick",
2284 .user = OCP_USER_MPU | OCP_USER_SDMA,
2285 };
2286
2287 /* l4 core -> mcspi4 interface */
2288
2289 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2290 .master = &omap3xxx_l4_core_hwmod,
2291 .slave = &omap34xx_mcspi4,
2292 .clk = "mcspi4_ick",
2293 .user = OCP_USER_MPU | OCP_USER_SDMA,
2294 };
2295
2296 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2297 .master = &omap3xxx_usb_host_hs_hwmod,
2298 .slave = &omap3xxx_l3_main_hwmod,
2299 .clk = "core_l3_ick",
2300 .user = OCP_USER_MPU,
2301 };
2302
2303
2304 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2305 .master = &omap3xxx_l4_core_hwmod,
2306 .slave = &omap3xxx_usb_host_hs_hwmod,
2307 .clk = "usbhost_ick",
2308 .user = OCP_USER_MPU | OCP_USER_SDMA,
2309 };
2310
2311
2312 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2313 .master = &omap3xxx_l4_core_hwmod,
2314 .slave = &omap3xxx_usb_tll_hs_hwmod,
2315 .clk = "usbtll_ick",
2316 .user = OCP_USER_MPU | OCP_USER_SDMA,
2317 };
2318
2319 /* l4_core -> hdq1w interface */
2320 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2321 .master = &omap3xxx_l4_core_hwmod,
2322 .slave = &omap3xxx_hdq1w_hwmod,
2323 .clk = "hdq_ick",
2324 .user = OCP_USER_MPU | OCP_USER_SDMA,
2325 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2326 };
2327
2328 /* l4_wkup -> 32ksync_counter */
2329
2330
2331 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2332 .master = &omap3xxx_l4_wkup_hwmod,
2333 .slave = &omap3xxx_counter_32k_hwmod,
2334 .clk = "omap_32ksync_ick",
2335 .user = OCP_USER_MPU | OCP_USER_SDMA,
2336 };
2337
2338 /* am35xx has Davinci MDIO & EMAC */
2339 static struct omap_hwmod_class am35xx_mdio_class = {
2340 .name = "davinci_mdio",
2341 };
2342
2343 static struct omap_hwmod am35xx_mdio_hwmod = {
2344 .name = "davinci_mdio",
2345 .class = &am35xx_mdio_class,
2346 .flags = HWMOD_NO_IDLEST,
2347 };
2348
2349 /*
2350 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2351 * but this will probably require some additional hwmod core support,
2352 * so is left as a future to-do item.
2353 */
2354 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2355 .master = &am35xx_mdio_hwmod,
2356 .slave = &omap3xxx_l3_main_hwmod,
2357 .clk = "emac_fck",
2358 .user = OCP_USER_MPU,
2359 };
2360
2361 /* l4_core -> davinci mdio */
2362 /*
2363 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2364 * but this will probably require some additional hwmod core support,
2365 * so is left as a future to-do item.
2366 */
2367 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2368 .master = &omap3xxx_l4_core_hwmod,
2369 .slave = &am35xx_mdio_hwmod,
2370 .clk = "emac_fck",
2371 .user = OCP_USER_MPU,
2372 };
2373
2374 static struct omap_hwmod_class am35xx_emac_class = {
2375 .name = "davinci_emac",
2376 };
2377
2378 static struct omap_hwmod am35xx_emac_hwmod = {
2379 .name = "davinci_emac",
2380 .class = &am35xx_emac_class,
2381 /*
2382 * According to Mark Greer, the MPU will not return from WFI
2383 * when the EMAC signals an interrupt.
2384 * http://www.spinics.net/lists/arm-kernel/msg174734.html
2385 */
2386 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2387 };
2388
2389 /* l3_core -> davinci emac interface */
2390 /*
2391 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2392 * but this will probably require some additional hwmod core support,
2393 * so is left as a future to-do item.
2394 */
2395 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2396 .master = &am35xx_emac_hwmod,
2397 .slave = &omap3xxx_l3_main_hwmod,
2398 .clk = "emac_ick",
2399 .user = OCP_USER_MPU,
2400 };
2401
2402 /* l4_core -> davinci emac */
2403 /*
2404 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2405 * but this will probably require some additional hwmod core support,
2406 * so is left as a future to-do item.
2407 */
2408 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2409 .master = &omap3xxx_l4_core_hwmod,
2410 .slave = &am35xx_emac_hwmod,
2411 .clk = "emac_ick",
2412 .user = OCP_USER_MPU,
2413 };
2414
2415 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2416 .master = &omap3xxx_l3_main_hwmod,
2417 .slave = &omap3xxx_gpmc_hwmod,
2418 .clk = "core_l3_ick",
2419 .user = OCP_USER_MPU | OCP_USER_SDMA,
2420 };
2421
2422 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2423 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2424 .rev_offs = 0x5c,
2425 .sysc_offs = 0x60,
2426 .syss_offs = 0x64,
2427 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2428 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2429 .sysc_fields = &omap3_sham_sysc_fields,
2430 };
2431
2432 static struct omap_hwmod_class omap3xxx_sham_class = {
2433 .name = "sham",
2434 .sysc = &omap3_sham_sysc,
2435 };
2436
2437
2438
2439 static struct omap_hwmod omap3xxx_sham_hwmod = {
2440 .name = "sham",
2441 .main_clk = "sha12_ick",
2442 .prcm = {
2443 .omap2 = {
2444 .module_offs = CORE_MOD,
2445 .idlest_reg_id = 1,
2446 .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2447 },
2448 },
2449 .class = &omap3xxx_sham_class,
2450 };
2451
2452
2453 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2454 .master = &omap3xxx_l4_core_hwmod,
2455 .slave = &omap3xxx_sham_hwmod,
2456 .clk = "sha12_ick",
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2458 };
2459
2460 /* l4_core -> AES */
2461 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2462 .rev_offs = 0x44,
2463 .sysc_offs = 0x48,
2464 .syss_offs = 0x4c,
2465 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2466 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2467 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2468 .sysc_fields = &omap3xxx_aes_sysc_fields,
2469 };
2470
2471 static struct omap_hwmod_class omap3xxx_aes_class = {
2472 .name = "aes",
2473 .sysc = &omap3_aes_sysc,
2474 };
2475
2476
2477 static struct omap_hwmod omap3xxx_aes_hwmod = {
2478 .name = "aes",
2479 .main_clk = "aes2_ick",
2480 .prcm = {
2481 .omap2 = {
2482 .module_offs = CORE_MOD,
2483 .idlest_reg_id = 1,
2484 .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2485 },
2486 },
2487 .class = &omap3xxx_aes_class,
2488 };
2489
2490
2491 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2492 .master = &omap3xxx_l4_core_hwmod,
2493 .slave = &omap3xxx_aes_hwmod,
2494 .clk = "aes2_ick",
2495 .user = OCP_USER_MPU | OCP_USER_SDMA,
2496 };
2497
2498 /*
2499 * 'ssi' class
2500 * synchronous serial interface (multichannel and full-duplex serial if)
2501 */
2502
2503 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2504 .rev_offs = 0x0000,
2505 .sysc_offs = 0x0010,
2506 .syss_offs = 0x0014,
2507 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2508 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2509 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2510 .sysc_fields = &omap_hwmod_sysc_type1,
2511 };
2512
2513 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2514 .name = "ssi",
2515 .sysc = &omap34xx_ssi_sysc,
2516 };
2517
2518 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2519 .name = "ssi",
2520 .class = &omap3xxx_ssi_hwmod_class,
2521 .clkdm_name = "core_l4_clkdm",
2522 .main_clk = "ssi_ssr_fck",
2523 .prcm = {
2524 .omap2 = {
2525 .module_offs = CORE_MOD,
2526 .idlest_reg_id = 1,
2527 .idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2528 },
2529 },
2530 };
2531
2532 /* L4 CORE -> SSI */
2533 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2534 .master = &omap3xxx_l4_core_hwmod,
2535 .slave = &omap3xxx_ssi_hwmod,
2536 .clk = "ssi_ick",
2537 .user = OCP_USER_MPU | OCP_USER_SDMA,
2538 };
2539
2540 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2541 &omap3xxx_l3_main__l4_core,
2542 &omap3xxx_l3_main__l4_per,
2543 &omap3xxx_mpu__l3_main,
2544 &omap3xxx_l3_main__l4_debugss,
2545 &omap3xxx_l4_core__l4_wkup,
2546 &omap3xxx_l4_core__mmc3,
2547 &omap3_l4_core__uart1,
2548 &omap3_l4_core__uart2,
2549 &omap3_l4_per__uart3,
2550 &omap3_l4_core__i2c1,
2551 &omap3_l4_core__i2c2,
2552 &omap3_l4_core__i2c3,
2553 &omap3xxx_l4_wkup__l4_sec,
2554 &omap3xxx_l4_wkup__timer1,
2555 &omap3xxx_l4_per__timer2,
2556 &omap3xxx_l4_per__timer3,
2557 &omap3xxx_l4_per__timer4,
2558 &omap3xxx_l4_per__timer5,
2559 &omap3xxx_l4_per__timer6,
2560 &omap3xxx_l4_per__timer7,
2561 &omap3xxx_l4_per__timer8,
2562 &omap3xxx_l4_per__timer9,
2563 &omap3xxx_l4_core__timer10,
2564 &omap3xxx_l4_core__timer11,
2565 &omap3xxx_l4_wkup__wd_timer2,
2566 &omap3xxx_l4_wkup__gpio1,
2567 &omap3xxx_l4_per__gpio2,
2568 &omap3xxx_l4_per__gpio3,
2569 &omap3xxx_l4_per__gpio4,
2570 &omap3xxx_l4_per__gpio5,
2571 &omap3xxx_l4_per__gpio6,
2572 &omap3xxx_l4_core__mcbsp1,
2573 &omap3xxx_l4_per__mcbsp2,
2574 &omap3xxx_l4_per__mcbsp3,
2575 &omap3xxx_l4_per__mcbsp4,
2576 &omap3xxx_l4_core__mcbsp5,
2577 &omap3xxx_l4_per__mcbsp2_sidetone,
2578 &omap3xxx_l4_per__mcbsp3_sidetone,
2579 &omap34xx_l4_core__mcspi1,
2580 &omap34xx_l4_core__mcspi2,
2581 &omap34xx_l4_core__mcspi3,
2582 &omap34xx_l4_core__mcspi4,
2583 &omap3xxx_l4_wkup__counter_32k,
2584 &omap3xxx_l3_main__gpmc,
2585 NULL,
2586 };
2587
2588 /* GP-only hwmod links */
2589 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2590 &omap3xxx_l4_sec__timer12,
2591 NULL,
2592 };
2593
2594 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2595 &omap3xxx_l4_sec__timer12,
2596 NULL,
2597 };
2598
2599 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2600 &omap3xxx_l4_sec__timer12,
2601 NULL,
2602 };
2603
2604 /* crypto hwmod links */
2605 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2606 &omap3xxx_l4_core__sham,
2607 NULL,
2608 };
2609
2610 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2611 &omap3xxx_l4_core__aes,
2612 NULL,
2613 };
2614
2615 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2616 &omap3xxx_l4_core__sham,
2617 NULL
2618 };
2619
2620 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2621 &omap3xxx_l4_core__aes,
2622 NULL
2623 };
2624
2625 /*
2626 * Apparently the SHA/MD5 and AES accelerator IP blocks are
2627 * only present on some AM35xx chips, and no one knows which
2628 * ones. See
2629 * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2630 * if you need these IP blocks on an AM35xx, try uncommenting
2631 * the following lines.
2632 */
2633 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2634 /* &omap3xxx_l4_core__sham, */
2635 NULL
2636 };
2637
2638 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2639 /* &omap3xxx_l4_core__aes, */
2640 NULL,
2641 };
2642
2643 /* 3430ES1-only hwmod links */
2644 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2645 &omap3430es1_dss__l3,
2646 &omap3430es1_l4_core__dss,
2647 NULL,
2648 };
2649
2650 /* 3430ES2+-only hwmod links */
2651 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2652 &omap3xxx_dss__l3,
2653 &omap3xxx_l4_core__dss,
2654 &omap3xxx_usbhsotg__l3,
2655 &omap3xxx_l4_core__usbhsotg,
2656 &omap3xxx_usb_host_hs__l3_main_2,
2657 &omap3xxx_l4_core__usb_host_hs,
2658 &omap3xxx_l4_core__usb_tll_hs,
2659 NULL,
2660 };
2661
2662 /* <= 3430ES3-only hwmod links */
2663 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2664 &omap3xxx_l4_core__pre_es3_mmc1,
2665 &omap3xxx_l4_core__pre_es3_mmc2,
2666 NULL,
2667 };
2668
2669 /* 3430ES3+-only hwmod links */
2670 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2671 &omap3xxx_l4_core__es3plus_mmc1,
2672 &omap3xxx_l4_core__es3plus_mmc2,
2673 NULL,
2674 };
2675
2676 /* 34xx-only hwmod links (all ES revisions) */
2677 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2678 &omap3xxx_l3__iva,
2679 &omap34xx_l4_core__sr1,
2680 &omap34xx_l4_core__sr2,
2681 &omap3xxx_l4_core__mailbox,
2682 &omap3xxx_l4_core__hdq1w,
2683 &omap3xxx_sad2d__l3,
2684 &omap3xxx_l4_core__mmu_isp,
2685 &omap3xxx_l3_main__mmu_iva,
2686 &omap3xxx_l4_core__ssi,
2687 NULL,
2688 };
2689
2690 /* 36xx-only hwmod links (all ES revisions) */
2691 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2692 &omap3xxx_l3__iva,
2693 &omap36xx_l4_per__uart4,
2694 &omap3xxx_dss__l3,
2695 &omap3xxx_l4_core__dss,
2696 &omap36xx_l4_core__sr1,
2697 &omap36xx_l4_core__sr2,
2698 &omap3xxx_usbhsotg__l3,
2699 &omap3xxx_l4_core__usbhsotg,
2700 &omap3xxx_l4_core__mailbox,
2701 &omap3xxx_usb_host_hs__l3_main_2,
2702 &omap3xxx_l4_core__usb_host_hs,
2703 &omap3xxx_l4_core__usb_tll_hs,
2704 &omap3xxx_l4_core__es3plus_mmc1,
2705 &omap3xxx_l4_core__es3plus_mmc2,
2706 &omap3xxx_l4_core__hdq1w,
2707 &omap3xxx_sad2d__l3,
2708 &omap3xxx_l4_core__mmu_isp,
2709 &omap3xxx_l3_main__mmu_iva,
2710 &omap3xxx_l4_core__ssi,
2711 NULL,
2712 };
2713
2714 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2715 &omap3xxx_dss__l3,
2716 &omap3xxx_l4_core__dss,
2717 &am35xx_usbhsotg__l3,
2718 &am35xx_l4_core__usbhsotg,
2719 &am35xx_l4_core__uart4,
2720 &omap3xxx_usb_host_hs__l3_main_2,
2721 &omap3xxx_l4_core__usb_host_hs,
2722 &omap3xxx_l4_core__usb_tll_hs,
2723 &omap3xxx_l4_core__es3plus_mmc1,
2724 &omap3xxx_l4_core__es3plus_mmc2,
2725 &omap3xxx_l4_core__hdq1w,
2726 &am35xx_mdio__l3,
2727 &am35xx_l4_core__mdio,
2728 &am35xx_emac__l3,
2729 &am35xx_l4_core__emac,
2730 NULL,
2731 };
2732
2733 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2734 &omap3xxx_l4_core__dss_dispc,
2735 &omap3xxx_l4_core__dss_dsi1,
2736 &omap3xxx_l4_core__dss_rfbi,
2737 &omap3xxx_l4_core__dss_venc,
2738 NULL,
2739 };
2740
2741 /**
2742 * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2743 * @bus: struct device_node * for the top-level OMAP DT data
2744 * @dev_name: device name used in the DT file
2745 *
2746 * Determine whether a "secure" IP block @dev_name is usable by Linux.
2747 * There doesn't appear to be a 100% reliable way to determine this,
2748 * so we rely on heuristics. If @bus is null, meaning there's no DT
2749 * data, then we only assume the IP block is accessible if the OMAP is
2750 * fused as a 'general-purpose' SoC. If however DT data is present,
2751 * test to see if the IP block is described in the DT data and set to
2752 * 'status = "okay"'. If so then we assume the ODM has configured the
2753 * OMAP firewalls to allow access to the IP block.
2754 *
2755 * Return: 0 if device named @dev_name is not likely to be accessible,
2756 * or 1 if it is likely to be accessible.
2757 */
2758 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2759 const char *dev_name)
2760 {
2761 struct device_node *node;
2762 bool available;
2763
2764 if (!bus)
2765 return omap_type() == OMAP2_DEVICE_TYPE_GP;
2766
2767 node = of_get_child_by_name(bus, dev_name);
2768 available = of_device_is_available(node);
2769 of_node_put(node);
2770
2771 return available;
2772 }
2773
2774 int __init omap3xxx_hwmod_init(void)
2775 {
2776 int r;
2777 struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2778 struct omap_hwmod_ocp_if **h_aes = NULL;
2779 struct device_node *bus;
2780 unsigned int rev;
2781
2782 omap_hwmod_init();
2783
2784 /* Register hwmod links common to all OMAP3 */
2785 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2786 if (r < 0)
2787 return r;
2788
2789 rev = omap_rev();
2790
2791 /*
2792 * Register hwmod links common to individual OMAP3 families, all
2793 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2794 * All possible revisions should be included in this conditional.
2795 */
2796 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2797 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2798 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2799 h = omap34xx_hwmod_ocp_ifs;
2800 h_gp = omap34xx_gp_hwmod_ocp_ifs;
2801 h_sham = omap34xx_sham_hwmod_ocp_ifs;
2802 h_aes = omap34xx_aes_hwmod_ocp_ifs;
2803 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2804 h = am35xx_hwmod_ocp_ifs;
2805 h_gp = am35xx_gp_hwmod_ocp_ifs;
2806 h_sham = am35xx_sham_hwmod_ocp_ifs;
2807 h_aes = am35xx_aes_hwmod_ocp_ifs;
2808 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2809 rev == OMAP3630_REV_ES1_2) {
2810 h = omap36xx_hwmod_ocp_ifs;
2811 h_gp = omap36xx_gp_hwmod_ocp_ifs;
2812 h_sham = omap36xx_sham_hwmod_ocp_ifs;
2813 h_aes = omap36xx_aes_hwmod_ocp_ifs;
2814 } else {
2815 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2816 return -EINVAL;
2817 }
2818
2819 r = omap_hwmod_register_links(h);
2820 if (r < 0)
2821 return r;
2822
2823 /* Register GP-only hwmod links. */
2824 if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
2825 r = omap_hwmod_register_links(h_gp);
2826 if (r < 0)
2827 return r;
2828 }
2829
2830 /*
2831 * Register crypto hwmod links only if they are not disabled in DT.
2832 * If DT information is missing, enable them only for GP devices.
2833 */
2834
2835 bus = of_find_node_by_name(NULL, "ocp");
2836
2837 if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2838 r = omap_hwmod_register_links(h_sham);
2839 if (r < 0)
2840 goto put_node;
2841 }
2842
2843 if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2844 r = omap_hwmod_register_links(h_aes);
2845 if (r < 0)
2846 goto put_node;
2847 }
2848 of_node_put(bus);
2849
2850 /*
2851 * Register hwmod links specific to certain ES levels of a
2852 * particular family of silicon (e.g., 34xx ES1.0)
2853 */
2854 h = NULL;
2855 if (rev == OMAP3430_REV_ES1_0) {
2856 h = omap3430es1_hwmod_ocp_ifs;
2857 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2858 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2859 rev == OMAP3430_REV_ES3_1_2) {
2860 h = omap3430es2plus_hwmod_ocp_ifs;
2861 }
2862
2863 if (h) {
2864 r = omap_hwmod_register_links(h);
2865 if (r < 0)
2866 return r;
2867 }
2868
2869 h = NULL;
2870 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2871 rev == OMAP3430_REV_ES2_1) {
2872 h = omap3430_pre_es3_hwmod_ocp_ifs;
2873 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2874 rev == OMAP3430_REV_ES3_1_2) {
2875 h = omap3430_es3plus_hwmod_ocp_ifs;
2876 }
2877
2878 if (h)
2879 r = omap_hwmod_register_links(h);
2880 if (r < 0)
2881 return r;
2882
2883 /*
2884 * DSS code presumes that dss_core hwmod is handled first,
2885 * _before_ any other DSS related hwmods so register common
2886 * DSS hwmod links last to ensure that dss_core is already
2887 * registered. Otherwise some change things may happen, for
2888 * ex. if dispc is handled before dss_core and DSS is enabled
2889 * in bootloader DISPC will be reset with outputs enabled
2890 * which sometimes leads to unrecoverable L3 error. XXX The
2891 * long-term fix to this is to ensure hwmods are set up in
2892 * dependency order in the hwmod core code.
2893 */
2894 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2895
2896 return r;
2897
2898 put_node:
2899 of_node_put(bus);
2900 return r;
2901 }
Linux with added FPC-III support