arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_44xx.h"
  25 #include "cm2_44xx.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28
  29 /* Base offset for all OMAP4 interrupts external to MPUSS */
  30 #define OMAP44XX_IRQ_GIC_START  32
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'dmm' class
  38  * instance(s): dmm
  39  */
  40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  41         .name   = "dmm",
  42 };
  43
  44 /* dmm */
  45 static struct omap_hwmod omap44xx_dmm_hwmod = {
  46         .name           = "dmm",
  47         .class          = &omap44xx_dmm_hwmod_class,
  48         .clkdm_name     = "l3_emif_clkdm",
  49         .prcm = {
  50                 .omap4 = {
  51                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  52                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  53                 },
  54         },
  55 };
  56
  57 /*
  58  * 'l3' class
  59  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  60  */
  61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  62         .name   = "l3",
  63 };
  64
  65 /* l3_instr */
  66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  67         .name           = "l3_instr",
  68         .class          = &omap44xx_l3_hwmod_class,
  69         .clkdm_name     = "l3_instr_clkdm",
  70         .prcm = {
  71                 .omap4 = {
  72                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  73                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  74                         .modulemode   = MODULEMODE_HWCTRL,
  75                 },
  76         },
  77 };
  78
  79 /* l3_main_1 */
  80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  81         .name           = "l3_main_1",
  82         .class          = &omap44xx_l3_hwmod_class,
  83         .clkdm_name     = "l3_1_clkdm",
  84         .prcm = {
  85                 .omap4 = {
  86                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  87                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  88                 },
  89         },
  90 };
  91
  92 /* l3_main_2 */
  93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  94         .name           = "l3_main_2",
  95         .class          = &omap44xx_l3_hwmod_class,
  96         .clkdm_name     = "l3_2_clkdm",
  97         .prcm = {
  98                 .omap4 = {
  99                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 100                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 101                 },
 102         },
 103 };
 104
 105 /* l3_main_3 */
 106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 107         .name           = "l3_main_3",
 108         .class          = &omap44xx_l3_hwmod_class,
 109         .clkdm_name     = "l3_instr_clkdm",
 110         .prcm = {
 111                 .omap4 = {
 112                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 113                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 114                         .modulemode   = MODULEMODE_HWCTRL,
 115                 },
 116         },
 117 };
 118
 119 /*
 120  * 'l4' class
 121  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 122  */
 123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 124         .name   = "l4",
 125 };
 126
 127 /* l4_abe */
 128 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 129         .name           = "l4_abe",
 130         .class          = &omap44xx_l4_hwmod_class,
 131         .clkdm_name     = "abe_clkdm",
 132         .prcm = {
 133                 .omap4 = {
 134                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 135                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 136                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 137                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 138                 },
 139         },
 140 };
 141
 142 /* l4_cfg */
 143 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 144         .name           = "l4_cfg",
 145         .class          = &omap44xx_l4_hwmod_class,
 146         .clkdm_name     = "l4_cfg_clkdm",
 147         .prcm = {
 148                 .omap4 = {
 149                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 150                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 151                 },
 152         },
 153 };
 154
 155 /* l4_per */
 156 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 157         .name           = "l4_per",
 158         .class          = &omap44xx_l4_hwmod_class,
 159         .clkdm_name     = "l4_per_clkdm",
 160         .prcm = {
 161                 .omap4 = {
 162                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 163                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 164                 },
 165         },
 166 };
 167
 168 /* l4_wkup */
 169 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 170         .name           = "l4_wkup",
 171         .class          = &omap44xx_l4_hwmod_class,
 172         .clkdm_name     = "l4_wkup_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /*
 182  * 'mpu_bus' class
 183  * instance(s): mpu_private
 184  */
 185 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 186         .name   = "mpu_bus",
 187 };
 188
 189 /* mpu_private */
 190 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 191         .name           = "mpu_private",
 192         .class          = &omap44xx_mpu_bus_hwmod_class,
 193         .clkdm_name     = "mpuss_clkdm",
 194         .prcm = {
 195                 .omap4 = {
 196                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 197                 },
 198         },
 199 };
 200
 201 /*
 202  * 'ocp_wp_noc' class
 203  * instance(s): ocp_wp_noc
 204  */
 205 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 206         .name   = "ocp_wp_noc",
 207 };
 208
 209 /* ocp_wp_noc */
 210 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 211         .name           = "ocp_wp_noc",
 212         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 213         .clkdm_name     = "l3_instr_clkdm",
 214         .prcm = {
 215                 .omap4 = {
 216                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 217                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 218                         .modulemode   = MODULEMODE_HWCTRL,
 219                 },
 220         },
 221 };
 222
 223 /*
 224  * Modules omap_hwmod structures
 225  *
 226  * The following IPs are excluded for the moment because:
 227  * - They do not need an explicit SW control using omap_hwmod API.
 228  * - They still need to be validated with the driver
 229  *   properly adapted to omap_hwmod / omap_device
 230  *
 231  * usim
 232  */
 233
 234 /*
 235  * 'counter' class
 236  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 237  */
 238
 239 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 240         .rev_offs       = 0x0000,
 241         .sysc_offs      = 0x0004,
 242         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 243         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 244         .sysc_fields    = &omap_hwmod_sysc_type1,
 245 };
 246
 247 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 248         .name   = "counter",
 249         .sysc   = &omap44xx_counter_sysc,
 250 };
 251
 252 /* counter_32k */
 253 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 254         .name           = "counter_32k",
 255         .class          = &omap44xx_counter_hwmod_class,
 256         .clkdm_name     = "l4_wkup_clkdm",
 257         .flags          = HWMOD_SWSUP_SIDLE,
 258         .main_clk       = "sys_32k_ck",
 259         .prcm = {
 260                 .omap4 = {
 261                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 262                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 263                 },
 264         },
 265 };
 266
 267 /*
 268  * 'ctrl_module' class
 269  * attila core control module + core pad control module + wkup pad control
 270  * module + attila wkup control module
 271  */
 272
 273 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 274         .rev_offs       = 0x0000,
 275         .sysc_offs      = 0x0010,
 276         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 277         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 278                            SIDLE_SMART_WKUP),
 279         .sysc_fields    = &omap_hwmod_sysc_type2,
 280 };
 281
 282 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 283         .name   = "ctrl_module",
 284         .sysc   = &omap44xx_ctrl_module_sysc,
 285 };
 286
 287 /* ctrl_module_core */
 288 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 289         .name           = "ctrl_module_core",
 290         .class          = &omap44xx_ctrl_module_hwmod_class,
 291         .clkdm_name     = "l4_cfg_clkdm",
 292         .prcm = {
 293                 .omap4 = {
 294                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 295                 },
 296         },
 297 };
 298
 299 /* ctrl_module_pad_core */
 300 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 301         .name           = "ctrl_module_pad_core",
 302         .class          = &omap44xx_ctrl_module_hwmod_class,
 303         .clkdm_name     = "l4_cfg_clkdm",
 304         .prcm = {
 305                 .omap4 = {
 306                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 307                 },
 308         },
 309 };
 310
 311 /* ctrl_module_wkup */
 312 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 313         .name           = "ctrl_module_wkup",
 314         .class          = &omap44xx_ctrl_module_hwmod_class,
 315         .clkdm_name     = "l4_wkup_clkdm",
 316         .prcm = {
 317                 .omap4 = {
 318                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 319                 },
 320         },
 321 };
 322
 323 /* ctrl_module_pad_wkup */
 324 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 325         .name           = "ctrl_module_pad_wkup",
 326         .class          = &omap44xx_ctrl_module_hwmod_class,
 327         .clkdm_name     = "l4_wkup_clkdm",
 328         .prcm = {
 329                 .omap4 = {
 330                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 331                 },
 332         },
 333 };
 334
 335 /*
 336  * 'debugss' class
 337  * debug and emulation sub system
 338  */
 339
 340 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 341         .name   = "debugss",
 342 };
 343
 344 /* debugss */
 345 static struct omap_hwmod omap44xx_debugss_hwmod = {
 346         .name           = "debugss",
 347         .class          = &omap44xx_debugss_hwmod_class,
 348         .clkdm_name     = "emu_sys_clkdm",
 349         .main_clk       = "trace_clk_div_ck",
 350         .prcm = {
 351                 .omap4 = {
 352                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 353                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 354                 },
 355         },
 356 };
 357
 358 /*
 359  * 'emif' class
 360  * external memory interface no1
 361  */
 362
 363 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 364         .rev_offs       = 0x0000,
 365 };
 366
 367 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 368         .name   = "emif",
 369         .sysc   = &omap44xx_emif_sysc,
 370 };
 371
 372 /* emif1 */
 373 static struct omap_hwmod omap44xx_emif1_hwmod = {
 374         .name           = "emif1",
 375         .class          = &omap44xx_emif_hwmod_class,
 376         .clkdm_name     = "l3_emif_clkdm",
 377         .flags          = HWMOD_INIT_NO_IDLE,
 378         .main_clk       = "ddrphy_ck",
 379         .prcm = {
 380                 .omap4 = {
 381                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 382                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 383                         .modulemode   = MODULEMODE_HWCTRL,
 384                 },
 385         },
 386 };
 387
 388 /* emif2 */
 389 static struct omap_hwmod omap44xx_emif2_hwmod = {
 390         .name           = "emif2",
 391         .class          = &omap44xx_emif_hwmod_class,
 392         .clkdm_name     = "l3_emif_clkdm",
 393         .flags          = HWMOD_INIT_NO_IDLE,
 394         .main_clk       = "ddrphy_ck",
 395         .prcm = {
 396                 .omap4 = {
 397                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 398                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 399                         .modulemode   = MODULEMODE_HWCTRL,
 400                 },
 401         },
 402 };
 403
 404 /*
 405  * 'gpmc' class
 406  * general purpose memory controller
 407  */
 408
 409 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
 410         .rev_offs       = 0x0000,
 411         .sysc_offs      = 0x0010,
 412         .syss_offs      = 0x0014,
 413         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 414                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 416         .sysc_fields    = &omap_hwmod_sysc_type1,
 417 };
 418
 419 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 420         .name   = "gpmc",
 421         .sysc   = &omap44xx_gpmc_sysc,
 422 };
 423
 424 /* gpmc */
 425 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 426         .name           = "gpmc",
 427         .class          = &omap44xx_gpmc_hwmod_class,
 428         .clkdm_name     = "l3_2_clkdm",
 429         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 430         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 431         .prcm = {
 432                 .omap4 = {
 433                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
 434                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
 435                         .modulemode   = MODULEMODE_HWCTRL,
 436                 },
 437         },
 438 };
 439
 440 /*
 441  * 'iss' class
 442  * external images sensor pixel data processor
 443  */
 444
 445 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
 446         .rev_offs       = 0x0000,
 447         .sysc_offs      = 0x0010,
 448         /*
 449          * ISS needs 100 OCP clk cycles delay after a softreset before
 450          * accessing sysconfig again.
 451          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 452          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 453          *
 454          * TODO: Indicate errata when available.
 455          */
 456         .srst_udelay    = 2,
 457         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 458                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 459         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 460                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 461                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 462         .sysc_fields    = &omap_hwmod_sysc_type2,
 463 };
 464
 465 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 466         .name   = "iss",
 467         .sysc   = &omap44xx_iss_sysc,
 468 };
 469
 470 /* iss */
 471 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
 472         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 473 };
 474
 475 static struct omap_hwmod omap44xx_iss_hwmod = {
 476         .name           = "iss",
 477         .class          = &omap44xx_iss_hwmod_class,
 478         .clkdm_name     = "iss_clkdm",
 479         .main_clk       = "ducati_clk_mux_ck",
 480         .prcm = {
 481                 .omap4 = {
 482                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
 483                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
 484                         .modulemode   = MODULEMODE_SWCTRL,
 485                 },
 486         },
 487         .opt_clks       = iss_opt_clks,
 488         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
 489 };
 490
 491 /*
 492  * 'iva' class
 493  * multi-standard video encoder/decoder hardware accelerator
 494  */
 495
 496 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 497         .name   = "iva",
 498 };
 499
 500 /* iva */
 501 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
 502         { .name = "seq0", .rst_shift = 0 },
 503         { .name = "seq1", .rst_shift = 1 },
 504         { .name = "logic", .rst_shift = 2 },
 505 };
 506
 507 static struct omap_hwmod omap44xx_iva_hwmod = {
 508         .name           = "iva",
 509         .class          = &omap44xx_iva_hwmod_class,
 510         .clkdm_name     = "ivahd_clkdm",
 511         .rst_lines      = omap44xx_iva_resets,
 512         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
 513         .main_clk       = "dpll_iva_m5x2_ck",
 514         .prcm = {
 515                 .omap4 = {
 516                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
 517                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
 518                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
 519                         .modulemode   = MODULEMODE_HWCTRL,
 520                 },
 521         },
 522 };
 523
 524 /*
 525  * 'mpu' class
 526  * mpu sub-system
 527  */
 528
 529 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 530         .name   = "mpu",
 531 };
 532
 533 /* mpu */
 534 static struct omap_hwmod omap44xx_mpu_hwmod = {
 535         .name           = "mpu",
 536         .class          = &omap44xx_mpu_hwmod_class,
 537         .clkdm_name     = "mpuss_clkdm",
 538         .flags          = HWMOD_INIT_NO_IDLE,
 539         .main_clk       = "dpll_mpu_m2_ck",
 540         .prcm = {
 541                 .omap4 = {
 542                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
 543                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
 544                 },
 545         },
 546 };
 547
 548 /*
 549  * 'ocmc_ram' class
 550  * top-level core on-chip ram
 551  */
 552
 553 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
 554         .name   = "ocmc_ram",
 555 };
 556
 557 /* ocmc_ram */
 558 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
 559         .name           = "ocmc_ram",
 560         .class          = &omap44xx_ocmc_ram_hwmod_class,
 561         .clkdm_name     = "l3_2_clkdm",
 562         .prcm = {
 563                 .omap4 = {
 564                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
 565                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
 566                 },
 567         },
 568 };
 569
 570
 571 /*
 572  * 'prcm' class
 573  * power and reset manager (part of the prcm infrastructure) + clock manager 2
 574  * + clock manager 1 (in always on power domain) + local prm in mpu
 575  */
 576
 577 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
 578         .name   = "prcm",
 579 };
 580
 581 /* prcm_mpu */
 582 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 583         .name           = "prcm_mpu",
 584         .class          = &omap44xx_prcm_hwmod_class,
 585         .clkdm_name     = "l4_wkup_clkdm",
 586         .flags          = HWMOD_NO_IDLEST,
 587         .prcm = {
 588                 .omap4 = {
 589                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 590                 },
 591         },
 592 };
 593
 594 /* cm_core_aon */
 595 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
 596         .name           = "cm_core_aon",
 597         .class          = &omap44xx_prcm_hwmod_class,
 598         .flags          = HWMOD_NO_IDLEST,
 599         .prcm = {
 600                 .omap4 = {
 601                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 602                 },
 603         },
 604 };
 605
 606 /* cm_core */
 607 static struct omap_hwmod omap44xx_cm_core_hwmod = {
 608         .name           = "cm_core",
 609         .class          = &omap44xx_prcm_hwmod_class,
 610         .flags          = HWMOD_NO_IDLEST,
 611         .prcm = {
 612                 .omap4 = {
 613                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 614                 },
 615         },
 616 };
 617
 618 /* prm */
 619 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 620         { .name = "rst_global_warm_sw", .rst_shift = 0 },
 621         { .name = "rst_global_cold_sw", .rst_shift = 1 },
 622 };
 623
 624 static struct omap_hwmod omap44xx_prm_hwmod = {
 625         .name           = "prm",
 626         .class          = &omap44xx_prcm_hwmod_class,
 627         .rst_lines      = omap44xx_prm_resets,
 628         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 629 };
 630
 631 /*
 632  * 'scrm' class
 633  * system clock and reset manager
 634  */
 635
 636 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
 637         .name   = "scrm",
 638 };
 639
 640 /* scrm */
 641 static struct omap_hwmod omap44xx_scrm_hwmod = {
 642         .name           = "scrm",
 643         .class          = &omap44xx_scrm_hwmod_class,
 644         .clkdm_name     = "l4_wkup_clkdm",
 645         .prcm = {
 646                 .omap4 = {
 647                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 648                 },
 649         },
 650 };
 651
 652 /*
 653  * 'sl2if' class
 654  * shared level 2 memory interface
 655  */
 656
 657 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
 658         .name   = "sl2if",
 659 };
 660
 661 /* sl2if */
 662 static struct omap_hwmod omap44xx_sl2if_hwmod = {
 663         .name           = "sl2if",
 664         .class          = &omap44xx_sl2if_hwmod_class,
 665         .clkdm_name     = "ivahd_clkdm",
 666         .prcm = {
 667                 .omap4 = {
 668                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
 669                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
 670                         .modulemode   = MODULEMODE_HWCTRL,
 671                 },
 672         },
 673 };
 674
 675 /*
 676  * 'timer' class
 677  * general purpose timer module with accurate 1ms tick
 678  * This class contains several variants: ['timer_1ms', 'timer']
 679  */
 680
 681 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
 682         .rev_offs       = 0x0000,
 683         .sysc_offs      = 0x0010,
 684         .syss_offs      = 0x0014,
 685         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 686                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
 687                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 688                            SYSS_HAS_RESET_STATUS),
 689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 690         .sysc_fields    = &omap_hwmod_sysc_type1,
 691 };
 692
 693 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
 694         .name   = "timer",
 695         .sysc   = &omap44xx_timer_1ms_sysc,
 696 };
 697
 698 /* timer1 */
 699 static struct omap_hwmod omap44xx_timer1_hwmod = {
 700         .name           = "timer1",
 701         .class          = &omap44xx_timer_1ms_hwmod_class,
 702         .clkdm_name     = "l4_wkup_clkdm",
 703         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 704         .main_clk       = "dmt1_clk_mux",
 705         .prcm = {
 706                 .omap4 = {
 707                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
 708                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
 709                         .modulemode   = MODULEMODE_SWCTRL,
 710                 },
 711         },
 712 };
 713
 714 /*
 715  * 'usb_host_fs' class
 716  * full-speed usb host controller
 717  */
 718
 719 /* The IP is not compliant to type1 / type2 scheme */
 720 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
 721         .rev_offs       = 0x0000,
 722         .sysc_offs      = 0x0210,
 723         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
 724                            SYSC_HAS_SOFTRESET),
 725         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 726                            SIDLE_SMART_WKUP),
 727         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
 728 };
 729
 730 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
 731         .name   = "usb_host_fs",
 732         .sysc   = &omap44xx_usb_host_fs_sysc,
 733 };
 734
 735 /* usb_host_fs */
 736 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
 737         .name           = "usb_host_fs",
 738         .class          = &omap44xx_usb_host_fs_hwmod_class,
 739         .clkdm_name     = "l3_init_clkdm",
 740         .main_clk       = "usb_host_fs_fck",
 741         .prcm = {
 742                 .omap4 = {
 743                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
 744                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
 745                         .modulemode   = MODULEMODE_SWCTRL,
 746                 },
 747         },
 748 };
 749
 750 /*
 751  * 'usb_host_hs' class
 752  * high-speed multi-port usb host controller
 753  */
 754
 755 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
 756         .rev_offs       = 0x0000,
 757         .sysc_offs      = 0x0010,
 758         .syss_offs      = 0x0014,
 759         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
 760                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
 761         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 762                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 763                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 764         .sysc_fields    = &omap_hwmod_sysc_type2,
 765 };
 766
 767 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
 768         .name   = "usb_host_hs",
 769         .sysc   = &omap44xx_usb_host_hs_sysc,
 770 };
 771
 772 /* usb_host_hs */
 773 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
 774         .name           = "usb_host_hs",
 775         .class          = &omap44xx_usb_host_hs_hwmod_class,
 776         .clkdm_name     = "l3_init_clkdm",
 777         .main_clk       = "usb_host_hs_fck",
 778         .prcm = {
 779                 .omap4 = {
 780                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
 781                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
 782                         .modulemode   = MODULEMODE_SWCTRL,
 783                 },
 784         },
 785
 786         /*
 787          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
 788          * id: i660
 789          *
 790          * Description:
 791          * In the following configuration :
 792          * - USBHOST module is set to smart-idle mode
 793          * - PRCM asserts idle_req to the USBHOST module ( This typically
 794          *   happens when the system is going to a low power mode : all ports
 795          *   have been suspended, the master part of the USBHOST module has
 796          *   entered the standby state, and SW has cut the functional clocks)
 797          * - an USBHOST interrupt occurs before the module is able to answer
 798          *   idle_ack, typically a remote wakeup IRQ.
 799          * Then the USB HOST module will enter a deadlock situation where it
 800          * is no more accessible nor functional.
 801          *
 802          * Workaround:
 803          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
 804          */
 805
 806         /*
 807          * Errata: USB host EHCI may stall when entering smart-standby mode
 808          * Id: i571
 809          *
 810          * Description:
 811          * When the USBHOST module is set to smart-standby mode, and when it is
 812          * ready to enter the standby state (i.e. all ports are suspended and
 813          * all attached devices are in suspend mode), then it can wrongly assert
 814          * the Mstandby signal too early while there are still some residual OCP
 815          * transactions ongoing. If this condition occurs, the internal state
 816          * machine may go to an undefined state and the USB link may be stuck
 817          * upon the next resume.
 818          *
 819          * Workaround:
 820          * Don't use smart standby; use only force standby,
 821          * hence HWMOD_SWSUP_MSTANDBY
 822          */
 823
 824         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 825 };
 826
 827 /*
 828  * 'usb_tll_hs' class
 829  * usb_tll_hs module is the adapter on the usb_host_hs ports
 830  */
 831
 832 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
 833         .rev_offs       = 0x0000,
 834         .sysc_offs      = 0x0010,
 835         .syss_offs      = 0x0014,
 836         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 837                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 838                            SYSC_HAS_AUTOIDLE),
 839         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 840         .sysc_fields    = &omap_hwmod_sysc_type1,
 841 };
 842
 843 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
 844         .name   = "usb_tll_hs",
 845         .sysc   = &omap44xx_usb_tll_hs_sysc,
 846 };
 847
 848 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
 849         .name           = "usb_tll_hs",
 850         .class          = &omap44xx_usb_tll_hs_hwmod_class,
 851         .clkdm_name     = "l3_init_clkdm",
 852         .main_clk       = "usb_tll_hs_ick",
 853         .prcm = {
 854                 .omap4 = {
 855                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
 856                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
 857                         .modulemode   = MODULEMODE_HWCTRL,
 858                 },
 859         },
 860 };
 861
 862 /*
 863  * interfaces
 864  */
 865
 866 /* l3_main_1 -> dmm */
 867 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
 868         .master         = &omap44xx_l3_main_1_hwmod,
 869         .slave          = &omap44xx_dmm_hwmod,
 870         .clk            = "l3_div_ck",
 871         .user           = OCP_USER_SDMA,
 872 };
 873
 874 /* mpu -> dmm */
 875 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 876         .master         = &omap44xx_mpu_hwmod,
 877         .slave          = &omap44xx_dmm_hwmod,
 878         .clk            = "l3_div_ck",
 879         .user           = OCP_USER_MPU,
 880 };
 881
 882 /* iva -> l3_instr */
 883 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 884         .master         = &omap44xx_iva_hwmod,
 885         .slave          = &omap44xx_l3_instr_hwmod,
 886         .clk            = "l3_div_ck",
 887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 888 };
 889
 890 /* l3_main_3 -> l3_instr */
 891 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 892         .master         = &omap44xx_l3_main_3_hwmod,
 893         .slave          = &omap44xx_l3_instr_hwmod,
 894         .clk            = "l3_div_ck",
 895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 896 };
 897
 898 /* ocp_wp_noc -> l3_instr */
 899 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
 900         .master         = &omap44xx_ocp_wp_noc_hwmod,
 901         .slave          = &omap44xx_l3_instr_hwmod,
 902         .clk            = "l3_div_ck",
 903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 904 };
 905
 906 /* l3_main_2 -> l3_main_1 */
 907 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 908         .master         = &omap44xx_l3_main_2_hwmod,
 909         .slave          = &omap44xx_l3_main_1_hwmod,
 910         .clk            = "l3_div_ck",
 911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 912 };
 913
 914 /* l4_cfg -> l3_main_1 */
 915 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 916         .master         = &omap44xx_l4_cfg_hwmod,
 917         .slave          = &omap44xx_l3_main_1_hwmod,
 918         .clk            = "l4_div_ck",
 919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 920 };
 921
 922 /* mpu -> l3_main_1 */
 923 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 924         .master         = &omap44xx_mpu_hwmod,
 925         .slave          = &omap44xx_l3_main_1_hwmod,
 926         .clk            = "l3_div_ck",
 927         .user           = OCP_USER_MPU,
 928 };
 929
 930 /* debugss -> l3_main_2 */
 931 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
 932         .master         = &omap44xx_debugss_hwmod,
 933         .slave          = &omap44xx_l3_main_2_hwmod,
 934         .clk            = "dbgclk_mux_ck",
 935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 936 };
 937
 938 /* iss -> l3_main_2 */
 939 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 940         .master         = &omap44xx_iss_hwmod,
 941         .slave          = &omap44xx_l3_main_2_hwmod,
 942         .clk            = "l3_div_ck",
 943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 944 };
 945
 946 /* iva -> l3_main_2 */
 947 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 948         .master         = &omap44xx_iva_hwmod,
 949         .slave          = &omap44xx_l3_main_2_hwmod,
 950         .clk            = "l3_div_ck",
 951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 952 };
 953
 954 /* l3_main_1 -> l3_main_2 */
 955 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 956         .master         = &omap44xx_l3_main_1_hwmod,
 957         .slave          = &omap44xx_l3_main_2_hwmod,
 958         .clk            = "l3_div_ck",
 959         .user           = OCP_USER_MPU,
 960 };
 961
 962 /* l4_cfg -> l3_main_2 */
 963 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 964         .master         = &omap44xx_l4_cfg_hwmod,
 965         .slave          = &omap44xx_l3_main_2_hwmod,
 966         .clk            = "l4_div_ck",
 967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 968 };
 969
 970 /* usb_host_fs -> l3_main_2 */
 971 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
 972         .master         = &omap44xx_usb_host_fs_hwmod,
 973         .slave          = &omap44xx_l3_main_2_hwmod,
 974         .clk            = "l3_div_ck",
 975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 976 };
 977
 978 /* usb_host_hs -> l3_main_2 */
 979 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
 980         .master         = &omap44xx_usb_host_hs_hwmod,
 981         .slave          = &omap44xx_l3_main_2_hwmod,
 982         .clk            = "l3_div_ck",
 983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 984 };
 985
 986 /* l3_main_1 -> l3_main_3 */
 987 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 988         .master         = &omap44xx_l3_main_1_hwmod,
 989         .slave          = &omap44xx_l3_main_3_hwmod,
 990         .clk            = "l3_div_ck",
 991         .user           = OCP_USER_MPU,
 992 };
 993
 994 /* l3_main_2 -> l3_main_3 */
 995 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 996         .master         = &omap44xx_l3_main_2_hwmod,
 997         .slave          = &omap44xx_l3_main_3_hwmod,
 998         .clk            = "l3_div_ck",
 999         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1000 };
1001
1002 /* l4_cfg -> l3_main_3 */
1003 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
1004         .master         = &omap44xx_l4_cfg_hwmod,
1005         .slave          = &omap44xx_l3_main_3_hwmod,
1006         .clk            = "l4_div_ck",
1007         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1008 };
1009
1010 /* l3_main_1 -> l4_abe */
1011 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
1012         .master         = &omap44xx_l3_main_1_hwmod,
1013         .slave          = &omap44xx_l4_abe_hwmod,
1014         .clk            = "l3_div_ck",
1015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1016 };
1017
1018 /* mpu -> l4_abe */
1019 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
1020         .master         = &omap44xx_mpu_hwmod,
1021         .slave          = &omap44xx_l4_abe_hwmod,
1022         .clk            = "ocp_abe_iclk",
1023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1024 };
1025
1026 /* l3_main_1 -> l4_cfg */
1027 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
1028         .master         = &omap44xx_l3_main_1_hwmod,
1029         .slave          = &omap44xx_l4_cfg_hwmod,
1030         .clk            = "l3_div_ck",
1031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1032 };
1033
1034 /* l3_main_2 -> l4_per */
1035 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
1036         .master         = &omap44xx_l3_main_2_hwmod,
1037         .slave          = &omap44xx_l4_per_hwmod,
1038         .clk            = "l3_div_ck",
1039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1040 };
1041
1042 /* l4_cfg -> l4_wkup */
1043 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
1044         .master         = &omap44xx_l4_cfg_hwmod,
1045         .slave          = &omap44xx_l4_wkup_hwmod,
1046         .clk            = "l4_div_ck",
1047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1048 };
1049
1050 /* mpu -> mpu_private */
1051 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
1052         .master         = &omap44xx_mpu_hwmod,
1053         .slave          = &omap44xx_mpu_private_hwmod,
1054         .clk            = "l3_div_ck",
1055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1056 };
1057
1058 /* l4_cfg -> ocp_wp_noc */
1059 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
1060         .master         = &omap44xx_l4_cfg_hwmod,
1061         .slave          = &omap44xx_ocp_wp_noc_hwmod,
1062         .clk            = "l4_div_ck",
1063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1064 };
1065
1066 /* l4_wkup -> counter_32k */
1067 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
1068         .master         = &omap44xx_l4_wkup_hwmod,
1069         .slave          = &omap44xx_counter_32k_hwmod,
1070         .clk            = "l4_wkup_clk_mux_ck",
1071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1072 };
1073
1074 /* l4_cfg -> ctrl_module_core */
1075 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
1076         .master         = &omap44xx_l4_cfg_hwmod,
1077         .slave          = &omap44xx_ctrl_module_core_hwmod,
1078         .clk            = "l4_div_ck",
1079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1080 };
1081
1082 /* l4_cfg -> ctrl_module_pad_core */
1083 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
1084         .master         = &omap44xx_l4_cfg_hwmod,
1085         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
1086         .clk            = "l4_div_ck",
1087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1088 };
1089
1090 /* l4_wkup -> ctrl_module_wkup */
1091 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
1092         .master         = &omap44xx_l4_wkup_hwmod,
1093         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
1094         .clk            = "l4_wkup_clk_mux_ck",
1095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1096 };
1097
1098 /* l4_wkup -> ctrl_module_pad_wkup */
1099 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
1100         .master         = &omap44xx_l4_wkup_hwmod,
1101         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
1102         .clk            = "l4_wkup_clk_mux_ck",
1103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1104 };
1105
1106 /* l3_instr -> debugss */
1107 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
1108         .master         = &omap44xx_l3_instr_hwmod,
1109         .slave          = &omap44xx_debugss_hwmod,
1110         .clk            = "l3_div_ck",
1111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1112 };
1113
1114 /* l3_main_2 -> gpmc */
1115 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
1116         .master         = &omap44xx_l3_main_2_hwmod,
1117         .slave          = &omap44xx_gpmc_hwmod,
1118         .clk            = "l3_div_ck",
1119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1120 };
1121
1122 /* l3_main_2 -> iss */
1123 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
1124         .master         = &omap44xx_l3_main_2_hwmod,
1125         .slave          = &omap44xx_iss_hwmod,
1126         .clk            = "l3_div_ck",
1127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1128 };
1129
1130 /* iva -> sl2if */
1131 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
1132         .master         = &omap44xx_iva_hwmod,
1133         .slave          = &omap44xx_sl2if_hwmod,
1134         .clk            = "dpll_iva_m5x2_ck",
1135         .user           = OCP_USER_IVA,
1136 };
1137
1138 /* l3_main_2 -> iva */
1139 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1140         .master         = &omap44xx_l3_main_2_hwmod,
1141         .slave          = &omap44xx_iva_hwmod,
1142         .clk            = "l3_div_ck",
1143         .user           = OCP_USER_MPU,
1144 };
1145
1146 /* l3_main_2 -> ocmc_ram */
1147 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
1148         .master         = &omap44xx_l3_main_2_hwmod,
1149         .slave          = &omap44xx_ocmc_ram_hwmod,
1150         .clk            = "l3_div_ck",
1151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1152 };
1153
1154 /* mpu_private -> prcm_mpu */
1155 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
1156         .master         = &omap44xx_mpu_private_hwmod,
1157         .slave          = &omap44xx_prcm_mpu_hwmod,
1158         .clk            = "l3_div_ck",
1159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1160 };
1161
1162 /* l4_wkup -> cm_core_aon */
1163 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
1164         .master         = &omap44xx_l4_wkup_hwmod,
1165         .slave          = &omap44xx_cm_core_aon_hwmod,
1166         .clk            = "l4_wkup_clk_mux_ck",
1167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1168 };
1169
1170 /* l4_cfg -> cm_core */
1171 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
1172         .master         = &omap44xx_l4_cfg_hwmod,
1173         .slave          = &omap44xx_cm_core_hwmod,
1174         .clk            = "l4_div_ck",
1175         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1176 };
1177
1178 /* l4_wkup -> prm */
1179 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
1180         .master         = &omap44xx_l4_wkup_hwmod,
1181         .slave          = &omap44xx_prm_hwmod,
1182         .clk            = "l4_wkup_clk_mux_ck",
1183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1184 };
1185
1186 /* l4_wkup -> scrm */
1187 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
1188         .master         = &omap44xx_l4_wkup_hwmod,
1189         .slave          = &omap44xx_scrm_hwmod,
1190         .clk            = "l4_wkup_clk_mux_ck",
1191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1192 };
1193
1194 /* l3_main_2 -> sl2if */
1195 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
1196         .master         = &omap44xx_l3_main_2_hwmod,
1197         .slave          = &omap44xx_sl2if_hwmod,
1198         .clk            = "l3_div_ck",
1199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1200 };
1201
1202 /* l4_wkup -> timer1 */
1203 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
1204         .master         = &omap44xx_l4_wkup_hwmod,
1205         .slave          = &omap44xx_timer1_hwmod,
1206         .clk            = "l4_wkup_clk_mux_ck",
1207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1208 };
1209
1210 /* l4_cfg -> usb_host_fs */
1211 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
1212         .master         = &omap44xx_l4_cfg_hwmod,
1213         .slave          = &omap44xx_usb_host_fs_hwmod,
1214         .clk            = "l4_div_ck",
1215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1216 };
1217
1218 /* l4_cfg -> usb_host_hs */
1219 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
1220         .master         = &omap44xx_l4_cfg_hwmod,
1221         .slave          = &omap44xx_usb_host_hs_hwmod,
1222         .clk            = "l4_div_ck",
1223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1224 };
1225
1226 /* l4_cfg -> usb_tll_hs */
1227 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
1228         .master         = &omap44xx_l4_cfg_hwmod,
1229         .slave          = &omap44xx_usb_tll_hs_hwmod,
1230         .clk            = "l4_div_ck",
1231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1232 };
1233
1234 /* mpu -> emif1 */
1235 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
1236         .master         = &omap44xx_mpu_hwmod,
1237         .slave          = &omap44xx_emif1_hwmod,
1238         .clk            = "l3_div_ck",
1239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1240 };
1241
1242 /* mpu -> emif2 */
1243 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
1244         .master         = &omap44xx_mpu_hwmod,
1245         .slave          = &omap44xx_emif2_hwmod,
1246         .clk            = "l3_div_ck",
1247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1248 };
1249
1250 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
1251         &omap44xx_l3_main_1__dmm,
1252         &omap44xx_mpu__dmm,
1253         &omap44xx_iva__l3_instr,
1254         &omap44xx_l3_main_3__l3_instr,
1255         &omap44xx_ocp_wp_noc__l3_instr,
1256         &omap44xx_l3_main_2__l3_main_1,
1257         &omap44xx_l4_cfg__l3_main_1,
1258         &omap44xx_mpu__l3_main_1,
1259         &omap44xx_debugss__l3_main_2,
1260         &omap44xx_iss__l3_main_2,
1261         &omap44xx_iva__l3_main_2,
1262         &omap44xx_l3_main_1__l3_main_2,
1263         &omap44xx_l4_cfg__l3_main_2,
1264         /* &omap44xx_usb_host_fs__l3_main_2, */
1265         &omap44xx_usb_host_hs__l3_main_2,
1266         &omap44xx_l3_main_1__l3_main_3,
1267         &omap44xx_l3_main_2__l3_main_3,
1268         &omap44xx_l4_cfg__l3_main_3,
1269         &omap44xx_l3_main_1__l4_abe,
1270         &omap44xx_mpu__l4_abe,
1271         &omap44xx_l3_main_1__l4_cfg,
1272         &omap44xx_l3_main_2__l4_per,
1273         &omap44xx_l4_cfg__l4_wkup,
1274         &omap44xx_mpu__mpu_private,
1275         &omap44xx_l4_cfg__ocp_wp_noc,
1276         &omap44xx_l4_wkup__counter_32k,
1277         &omap44xx_l4_cfg__ctrl_module_core,
1278         &omap44xx_l4_cfg__ctrl_module_pad_core,
1279         &omap44xx_l4_wkup__ctrl_module_wkup,
1280         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
1281         &omap44xx_l3_instr__debugss,
1282         &omap44xx_l3_main_2__gpmc,
1283         &omap44xx_l3_main_2__iss,
1284         /* &omap44xx_iva__sl2if, */
1285         &omap44xx_l3_main_2__iva,
1286         &omap44xx_l3_main_2__ocmc_ram,
1287         &omap44xx_mpu_private__prcm_mpu,
1288         &omap44xx_l4_wkup__cm_core_aon,
1289         &omap44xx_l4_cfg__cm_core,
1290         &omap44xx_l4_wkup__prm,
1291         &omap44xx_l4_wkup__scrm,
1292         /* &omap44xx_l3_main_2__sl2if, */
1293         &omap44xx_l4_wkup__timer1,
1294         /* &omap44xx_l4_cfg__usb_host_fs, */
1295         &omap44xx_l4_cfg__usb_host_hs,
1296         &omap44xx_l4_cfg__usb_tll_hs,
1297         &omap44xx_mpu__emif1,
1298         &omap44xx_mpu__emif2,
1299         NULL,
1300 };
1301
1302 int __init omap44xx_hwmod_init(void)
1303 {
1304         omap_hwmod_init();
1305         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
1306 }
1307