arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP54xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19
  20 #include "omap_hwmod.h"
  21 #include "omap_hwmod_common_data.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24 #include "prm54xx.h"
  25
  26 /* Base offset for all OMAP5 interrupts external to MPUSS */
  27 #define OMAP54XX_IRQ_GIC_START  32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'dmm' class
  35  * instance(s): dmm
  36  */
  37 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  38         .name   = "dmm",
  39 };
  40
  41 /* dmm */
  42 static struct omap_hwmod omap54xx_dmm_hwmod = {
  43         .name           = "dmm",
  44         .class          = &omap54xx_dmm_hwmod_class,
  45         .clkdm_name     = "emif_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  49                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  50                 },
  51         },
  52 };
  53
  54 /*
  55  * 'l3' class
  56  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  57  */
  58 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  59         .name   = "l3",
  60 };
  61
  62 /* l3_instr */
  63 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &omap54xx_l3_hwmod_class,
  66         .clkdm_name     = "l3instr_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  71                         .modulemode   = MODULEMODE_HWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /* l3_main_1 */
  77 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  78         .name           = "l3_main_1",
  79         .class          = &omap54xx_l3_hwmod_class,
  80         .clkdm_name     = "l3main1_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  84                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_2 */
  90 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
  91         .name           = "l3_main_2",
  92         .class          = &omap54xx_l3_hwmod_class,
  93         .clkdm_name     = "l3main2_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /* l3_main_3 */
 103 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 104         .name           = "l3_main_3",
 105         .class          = &omap54xx_l3_hwmod_class,
 106         .clkdm_name     = "l3instr_clkdm",
 107         .prcm = {
 108                 .omap4 = {
 109                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 110                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 111                         .modulemode   = MODULEMODE_HWCTRL,
 112                 },
 113         },
 114 };
 115
 116 /*
 117  * 'l4' class
 118  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 119  */
 120 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 121         .name   = "l4",
 122 };
 123
 124 /* l4_abe */
 125 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 126         .name           = "l4_abe",
 127         .class          = &omap54xx_l4_hwmod_class,
 128         .clkdm_name     = "abe_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 132                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 133                 },
 134         },
 135 };
 136
 137 /* l4_cfg */
 138 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 139         .name           = "l4_cfg",
 140         .class          = &omap54xx_l4_hwmod_class,
 141         .clkdm_name     = "l4cfg_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 145                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 146                 },
 147         },
 148 };
 149
 150 /* l4_per */
 151 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 152         .name           = "l4_per",
 153         .class          = &omap54xx_l4_hwmod_class,
 154         .clkdm_name     = "l4per_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l4_wkup */
 164 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 165         .name           = "l4_wkup",
 166         .class          = &omap54xx_l4_hwmod_class,
 167         .clkdm_name     = "wkupaon_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /*
 177  * 'mpu_bus' class
 178  * instance(s): mpu_private
 179  */
 180 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 181         .name   = "mpu_bus",
 182 };
 183
 184 /* mpu_private */
 185 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 186         .name           = "mpu_private",
 187         .class          = &omap54xx_mpu_bus_hwmod_class,
 188         .clkdm_name     = "mpu_clkdm",
 189         .prcm = {
 190                 .omap4 = {
 191                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 192                 },
 193         },
 194 };
 195
 196 /*
 197  * 'counter' class
 198  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 199  */
 200
 201 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 202         .rev_offs       = 0x0000,
 203         .sysc_offs      = 0x0010,
 204         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 205         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 206         .sysc_fields    = &omap_hwmod_sysc_type1,
 207 };
 208
 209 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 210         .name   = "counter",
 211         .sysc   = &omap54xx_counter_sysc,
 212 };
 213
 214 /* counter_32k */
 215 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 216         .name           = "counter_32k",
 217         .class          = &omap54xx_counter_hwmod_class,
 218         .clkdm_name     = "wkupaon_clkdm",
 219         .flags          = HWMOD_SWSUP_SIDLE,
 220         .main_clk       = "wkupaon_iclk_mux",
 221         .prcm = {
 222                 .omap4 = {
 223                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 224                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 225                 },
 226         },
 227 };
 228
 229 /*
 230  * 'emif' class
 231  * external memory interface no1 (wrapper)
 232  */
 233
 234 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 235         .rev_offs       = 0x0000,
 236 };
 237
 238 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 239         .name   = "emif",
 240         .sysc   = &omap54xx_emif_sysc,
 241 };
 242
 243 /* emif1 */
 244 static struct omap_hwmod omap54xx_emif1_hwmod = {
 245         .name           = "emif1",
 246         .class          = &omap54xx_emif_hwmod_class,
 247         .clkdm_name     = "emif_clkdm",
 248         .flags          = HWMOD_INIT_NO_IDLE,
 249         .main_clk       = "dpll_core_h11x2_ck",
 250         .prcm = {
 251                 .omap4 = {
 252                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 253                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 254                         .modulemode   = MODULEMODE_HWCTRL,
 255                 },
 256         },
 257 };
 258
 259 /* emif2 */
 260 static struct omap_hwmod omap54xx_emif2_hwmod = {
 261         .name           = "emif2",
 262         .class          = &omap54xx_emif_hwmod_class,
 263         .clkdm_name     = "emif_clkdm",
 264         .flags          = HWMOD_INIT_NO_IDLE,
 265         .main_clk       = "dpll_core_h11x2_ck",
 266         .prcm = {
 267                 .omap4 = {
 268                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 269                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 270                         .modulemode   = MODULEMODE_HWCTRL,
 271                 },
 272         },
 273 };
 274
 275
 276
 277
 278 /*
 279  * 'mpu' class
 280  * mpu sub-system
 281  */
 282
 283 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
 284         .name   = "mpu",
 285 };
 286
 287 /* mpu */
 288 static struct omap_hwmod omap54xx_mpu_hwmod = {
 289         .name           = "mpu",
 290         .class          = &omap54xx_mpu_hwmod_class,
 291         .clkdm_name     = "mpu_clkdm",
 292         .flags          = HWMOD_INIT_NO_IDLE,
 293         .main_clk       = "dpll_mpu_m2_ck",
 294         .prcm = {
 295                 .omap4 = {
 296                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 297                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
 298                 },
 299         },
 300 };
 301
 302
 303 /*
 304  * 'timer' class
 305  * general purpose timer module with accurate 1ms tick
 306  * This class contains several variants: ['timer_1ms', 'timer']
 307  */
 308
 309 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
 310         .rev_offs       = 0x0000,
 311         .sysc_offs      = 0x0010,
 312         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 313                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 315                            SIDLE_SMART_WKUP),
 316         .sysc_fields    = &omap_hwmod_sysc_type2,
 317 };
 318
 319 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
 320         .name   = "timer",
 321         .sysc   = &omap54xx_timer_1ms_sysc,
 322 };
 323
 324 /* timer1 */
 325 static struct omap_hwmod omap54xx_timer1_hwmod = {
 326         .name           = "timer1",
 327         .class          = &omap54xx_timer_1ms_hwmod_class,
 328         .clkdm_name     = "wkupaon_clkdm",
 329         .main_clk       = "timer1_gfclk_mux",
 330         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
 334                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
 335                         .modulemode   = MODULEMODE_SWCTRL,
 336                 },
 337         },
 338 };
 339
 340 /*
 341  * 'usb_host_hs' class
 342  * high-speed multi-port usb host controller
 343  */
 344
 345 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
 346         .rev_offs       = 0x0000,
 347         .sysc_offs      = 0x0010,
 348         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 349                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 350         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 351                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 352                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 353         .sysc_fields    = &omap_hwmod_sysc_type2,
 354 };
 355
 356 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
 357         .name   = "usb_host_hs",
 358         .sysc   = &omap54xx_usb_host_hs_sysc,
 359 };
 360
 361 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
 362         .name           = "usb_host_hs",
 363         .class          = &omap54xx_usb_host_hs_hwmod_class,
 364         .clkdm_name     = "l3init_clkdm",
 365         /*
 366          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
 367          * id: i660
 368          *
 369          * Description:
 370          * In the following configuration :
 371          * - USBHOST module is set to smart-idle mode
 372          * - PRCM asserts idle_req to the USBHOST module ( This typically
 373          *   happens when the system is going to a low power mode : all ports
 374          *   have been suspended, the master part of the USBHOST module has
 375          *   entered the standby state, and SW has cut the functional clocks)
 376          * - an USBHOST interrupt occurs before the module is able to answer
 377          *   idle_ack, typically a remote wakeup IRQ.
 378          * Then the USB HOST module will enter a deadlock situation where it
 379          * is no more accessible nor functional.
 380          *
 381          * Workaround:
 382          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
 383          */
 384
 385         /*
 386          * Errata: USB host EHCI may stall when entering smart-standby mode
 387          * Id: i571
 388          *
 389          * Description:
 390          * When the USBHOST module is set to smart-standby mode, and when it is
 391          * ready to enter the standby state (i.e. all ports are suspended and
 392          * all attached devices are in suspend mode), then it can wrongly assert
 393          * the Mstandby signal too early while there are still some residual OCP
 394          * transactions ongoing. If this condition occurs, the internal state
 395          * machine may go to an undefined state and the USB link may be stuck
 396          * upon the next resume.
 397          *
 398          * Workaround:
 399          * Don't use smart standby; use only force standby,
 400          * hence HWMOD_SWSUP_MSTANDBY
 401          */
 402
 403         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 404         .main_clk       = "l3init_60m_fclk",
 405         .prcm = {
 406                 .omap4 = {
 407                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
 408                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
 409                         .modulemode   = MODULEMODE_SWCTRL,
 410                 },
 411         },
 412 };
 413
 414 /*
 415  * 'usb_tll_hs' class
 416  * usb_tll_hs module is the adapter on the usb_host_hs ports
 417  */
 418
 419 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
 420         .rev_offs       = 0x0000,
 421         .sysc_offs      = 0x0010,
 422         .syss_offs      = 0x0014,
 423         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 424                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 425                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 426         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 427         .sysc_fields    = &omap_hwmod_sysc_type1,
 428 };
 429
 430 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
 431         .name   = "usb_tll_hs",
 432         .sysc   = &omap54xx_usb_tll_hs_sysc,
 433 };
 434
 435 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
 436         .name           = "usb_tll_hs",
 437         .class          = &omap54xx_usb_tll_hs_hwmod_class,
 438         .clkdm_name     = "l3init_clkdm",
 439         .main_clk       = "l4_root_clk_div",
 440         .prcm = {
 441                 .omap4 = {
 442                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
 443                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
 444                         .modulemode   = MODULEMODE_HWCTRL,
 445                 },
 446         },
 447 };
 448
 449 /*
 450  * 'usb_otg_ss' class
 451  * 2.0 super speed (usb_otg_ss) controller
 452  */
 453
 454 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
 455         .rev_offs       = 0x0000,
 456         .sysc_offs      = 0x0010,
 457         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
 458                            SYSC_HAS_SIDLEMODE),
 459         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 460                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 461                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 462         .sysc_fields    = &omap_hwmod_sysc_type2,
 463 };
 464
 465 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
 466         .name   = "usb_otg_ss",
 467         .sysc   = &omap54xx_usb_otg_ss_sysc,
 468 };
 469
 470 /* usb_otg_ss */
 471 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
 472         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
 473 };
 474
 475 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
 476         .name           = "usb_otg_ss",
 477         .class          = &omap54xx_usb_otg_ss_hwmod_class,
 478         .clkdm_name     = "l3init_clkdm",
 479         .flags          = HWMOD_SWSUP_SIDLE,
 480         .main_clk       = "dpll_core_h13x2_ck",
 481         .prcm = {
 482                 .omap4 = {
 483                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
 484                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
 485                         .modulemode   = MODULEMODE_HWCTRL,
 486                 },
 487         },
 488         .opt_clks       = usb_otg_ss_opt_clks,
 489         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
 490 };
 491
 492 /*
 493  * 'sata' class
 494  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
 495  */
 496
 497 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
 498         .rev_offs       = 0x00fc,
 499         .sysc_offs      = 0x0000,
 500         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 502                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 503                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 504         .sysc_fields    = &omap_hwmod_sysc_type2,
 505 };
 506
 507 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
 508         .name   = "sata",
 509         .sysc   = &omap54xx_sata_sysc,
 510 };
 511
 512 /* sata */
 513 static struct omap_hwmod omap54xx_sata_hwmod = {
 514         .name           = "sata",
 515         .class          = &omap54xx_sata_hwmod_class,
 516         .clkdm_name     = "l3init_clkdm",
 517         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 518         .main_clk       = "func_48m_fclk",
 519         .mpu_rt_idx     = 1,
 520         .prcm = {
 521                 .omap4 = {
 522                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 523                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 524                         .modulemode   = MODULEMODE_SWCTRL,
 525                 },
 526         },
 527 };
 528
 529 /* l4_cfg -> sata */
 530 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
 531         .master         = &omap54xx_l4_cfg_hwmod,
 532         .slave          = &omap54xx_sata_hwmod,
 533         .clk            = "l3_iclk_div",
 534         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 535 };
 536
 537 /*
 538  * Interfaces
 539  */
 540
 541 /* l3_main_1 -> dmm */
 542 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
 543         .master         = &omap54xx_l3_main_1_hwmod,
 544         .slave          = &omap54xx_dmm_hwmod,
 545         .clk            = "l3_iclk_div",
 546         .user           = OCP_USER_SDMA,
 547 };
 548
 549 /* l3_main_3 -> l3_instr */
 550 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
 551         .master         = &omap54xx_l3_main_3_hwmod,
 552         .slave          = &omap54xx_l3_instr_hwmod,
 553         .clk            = "l3_iclk_div",
 554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 555 };
 556
 557 /* l3_main_2 -> l3_main_1 */
 558 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
 559         .master         = &omap54xx_l3_main_2_hwmod,
 560         .slave          = &omap54xx_l3_main_1_hwmod,
 561         .clk            = "l3_iclk_div",
 562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 563 };
 564
 565 /* l4_cfg -> l3_main_1 */
 566 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
 567         .master         = &omap54xx_l4_cfg_hwmod,
 568         .slave          = &omap54xx_l3_main_1_hwmod,
 569         .clk            = "l3_iclk_div",
 570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 571 };
 572
 573 /* mpu -> l3_main_1 */
 574 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
 575         .master         = &omap54xx_mpu_hwmod,
 576         .slave          = &omap54xx_l3_main_1_hwmod,
 577         .clk            = "l3_iclk_div",
 578         .user           = OCP_USER_MPU,
 579 };
 580
 581 /* l3_main_1 -> l3_main_2 */
 582 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
 583         .master         = &omap54xx_l3_main_1_hwmod,
 584         .slave          = &omap54xx_l3_main_2_hwmod,
 585         .clk            = "l3_iclk_div",
 586         .user           = OCP_USER_MPU,
 587 };
 588
 589 /* l4_cfg -> l3_main_2 */
 590 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
 591         .master         = &omap54xx_l4_cfg_hwmod,
 592         .slave          = &omap54xx_l3_main_2_hwmod,
 593         .clk            = "l3_iclk_div",
 594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 595 };
 596
 597 /* l3_main_1 -> l3_main_3 */
 598 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
 599         .master         = &omap54xx_l3_main_1_hwmod,
 600         .slave          = &omap54xx_l3_main_3_hwmod,
 601         .clk            = "l3_iclk_div",
 602         .user           = OCP_USER_MPU,
 603 };
 604
 605 /* l3_main_2 -> l3_main_3 */
 606 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
 607         .master         = &omap54xx_l3_main_2_hwmod,
 608         .slave          = &omap54xx_l3_main_3_hwmod,
 609         .clk            = "l3_iclk_div",
 610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 611 };
 612
 613 /* l4_cfg -> l3_main_3 */
 614 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
 615         .master         = &omap54xx_l4_cfg_hwmod,
 616         .slave          = &omap54xx_l3_main_3_hwmod,
 617         .clk            = "l3_iclk_div",
 618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 619 };
 620
 621 /* l3_main_1 -> l4_abe */
 622 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
 623         .master         = &omap54xx_l3_main_1_hwmod,
 624         .slave          = &omap54xx_l4_abe_hwmod,
 625         .clk            = "abe_iclk",
 626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 627 };
 628
 629 /* mpu -> l4_abe */
 630 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
 631         .master         = &omap54xx_mpu_hwmod,
 632         .slave          = &omap54xx_l4_abe_hwmod,
 633         .clk            = "abe_iclk",
 634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 635 };
 636
 637 /* l3_main_1 -> l4_cfg */
 638 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
 639         .master         = &omap54xx_l3_main_1_hwmod,
 640         .slave          = &omap54xx_l4_cfg_hwmod,
 641         .clk            = "l4_root_clk_div",
 642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 643 };
 644
 645 /* l3_main_2 -> l4_per */
 646 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
 647         .master         = &omap54xx_l3_main_2_hwmod,
 648         .slave          = &omap54xx_l4_per_hwmod,
 649         .clk            = "l4_root_clk_div",
 650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 651 };
 652
 653 /* l3_main_1 -> l4_wkup */
 654 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
 655         .master         = &omap54xx_l3_main_1_hwmod,
 656         .slave          = &omap54xx_l4_wkup_hwmod,
 657         .clk            = "wkupaon_iclk_mux",
 658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 659 };
 660
 661 /* mpu -> mpu_private */
 662 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
 663         .master         = &omap54xx_mpu_hwmod,
 664         .slave          = &omap54xx_mpu_private_hwmod,
 665         .clk            = "l3_iclk_div",
 666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 667 };
 668
 669 /* l4_wkup -> counter_32k */
 670 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
 671         .master         = &omap54xx_l4_wkup_hwmod,
 672         .slave          = &omap54xx_counter_32k_hwmod,
 673         .clk            = "wkupaon_iclk_mux",
 674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 675 };
 676
 677 /* mpu -> emif1 */
 678 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
 679         .master         = &omap54xx_mpu_hwmod,
 680         .slave          = &omap54xx_emif1_hwmod,
 681         .clk            = "dpll_core_h11x2_ck",
 682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 683 };
 684
 685 /* mpu -> emif2 */
 686 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
 687         .master         = &omap54xx_mpu_hwmod,
 688         .slave          = &omap54xx_emif2_hwmod,
 689         .clk            = "dpll_core_h11x2_ck",
 690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 691 };
 692
 693 /* l4_cfg -> mpu */
 694 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
 695         .master         = &omap54xx_l4_cfg_hwmod,
 696         .slave          = &omap54xx_mpu_hwmod,
 697         .clk            = "l4_root_clk_div",
 698         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 699 };
 700
 701 /* l4_wkup -> timer1 */
 702 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
 703         .master         = &omap54xx_l4_wkup_hwmod,
 704         .slave          = &omap54xx_timer1_hwmod,
 705         .clk            = "wkupaon_iclk_mux",
 706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 707 };
 708
 709 /* l4_cfg -> usb_host_hs */
 710 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
 711         .master         = &omap54xx_l4_cfg_hwmod,
 712         .slave          = &omap54xx_usb_host_hs_hwmod,
 713         .clk            = "l3_iclk_div",
 714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 715 };
 716
 717 /* l4_cfg -> usb_tll_hs */
 718 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
 719         .master         = &omap54xx_l4_cfg_hwmod,
 720         .slave          = &omap54xx_usb_tll_hs_hwmod,
 721         .clk            = "l4_root_clk_div",
 722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 723 };
 724
 725 /* l4_cfg -> usb_otg_ss */
 726 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
 727         .master         = &omap54xx_l4_cfg_hwmod,
 728         .slave          = &omap54xx_usb_otg_ss_hwmod,
 729         .clk            = "dpll_core_h13x2_ck",
 730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 731 };
 732
 733 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
 734         &omap54xx_l3_main_1__dmm,
 735         &omap54xx_l3_main_3__l3_instr,
 736         &omap54xx_l3_main_2__l3_main_1,
 737         &omap54xx_l4_cfg__l3_main_1,
 738         &omap54xx_mpu__l3_main_1,
 739         &omap54xx_l3_main_1__l3_main_2,
 740         &omap54xx_l4_cfg__l3_main_2,
 741         &omap54xx_l3_main_1__l3_main_3,
 742         &omap54xx_l3_main_2__l3_main_3,
 743         &omap54xx_l4_cfg__l3_main_3,
 744         &omap54xx_l3_main_1__l4_abe,
 745         &omap54xx_mpu__l4_abe,
 746         &omap54xx_l3_main_1__l4_cfg,
 747         &omap54xx_l3_main_2__l4_per,
 748         &omap54xx_l3_main_1__l4_wkup,
 749         &omap54xx_mpu__mpu_private,
 750         &omap54xx_l4_wkup__counter_32k,
 751         &omap54xx_mpu__emif1,
 752         &omap54xx_mpu__emif2,
 753         &omap54xx_l4_cfg__mpu,
 754         &omap54xx_l4_wkup__timer1,
 755         &omap54xx_l4_cfg__usb_host_hs,
 756         &omap54xx_l4_cfg__usb_tll_hs,
 757         &omap54xx_l4_cfg__usb_otg_ss,
 758         &omap54xx_l4_cfg__sata,
 759         NULL,
 760 };
 761
 762 int __init omap54xx_hwmod_init(void)
 763 {
 764         omap_hwmod_init();
 765         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
 766 }