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Linux 5.7.7
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_7xx_data.c
blobe95668bdbc3f3592bd8383116a2755ca8547ab87
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Hardware modules present on the DRA7xx chips
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 */
16
17 #include <linux/io.h>
18
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
21 #include "cm1_7xx.h"
22 #include "cm2_7xx.h"
23 #include "prm7xx.h"
24 #include "soc.h"
25
26 /* Base offset for all DRA7XX interrupts external to MPUSS */
27 #define DRA7XX_IRQ_GIC_START 32
28
29 /*
30 * IP blocks
31 */
32
33 /*
34 * 'dmm' class
35 * instance(s): dmm
36 */
37 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
38 .name = "dmm",
39 };
40
41 /* dmm */
42 static struct omap_hwmod dra7xx_dmm_hwmod = {
43 .name = "dmm",
44 .class = &dra7xx_dmm_hwmod_class,
45 .clkdm_name = "emif_clkdm",
46 .prcm = {
47 .omap4 = {
48 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
49 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
50 },
51 },
52 };
53
54 /*
55 * 'l3' class
56 * instance(s): l3_instr, l3_main_1, l3_main_2
57 */
58 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
59 .name = "l3",
60 };
61
62 /* l3_instr */
63 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
64 .name = "l3_instr",
65 .class = &dra7xx_l3_hwmod_class,
66 .clkdm_name = "l3instr_clkdm",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
70 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
71 .modulemode = MODULEMODE_HWCTRL,
72 },
73 },
74 };
75
76 /* l3_main_1 */
77 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
78 .name = "l3_main_1",
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3main1_clkdm",
81 .prcm = {
82 .omap4 = {
83 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
85 },
86 },
87 };
88
89 /* l3_main_2 */
90 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
91 .name = "l3_main_2",
92 .class = &dra7xx_l3_hwmod_class,
93 .clkdm_name = "l3instr_clkdm",
94 .prcm = {
95 .omap4 = {
96 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
97 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
98 .modulemode = MODULEMODE_HWCTRL,
99 },
100 },
101 };
102
103 /*
104 * 'l4' class
105 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
106 */
107 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
108 .name = "l4",
109 };
110
111 /* l4_cfg */
112 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
113 .name = "l4_cfg",
114 .class = &dra7xx_l4_hwmod_class,
115 .clkdm_name = "l4cfg_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
119 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
120 },
121 },
122 };
123
124 /* l4_per1 */
125 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
126 .name = "l4_per1",
127 .class = &dra7xx_l4_hwmod_class,
128 .clkdm_name = "l4per_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
133 },
134 },
135 };
136
137 /* l4_per2 */
138 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
139 .name = "l4_per2",
140 .class = &dra7xx_l4_hwmod_class,
141 .clkdm_name = "l4per2_clkdm",
142 .prcm = {
143 .omap4 = {
144 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
145 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
146 },
147 },
148 };
149
150 /* l4_per3 */
151 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
152 .name = "l4_per3",
153 .class = &dra7xx_l4_hwmod_class,
154 .clkdm_name = "l4per3_clkdm",
155 .prcm = {
156 .omap4 = {
157 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
158 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
159 },
160 },
161 };
162
163 /* l4_wkup */
164 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
165 .name = "l4_wkup",
166 .class = &dra7xx_l4_hwmod_class,
167 .clkdm_name = "wkupaon_clkdm",
168 .prcm = {
169 .omap4 = {
170 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
171 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
172 },
173 },
174 };
175
176 /*
177 * 'atl' class
178 *
179 */
180
181 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
182 .name = "atl",
183 };
184
185 /* atl */
186 static struct omap_hwmod dra7xx_atl_hwmod = {
187 .name = "atl",
188 .class = &dra7xx_atl_hwmod_class,
189 .clkdm_name = "atl_clkdm",
190 .main_clk = "atl_gfclk_mux",
191 .prcm = {
192 .omap4 = {
193 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
194 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
195 .modulemode = MODULEMODE_SWCTRL,
196 },
197 },
198 };
199
200 /*
201 * 'bb2d' class
202 *
203 */
204
205 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
206 .name = "bb2d",
207 };
208
209 /* bb2d */
210 static struct omap_hwmod dra7xx_bb2d_hwmod = {
211 .name = "bb2d",
212 .class = &dra7xx_bb2d_hwmod_class,
213 .clkdm_name = "dss_clkdm",
214 .main_clk = "dpll_core_h24x2_ck",
215 .prcm = {
216 .omap4 = {
217 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
218 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
219 .modulemode = MODULEMODE_SWCTRL,
220 },
221 },
222 };
223
224 /*
225 * 'counter' class
226 *
227 */
228
229 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
230 .rev_offs = 0x0000,
231 .sysc_offs = 0x0010,
232 .sysc_flags = SYSC_HAS_SIDLEMODE,
233 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
234 SIDLE_SMART_WKUP),
235 .sysc_fields = &omap_hwmod_sysc_type1,
236 };
237
238 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
239 .name = "counter",
240 .sysc = &dra7xx_counter_sysc,
241 };
242
243 /* counter_32k */
244 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
245 .name = "counter_32k",
246 .class = &dra7xx_counter_hwmod_class,
247 .clkdm_name = "wkupaon_clkdm",
248 .flags = HWMOD_SWSUP_SIDLE,
249 .main_clk = "wkupaon_iclk_mux",
250 .prcm = {
251 .omap4 = {
252 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
253 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
254 },
255 },
256 };
257
258 /*
259 * 'ctrl_module' class
260 *
261 */
262
263 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
264 .name = "ctrl_module",
265 };
266
267 /* ctrl_module_wkup */
268 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
269 .name = "ctrl_module_wkup",
270 .class = &dra7xx_ctrl_module_hwmod_class,
271 .clkdm_name = "wkupaon_clkdm",
272 .prcm = {
273 .omap4 = {
274 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
275 },
276 },
277 };
278
279 /*
280 * 'gpmc' class
281 *
282 */
283
284 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
285 .rev_offs = 0x0000,
286 .sysc_offs = 0x0010,
287 .syss_offs = 0x0014,
288 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
289 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
290 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
291 .sysc_fields = &omap_hwmod_sysc_type1,
292 };
293
294 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
295 .name = "gpmc",
296 .sysc = &dra7xx_gpmc_sysc,
297 };
298
299 /* gpmc */
300
301 static struct omap_hwmod dra7xx_gpmc_hwmod = {
302 .name = "gpmc",
303 .class = &dra7xx_gpmc_hwmod_class,
304 .clkdm_name = "l3main1_clkdm",
305 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
306 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
307 .main_clk = "l3_iclk_div",
308 .prcm = {
309 .omap4 = {
310 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
311 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
312 .modulemode = MODULEMODE_HWCTRL,
313 },
314 },
315 };
316
317
318
319 /*
320 * 'mpu' class
321 *
322 */
323
324 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
325 .name = "mpu",
326 };
327
328 /* mpu */
329 static struct omap_hwmod dra7xx_mpu_hwmod = {
330 .name = "mpu",
331 .class = &dra7xx_mpu_hwmod_class,
332 .clkdm_name = "mpu_clkdm",
333 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
334 .main_clk = "dpll_mpu_m2_ck",
335 .prcm = {
336 .omap4 = {
337 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
338 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
339 },
340 },
341 };
342
343
344 /*
345 * 'PCIE' class
346 *
347 */
348
349 /*
350 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
351 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
352 * associated with an IP automatically leaving the driver to handle that
353 * by itself. This does not work for PCIeSS which needs the reset lines
354 * deasserted for the driver to start accessing registers.
355 *
356 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
357 * lines after asserting them.
358 */
359 int dra7xx_pciess_reset(struct omap_hwmod *oh)
360 {
361 int i;
362
363 for (i = 0; i < oh->rst_lines_cnt; i++) {
364 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
365 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
366 }
367
368 return 0;
369 }
370
371 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
372 .name = "pcie",
373 .reset = dra7xx_pciess_reset,
374 };
375
376 /* pcie1 */
377 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
378 { .name = "pcie", .rst_shift = 0 },
379 };
380
381 static struct omap_hwmod dra7xx_pciess1_hwmod = {
382 .name = "pcie1",
383 .class = &dra7xx_pciess_hwmod_class,
384 .clkdm_name = "pcie_clkdm",
385 .rst_lines = dra7xx_pciess1_resets,
386 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
387 .main_clk = "l4_root_clk_div",
388 .prcm = {
389 .omap4 = {
390 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
391 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
392 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
393 .modulemode = MODULEMODE_SWCTRL,
394 },
395 },
396 };
397
398 /* pcie2 */
399 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
400 { .name = "pcie", .rst_shift = 1 },
401 };
402
403 /* pcie2 */
404 static struct omap_hwmod dra7xx_pciess2_hwmod = {
405 .name = "pcie2",
406 .class = &dra7xx_pciess_hwmod_class,
407 .clkdm_name = "pcie_clkdm",
408 .rst_lines = dra7xx_pciess2_resets,
409 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
410 .main_clk = "l4_root_clk_div",
411 .prcm = {
412 .omap4 = {
413 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
414 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
415 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
416 .modulemode = MODULEMODE_SWCTRL,
417 },
418 },
419 };
420
421 /*
422 * 'qspi' class
423 *
424 */
425
426 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
427 .rev_offs = 0,
428 .sysc_offs = 0x0010,
429 .sysc_flags = SYSC_HAS_SIDLEMODE,
430 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
431 SIDLE_SMART_WKUP),
432 .sysc_fields = &omap_hwmod_sysc_type2,
433 };
434
435 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
436 .name = "qspi",
437 .sysc = &dra7xx_qspi_sysc,
438 };
439
440 /* qspi */
441 static struct omap_hwmod dra7xx_qspi_hwmod = {
442 .name = "qspi",
443 .class = &dra7xx_qspi_hwmod_class,
444 .clkdm_name = "l4per2_clkdm",
445 .main_clk = "qspi_gfclk_div",
446 .prcm = {
447 .omap4 = {
448 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
449 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
450 .modulemode = MODULEMODE_SWCTRL,
451 },
452 },
453 };
454
455 /*
456 * 'rtcss' class
457 *
458 */
459 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
460 .rev_offs = 0x0074,
461 .sysc_offs = 0x0078,
462 .sysc_flags = SYSC_HAS_SIDLEMODE,
463 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
464 SIDLE_SMART_WKUP),
465 .sysc_fields = &omap_hwmod_sysc_type3,
466 };
467
468 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
469 .name = "rtcss",
470 .sysc = &dra7xx_rtcss_sysc,
471 .unlock = &omap_hwmod_rtc_unlock,
472 .lock = &omap_hwmod_rtc_lock,
473 };
474
475 /* rtcss */
476 static struct omap_hwmod dra7xx_rtcss_hwmod = {
477 .name = "rtcss",
478 .class = &dra7xx_rtcss_hwmod_class,
479 .clkdm_name = "rtc_clkdm",
480 .main_clk = "sys_32k_ck",
481 .prcm = {
482 .omap4 = {
483 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
484 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
485 .modulemode = MODULEMODE_SWCTRL,
486 },
487 },
488 };
489
490 /*
491 * 'sata' class
492 *
493 */
494
495 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
496 .rev_offs = 0x00fc,
497 .sysc_offs = 0x0000,
498 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
499 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
500 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
501 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
502 .sysc_fields = &omap_hwmod_sysc_type2,
503 };
504
505 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
506 .name = "sata",
507 .sysc = &dra7xx_sata_sysc,
508 };
509
510 /* sata */
511
512 static struct omap_hwmod dra7xx_sata_hwmod = {
513 .name = "sata",
514 .class = &dra7xx_sata_hwmod_class,
515 .clkdm_name = "l3init_clkdm",
516 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
517 .main_clk = "func_48m_fclk",
518 .mpu_rt_idx = 1,
519 .prcm = {
520 .omap4 = {
521 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
522 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
523 .modulemode = MODULEMODE_SWCTRL,
524 },
525 },
526 };
527
528 /*
529 * 'timer' class
530 *
531 * This class contains several variants: ['timer_1ms', 'timer_secure',
532 * 'timer']
533 */
534
535 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
536 .rev_offs = 0x0000,
537 .sysc_offs = 0x0010,
538 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
539 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
541 SIDLE_SMART_WKUP),
542 .sysc_fields = &omap_hwmod_sysc_type2,
543 };
544
545 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
546 .name = "timer",
547 .sysc = &dra7xx_timer_1ms_sysc,
548 };
549
550 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
551 .rev_offs = 0x0000,
552 .sysc_offs = 0x0010,
553 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
554 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
556 SIDLE_SMART_WKUP),
557 .sysc_fields = &omap_hwmod_sysc_type2,
558 };
559
560 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
561 .name = "timer",
562 .sysc = &dra7xx_timer_sysc,
563 };
564
565 /* timer1 */
566 static struct omap_hwmod dra7xx_timer1_hwmod = {
567 .name = "timer1",
568 .class = &dra7xx_timer_1ms_hwmod_class,
569 .clkdm_name = "wkupaon_clkdm",
570 .main_clk = "timer1_gfclk_mux",
571 .prcm = {
572 .omap4 = {
573 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
574 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
575 .modulemode = MODULEMODE_SWCTRL,
576 },
577 },
578 };
579
580 /* timer2 */
581 static struct omap_hwmod dra7xx_timer2_hwmod = {
582 .name = "timer2",
583 .class = &dra7xx_timer_1ms_hwmod_class,
584 .clkdm_name = "l4per_clkdm",
585 .main_clk = "timer2_gfclk_mux",
586 .prcm = {
587 .omap4 = {
588 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
589 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
590 .modulemode = MODULEMODE_SWCTRL,
591 },
592 },
593 };
594
595 /* timer3 */
596 static struct omap_hwmod dra7xx_timer3_hwmod = {
597 .name = "timer3",
598 .class = &dra7xx_timer_hwmod_class,
599 .clkdm_name = "l4per_clkdm",
600 .main_clk = "timer3_gfclk_mux",
601 .prcm = {
602 .omap4 = {
603 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
604 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
605 .modulemode = MODULEMODE_SWCTRL,
606 },
607 },
608 };
609
610 /* timer4 */
611 static struct omap_hwmod dra7xx_timer4_hwmod = {
612 .name = "timer4",
613 .class = &dra7xx_timer_hwmod_class,
614 .clkdm_name = "l4per_clkdm",
615 .main_clk = "timer4_gfclk_mux",
616 .prcm = {
617 .omap4 = {
618 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
619 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
620 .modulemode = MODULEMODE_SWCTRL,
621 },
622 },
623 };
624
625 /*
626 * 'usb_otg_ss' class
627 *
628 */
629
630 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
631 .rev_offs = 0x0000,
632 .sysc_offs = 0x0010,
633 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
634 SYSC_HAS_SIDLEMODE),
635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
636 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
637 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
638 .sysc_fields = &omap_hwmod_sysc_type2,
639 };
640
641 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
642 .name = "usb_otg_ss",
643 .sysc = &dra7xx_usb_otg_ss_sysc,
644 };
645
646 /* usb_otg_ss1 */
647 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
648 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
649 };
650
651 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
652 .name = "usb_otg_ss1",
653 .class = &dra7xx_usb_otg_ss_hwmod_class,
654 .clkdm_name = "l3init_clkdm",
655 .main_clk = "dpll_core_h13x2_ck",
656 .flags = HWMOD_CLKDM_NOAUTO,
657 .prcm = {
658 .omap4 = {
659 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
660 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
661 .modulemode = MODULEMODE_HWCTRL,
662 },
663 },
664 .opt_clks = usb_otg_ss1_opt_clks,
665 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
666 };
667
668 /* usb_otg_ss2 */
669 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
670 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
671 };
672
673 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
674 .name = "usb_otg_ss2",
675 .class = &dra7xx_usb_otg_ss_hwmod_class,
676 .clkdm_name = "l3init_clkdm",
677 .main_clk = "dpll_core_h13x2_ck",
678 .flags = HWMOD_CLKDM_NOAUTO,
679 .prcm = {
680 .omap4 = {
681 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
682 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
683 .modulemode = MODULEMODE_HWCTRL,
684 },
685 },
686 .opt_clks = usb_otg_ss2_opt_clks,
687 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
688 };
689
690 /* usb_otg_ss3 */
691 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
692 .name = "usb_otg_ss3",
693 .class = &dra7xx_usb_otg_ss_hwmod_class,
694 .clkdm_name = "l3init_clkdm",
695 .main_clk = "dpll_core_h13x2_ck",
696 .prcm = {
697 .omap4 = {
698 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
699 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
700 .modulemode = MODULEMODE_HWCTRL,
701 },
702 },
703 };
704
705 /* usb_otg_ss4 */
706 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
707 .name = "usb_otg_ss4",
708 .class = &dra7xx_usb_otg_ss_hwmod_class,
709 .clkdm_name = "l3init_clkdm",
710 .main_clk = "dpll_core_h13x2_ck",
711 .prcm = {
712 .omap4 = {
713 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
714 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
715 .modulemode = MODULEMODE_HWCTRL,
716 },
717 },
718 };
719
720 /*
721 * 'vcp' class
722 *
723 */
724
725 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
726 .name = "vcp",
727 };
728
729 /* vcp1 */
730 static struct omap_hwmod dra7xx_vcp1_hwmod = {
731 .name = "vcp1",
732 .class = &dra7xx_vcp_hwmod_class,
733 .clkdm_name = "l3main1_clkdm",
734 .main_clk = "l3_iclk_div",
735 .prcm = {
736 .omap4 = {
737 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
738 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
739 },
740 },
741 };
742
743 /* vcp2 */
744 static struct omap_hwmod dra7xx_vcp2_hwmod = {
745 .name = "vcp2",
746 .class = &dra7xx_vcp_hwmod_class,
747 .clkdm_name = "l3main1_clkdm",
748 .main_clk = "l3_iclk_div",
749 .prcm = {
750 .omap4 = {
751 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
752 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
753 },
754 },
755 };
756
757
758
759 /*
760 * Interfaces
761 */
762
763 /* l3_main_1 -> dmm */
764 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
765 .master = &dra7xx_l3_main_1_hwmod,
766 .slave = &dra7xx_dmm_hwmod,
767 .clk = "l3_iclk_div",
768 .user = OCP_USER_SDMA,
769 };
770
771 /* l3_main_2 -> l3_instr */
772 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
773 .master = &dra7xx_l3_main_2_hwmod,
774 .slave = &dra7xx_l3_instr_hwmod,
775 .clk = "l3_iclk_div",
776 .user = OCP_USER_MPU | OCP_USER_SDMA,
777 };
778
779 /* l4_cfg -> l3_main_1 */
780 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
781 .master = &dra7xx_l4_cfg_hwmod,
782 .slave = &dra7xx_l3_main_1_hwmod,
783 .clk = "l3_iclk_div",
784 .user = OCP_USER_MPU | OCP_USER_SDMA,
785 };
786
787 /* mpu -> l3_main_1 */
788 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
789 .master = &dra7xx_mpu_hwmod,
790 .slave = &dra7xx_l3_main_1_hwmod,
791 .clk = "l3_iclk_div",
792 .user = OCP_USER_MPU,
793 };
794
795 /* l3_main_1 -> l3_main_2 */
796 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
797 .master = &dra7xx_l3_main_1_hwmod,
798 .slave = &dra7xx_l3_main_2_hwmod,
799 .clk = "l3_iclk_div",
800 .user = OCP_USER_MPU,
801 };
802
803 /* l4_cfg -> l3_main_2 */
804 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
805 .master = &dra7xx_l4_cfg_hwmod,
806 .slave = &dra7xx_l3_main_2_hwmod,
807 .clk = "l3_iclk_div",
808 .user = OCP_USER_MPU | OCP_USER_SDMA,
809 };
810
811 /* l3_main_1 -> l4_cfg */
812 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
813 .master = &dra7xx_l3_main_1_hwmod,
814 .slave = &dra7xx_l4_cfg_hwmod,
815 .clk = "l3_iclk_div",
816 .user = OCP_USER_MPU | OCP_USER_SDMA,
817 };
818
819 /* l3_main_1 -> l4_per1 */
820 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
821 .master = &dra7xx_l3_main_1_hwmod,
822 .slave = &dra7xx_l4_per1_hwmod,
823 .clk = "l3_iclk_div",
824 .user = OCP_USER_MPU | OCP_USER_SDMA,
825 };
826
827 /* l3_main_1 -> l4_per2 */
828 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
829 .master = &dra7xx_l3_main_1_hwmod,
830 .slave = &dra7xx_l4_per2_hwmod,
831 .clk = "l3_iclk_div",
832 .user = OCP_USER_MPU | OCP_USER_SDMA,
833 };
834
835 /* l3_main_1 -> l4_per3 */
836 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
837 .master = &dra7xx_l3_main_1_hwmod,
838 .slave = &dra7xx_l4_per3_hwmod,
839 .clk = "l3_iclk_div",
840 .user = OCP_USER_MPU | OCP_USER_SDMA,
841 };
842
843 /* l3_main_1 -> l4_wkup */
844 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
845 .master = &dra7xx_l3_main_1_hwmod,
846 .slave = &dra7xx_l4_wkup_hwmod,
847 .clk = "wkupaon_iclk_mux",
848 .user = OCP_USER_MPU | OCP_USER_SDMA,
849 };
850
851 /* l4_per2 -> atl */
852 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
853 .master = &dra7xx_l4_per2_hwmod,
854 .slave = &dra7xx_atl_hwmod,
855 .clk = "l3_iclk_div",
856 .user = OCP_USER_MPU | OCP_USER_SDMA,
857 };
858
859 /* l3_main_1 -> bb2d */
860 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
861 .master = &dra7xx_l3_main_1_hwmod,
862 .slave = &dra7xx_bb2d_hwmod,
863 .clk = "l3_iclk_div",
864 .user = OCP_USER_MPU | OCP_USER_SDMA,
865 };
866
867 /* l4_wkup -> counter_32k */
868 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
869 .master = &dra7xx_l4_wkup_hwmod,
870 .slave = &dra7xx_counter_32k_hwmod,
871 .clk = "wkupaon_iclk_mux",
872 .user = OCP_USER_MPU | OCP_USER_SDMA,
873 };
874
875 /* l4_wkup -> ctrl_module_wkup */
876 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
877 .master = &dra7xx_l4_wkup_hwmod,
878 .slave = &dra7xx_ctrl_module_wkup_hwmod,
879 .clk = "wkupaon_iclk_mux",
880 .user = OCP_USER_MPU | OCP_USER_SDMA,
881 };
882
883 /* l3_main_1 -> gpmc */
884 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
885 .master = &dra7xx_l3_main_1_hwmod,
886 .slave = &dra7xx_gpmc_hwmod,
887 .clk = "l3_iclk_div",
888 .user = OCP_USER_MPU | OCP_USER_SDMA,
889 };
890
891 /* l4_cfg -> mpu */
892 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
893 .master = &dra7xx_l4_cfg_hwmod,
894 .slave = &dra7xx_mpu_hwmod,
895 .clk = "l3_iclk_div",
896 .user = OCP_USER_MPU | OCP_USER_SDMA,
897 };
898
899 /* l3_main_1 -> pciess1 */
900 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
901 .master = &dra7xx_l3_main_1_hwmod,
902 .slave = &dra7xx_pciess1_hwmod,
903 .clk = "l3_iclk_div",
904 .user = OCP_USER_MPU | OCP_USER_SDMA,
905 };
906
907 /* l4_cfg -> pciess1 */
908 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
909 .master = &dra7xx_l4_cfg_hwmod,
910 .slave = &dra7xx_pciess1_hwmod,
911 .clk = "l4_root_clk_div",
912 .user = OCP_USER_MPU | OCP_USER_SDMA,
913 };
914
915 /* l3_main_1 -> pciess2 */
916 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
917 .master = &dra7xx_l3_main_1_hwmod,
918 .slave = &dra7xx_pciess2_hwmod,
919 .clk = "l3_iclk_div",
920 .user = OCP_USER_MPU | OCP_USER_SDMA,
921 };
922
923 /* l4_cfg -> pciess2 */
924 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
925 .master = &dra7xx_l4_cfg_hwmod,
926 .slave = &dra7xx_pciess2_hwmod,
927 .clk = "l4_root_clk_div",
928 .user = OCP_USER_MPU | OCP_USER_SDMA,
929 };
930
931 /* l3_main_1 -> qspi */
932 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
933 .master = &dra7xx_l3_main_1_hwmod,
934 .slave = &dra7xx_qspi_hwmod,
935 .clk = "l3_iclk_div",
936 .user = OCP_USER_MPU | OCP_USER_SDMA,
937 };
938
939 /* l4_per3 -> rtcss */
940 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
941 .master = &dra7xx_l4_per3_hwmod,
942 .slave = &dra7xx_rtcss_hwmod,
943 .clk = "l4_root_clk_div",
944 .user = OCP_USER_MPU | OCP_USER_SDMA,
945 };
946
947 /* l4_cfg -> sata */
948 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
949 .master = &dra7xx_l4_cfg_hwmod,
950 .slave = &dra7xx_sata_hwmod,
951 .clk = "l3_iclk_div",
952 .user = OCP_USER_MPU | OCP_USER_SDMA,
953 };
954
955 /* l4_wkup -> timer1 */
956 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
957 .master = &dra7xx_l4_wkup_hwmod,
958 .slave = &dra7xx_timer1_hwmod,
959 .clk = "wkupaon_iclk_mux",
960 .user = OCP_USER_MPU | OCP_USER_SDMA,
961 };
962
963 /* l4_per1 -> timer2 */
964 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
965 .master = &dra7xx_l4_per1_hwmod,
966 .slave = &dra7xx_timer2_hwmod,
967 .clk = "l3_iclk_div",
968 .user = OCP_USER_MPU | OCP_USER_SDMA,
969 };
970
971 /* l4_per1 -> timer3 */
972 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
973 .master = &dra7xx_l4_per1_hwmod,
974 .slave = &dra7xx_timer3_hwmod,
975 .clk = "l3_iclk_div",
976 .user = OCP_USER_MPU | OCP_USER_SDMA,
977 };
978
979 /* l4_per1 -> timer4 */
980 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
981 .master = &dra7xx_l4_per1_hwmod,
982 .slave = &dra7xx_timer4_hwmod,
983 .clk = "l3_iclk_div",
984 .user = OCP_USER_MPU | OCP_USER_SDMA,
985 };
986
987 /* l4_per3 -> usb_otg_ss1 */
988 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
989 .master = &dra7xx_l4_per3_hwmod,
990 .slave = &dra7xx_usb_otg_ss1_hwmod,
991 .clk = "dpll_core_h13x2_ck",
992 .user = OCP_USER_MPU | OCP_USER_SDMA,
993 };
994
995 /* l4_per3 -> usb_otg_ss2 */
996 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
997 .master = &dra7xx_l4_per3_hwmod,
998 .slave = &dra7xx_usb_otg_ss2_hwmod,
999 .clk = "dpll_core_h13x2_ck",
1000 .user = OCP_USER_MPU | OCP_USER_SDMA,
1001 };
1002
1003 /* l4_per3 -> usb_otg_ss3 */
1004 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
1005 .master = &dra7xx_l4_per3_hwmod,
1006 .slave = &dra7xx_usb_otg_ss3_hwmod,
1007 .clk = "dpll_core_h13x2_ck",
1008 .user = OCP_USER_MPU | OCP_USER_SDMA,
1009 };
1010
1011 /* l4_per3 -> usb_otg_ss4 */
1012 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
1013 .master = &dra7xx_l4_per3_hwmod,
1014 .slave = &dra7xx_usb_otg_ss4_hwmod,
1015 .clk = "dpll_core_h13x2_ck",
1016 .user = OCP_USER_MPU | OCP_USER_SDMA,
1017 };
1018
1019 /* l3_main_1 -> vcp1 */
1020 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
1021 .master = &dra7xx_l3_main_1_hwmod,
1022 .slave = &dra7xx_vcp1_hwmod,
1023 .clk = "l3_iclk_div",
1024 .user = OCP_USER_MPU | OCP_USER_SDMA,
1025 };
1026
1027 /* l4_per2 -> vcp1 */
1028 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
1029 .master = &dra7xx_l4_per2_hwmod,
1030 .slave = &dra7xx_vcp1_hwmod,
1031 .clk = "l3_iclk_div",
1032 .user = OCP_USER_MPU | OCP_USER_SDMA,
1033 };
1034
1035 /* l3_main_1 -> vcp2 */
1036 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
1037 .master = &dra7xx_l3_main_1_hwmod,
1038 .slave = &dra7xx_vcp2_hwmod,
1039 .clk = "l3_iclk_div",
1040 .user = OCP_USER_MPU | OCP_USER_SDMA,
1041 };
1042
1043 /* l4_per2 -> vcp2 */
1044 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
1045 .master = &dra7xx_l4_per2_hwmod,
1046 .slave = &dra7xx_vcp2_hwmod,
1047 .clk = "l3_iclk_div",
1048 .user = OCP_USER_MPU | OCP_USER_SDMA,
1049 };
1050
1051 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
1052 &dra7xx_l3_main_1__dmm,
1053 &dra7xx_l3_main_2__l3_instr,
1054 &dra7xx_l4_cfg__l3_main_1,
1055 &dra7xx_mpu__l3_main_1,
1056 &dra7xx_l3_main_1__l3_main_2,
1057 &dra7xx_l4_cfg__l3_main_2,
1058 &dra7xx_l3_main_1__l4_cfg,
1059 &dra7xx_l3_main_1__l4_per1,
1060 &dra7xx_l3_main_1__l4_per2,
1061 &dra7xx_l3_main_1__l4_per3,
1062 &dra7xx_l3_main_1__l4_wkup,
1063 &dra7xx_l4_per2__atl,
1064 &dra7xx_l3_main_1__bb2d,
1065 &dra7xx_l4_wkup__counter_32k,
1066 &dra7xx_l4_wkup__ctrl_module_wkup,
1067 &dra7xx_l3_main_1__gpmc,
1068 &dra7xx_l4_cfg__mpu,
1069 &dra7xx_l3_main_1__pciess1,
1070 &dra7xx_l4_cfg__pciess1,
1071 &dra7xx_l3_main_1__pciess2,
1072 &dra7xx_l4_cfg__pciess2,
1073 &dra7xx_l3_main_1__qspi,
1074 &dra7xx_l4_cfg__sata,
1075 &dra7xx_l4_wkup__timer1,
1076 &dra7xx_l4_per1__timer2,
1077 &dra7xx_l4_per1__timer3,
1078 &dra7xx_l4_per1__timer4,
1079 &dra7xx_l4_per3__usb_otg_ss1,
1080 &dra7xx_l4_per3__usb_otg_ss2,
1081 &dra7xx_l4_per3__usb_otg_ss3,
1082 &dra7xx_l3_main_1__vcp1,
1083 &dra7xx_l4_per2__vcp1,
1084 &dra7xx_l3_main_1__vcp2,
1085 &dra7xx_l4_per2__vcp2,
1086 NULL,
1087 };
1088
1089 /* SoC variant specific hwmod links */
1090 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
1091 &dra7xx_l4_per3__usb_otg_ss4,
1092 NULL,
1093 };
1094
1095 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
1096 NULL,
1097 };
1098
1099 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
1100 &dra7xx_l4_per3__usb_otg_ss4,
1101 NULL,
1102 };
1103
1104 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
1105 NULL,
1106 };
1107
1108 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
1109 &dra7xx_l4_per3__rtcss,
1110 NULL,
1111 };
1112
1113 int __init dra7xx_hwmod_init(void)
1114 {
1115 int ret;
1116
1117 omap_hwmod_init();
1118 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
1119
1120 if (!ret && soc_is_dra74x()) {
1121 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
1122 if (!ret)
1123 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1124 } else if (!ret && soc_is_dra72x()) {
1125 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
1126 if (!ret && !of_machine_is_compatible("ti,dra718"))
1127 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1128 } else if (!ret && soc_is_dra76x()) {
1129 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
1130
1131 if (!ret && soc_is_dra76x_acd()) {
1132 ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
1133 } else if (!ret && soc_is_dra76x_abz()) {
1134 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
1135 }
1136 }
1137
1138 return ret;
1139 }
Linux with added FPC-III support