arch/arm/mach-sa1100/include/mach/nanoengine.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * arch/arm/mach-sa1100/include/mach/nanoengine.h
   4  *
   5  * This file contains the hardware specific definitions for nanoEngine.
   6  * Only include this file from SA1100-specific files.
   7  *
   8  * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
   9  */
  10 #ifndef __ASM_ARCH_NANOENGINE_H
  11 #define __ASM_ARCH_NANOENGINE_H
  12
  13 #include <mach/irqs.h>
  14
  15 #define GPIO_PC_READY0  11 /* ready for socket 0 (active high)*/
  16 #define GPIO_PC_READY1  12 /* ready for socket 1 (active high) */
  17 #define GPIO_PC_CD0     13 /* detect for socket 0 (active low) */
  18 #define GPIO_PC_CD1     14 /* detect for socket 1 (active low) */
  19 #define GPIO_PC_RESET0  15 /* reset socket 0 */
  20 #define GPIO_PC_RESET1  16 /* reset socket 1 */
  21
  22 #define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
  23 #define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
  24 #define NANOENGINE_IRQ_GPIO_PC_READY1   IRQ_GPIO12
  25 #define NANOENGINE_IRQ_GPIO_PC_CD0      IRQ_GPIO13
  26 #define NANOENGINE_IRQ_GPIO_PC_CD1      IRQ_GPIO14
  27
  28 /*
  29  * nanoEngine Memory Map:
  30  *
  31  * 0000.0000 - 003F.0000 -   4 MB Flash
  32  * C000.0000 - C1FF.FFFF -  32 MB SDRAM
  33  * 1860.0000 - 186F.FFFF -   1 MB Internal PCI Memory Read/Write
  34  * 18A1.0000 - 18A1.FFFF -  64 KB Internal PCI Config Space
  35  * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
  36  * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
  37  *
  38  */
  39
  40 #define NANO_PCI_MEM_RW_PHYS            0x18600000
  41 #define NANO_PCI_MEM_RW_VIRT            0xf1000000
  42 #define NANO_PCI_MEM_RW_SIZE            SZ_1M
  43 #define NANO_PCI_CONFIG_SPACE_PHYS      0x18A10000
  44 #define NANO_PCI_CONFIG_SPACE_VIRT      0xf2000000
  45 #define NANO_PCI_CONFIG_SPACE_SIZE      SZ_64K
  46
  47 #endif
  48