?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 5.7.7
[linux/fpc-iii.git] / arch / arm / mach-sunxi / mc_smp.c
blob26cbce1353387af67e366c3c03c8995384f8c496
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Chen-Yu Tsai
4 *
5 * Chen-Yu Tsai <wens@csie.org>
6 *
7 * arch/arm/mach-sunxi/mc_smp.c
8 *
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
11 * Cluster cache enable trampoline code adapted from MCPM framework
12 */
13
14 #include <linux/arm-cci.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/delay.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/irqchip/arm-gic.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/smp.h>
24
25 #include <asm/cacheflush.h>
26 #include <asm/cp15.h>
27 #include <asm/cputype.h>
28 #include <asm/idmap.h>
29 #include <asm/smp_plat.h>
30 #include <asm/suspend.h>
31
32 #define SUNXI_CPUS_PER_CLUSTER 4
33 #define SUNXI_NR_CLUSTERS 2
34
35 #define POLL_USEC 100
36 #define TIMEOUT_USEC 100000
37
38 #define CPUCFG_CX_CTRL_REG0(c) (0x10 * (c))
39 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n)
40 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL 0xf
41 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4)
42 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0)
43 #define CPUCFG_CX_CTRL_REG1(c) (0x10 * (c) + 0x4)
44 #define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0)
45 #define CPUCFG_CX_STATUS(c) (0x30 + 0x4 * (c))
46 #define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n))
47 #define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0)
48 #define CPUCFG_CX_RST_CTRL(c) (0x80 + 0x4 * (c))
49 #define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24)
50 #define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n))
51 #define CPUCFG_CX_RST_CTRL_ETM_RST_ALL (0xf << 20)
52 #define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n))
53 #define CPUCFG_CX_RST_CTRL_DBG_RST_ALL (0xf << 16)
54 #define CPUCFG_CX_RST_CTRL_H_RST BIT(12)
55 #define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
56 #define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
57 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
58 #define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
59
60 #define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c))
61 #define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
62 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
63 #define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
64 /* The power off register for clusters are different from a80 and a83t */
65 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0)
66 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4)
67 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
68 #define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu))
69 #define PRCM_CPU_SOFT_ENTRY_REG 0x164
70
71 /* R_CPUCFG registers, specific to sun8i-a83t */
72 #define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
73 #define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n)
74 #define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4
75
76 #define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F
77 #define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A
78
79 static void __iomem *cpucfg_base;
80 static void __iomem *prcm_base;
81 static void __iomem *sram_b_smp_base;
82 static void __iomem *r_cpucfg_base;
83
84 extern void sunxi_mc_smp_secondary_startup(void);
85 extern void sunxi_mc_smp_resume(void);
86 static bool is_a83t;
87
88 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
89 {
90 struct device_node *node;
91 int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
92 bool is_compatible;
93
94 node = of_cpu_device_node_get(cpu);
95
96 /* In case of_cpu_device_node_get fails */
97 if (!node)
98 node = of_get_cpu_node(cpu, NULL);
99
100 if (!node) {
101 /*
102 * There's no point in returning an error, since we
103 * would be mid way in a core or cluster power sequence.
104 */
105 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
106 __func__, cluster, core);
107
108 return false;
109 }
110
111 is_compatible = of_device_is_compatible(node, "arm,cortex-a15");
112 of_node_put(node);
113 return is_compatible;
114 }
115
116 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
117 bool enable)
118 {
119 u32 reg;
120
121 /* control sequence from Allwinner A80 user manual v1.2 PRCM section */
122 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
123 if (enable) {
124 if (reg == 0x00) {
125 pr_debug("power clamp for cluster %u cpu %u already open\n",
126 cluster, cpu);
127 return 0;
128 }
129
130 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
131 udelay(10);
132 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
133 udelay(10);
134 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
135 udelay(10);
136 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
137 udelay(10);
138 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
139 udelay(10);
140 } else {
141 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
142 udelay(10);
143 }
144
145 return 0;
146 }
147
148 static void sunxi_cpu0_hotplug_support_set(bool enable)
149 {
150 if (enable) {
151 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
152 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
153 } else {
154 writel(0x0, sram_b_smp_base);
155 writel(0x0, sram_b_smp_base + 0x4);
156 }
157 }
158
159 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
160 {
161 u32 reg;
162
163 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
164 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
165 return -EINVAL;
166
167 /* Set hotplug support magic flags for cpu0 */
168 if (cluster == 0 && cpu == 0)
169 sunxi_cpu0_hotplug_support_set(true);
170
171 /* assert processor power-on reset */
172 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
173 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
174 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
175
176 if (is_a83t) {
177 /* assert cpu power-on reset */
178 reg = readl(r_cpucfg_base +
179 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
180 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
181 writel(reg, r_cpucfg_base +
182 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
183 udelay(10);
184 }
185
186 /* Cortex-A7: hold L1 reset disable signal low */
187 if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
188 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
189 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu);
190 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
191 }
192
193 /* assert processor related resets */
194 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
195 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
196
197 /*
198 * Allwinner code also asserts resets for NEON on A15. According
199 * to ARM manuals, asserting power-on reset is sufficient.
200 */
201 if (!sunxi_core_is_cortex_a15(cpu, cluster))
202 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
203
204 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
205
206 /* open power switch */
207 sunxi_cpu_power_switch_set(cpu, cluster, true);
208
209 /* Handle A83T bit swap */
210 if (is_a83t) {
211 if (cpu == 0)
212 cpu = 4;
213 }
214
215 /* clear processor power gate */
216 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
217 reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
218 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
219 udelay(20);
220
221 /* Handle A83T bit swap */
222 if (is_a83t) {
223 if (cpu == 4)
224 cpu = 0;
225 }
226
227 /* de-assert processor power-on reset */
228 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
229 reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
230 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
231
232 if (is_a83t) {
233 reg = readl(r_cpucfg_base +
234 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
235 reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
236 writel(reg, r_cpucfg_base +
237 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
238 udelay(10);
239 }
240
241 /* de-assert all processor resets */
242 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
243 reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
244 reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu);
245 if (!sunxi_core_is_cortex_a15(cpu, cluster))
246 reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
247 else
248 reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */
249 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
250
251 return 0;
252 }
253
254 static int sunxi_cluster_powerup(unsigned int cluster)
255 {
256 u32 reg;
257
258 pr_debug("%s: cluster %u\n", __func__, cluster);
259 if (cluster >= SUNXI_NR_CLUSTERS)
260 return -EINVAL;
261
262 /* For A83T, assert cluster cores resets */
263 if (is_a83t) {
264 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
265 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */
266 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
267 udelay(10);
268 }
269
270 /* assert ACINACTM */
271 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
272 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
273 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
274
275 /* assert cluster processor power-on resets */
276 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
277 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
278 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
279
280 /* assert cluster cores resets */
281 if (is_a83t) {
282 reg = readl(r_cpucfg_base +
283 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
284 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
285 writel(reg, r_cpucfg_base +
286 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
287 udelay(10);
288 }
289
290 /* assert cluster resets */
291 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
292 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
293 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL;
294 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
295 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
296
297 /*
298 * Allwinner code also asserts resets for NEON on A15. According
299 * to ARM manuals, asserting power-on reset is sufficient.
300 */
301 if (!sunxi_core_is_cortex_a15(0, cluster))
302 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL;
303
304 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
305
306 /* hold L1/L2 reset disable signals low */
307 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
308 if (sunxi_core_is_cortex_a15(0, cluster)) {
309 /* Cortex-A15: hold L2RSTDISABLE low */
310 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15;
311 } else {
312 /* Cortex-A7: hold L1RSTDISABLE and L2RSTDISABLE low */
313 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL;
314 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7;
315 }
316 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
317
318 /* clear cluster power gate */
319 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
320 if (is_a83t)
321 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
322 else
323 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
324 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
325 udelay(20);
326
327 /* de-assert cluster resets */
328 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
329 reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
330 reg |= CPUCFG_CX_RST_CTRL_H_RST;
331 reg |= CPUCFG_CX_RST_CTRL_L2_RST;
332 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
333
334 /* de-assert ACINACTM */
335 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
336 reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM;
337 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
338
339 return 0;
340 }
341
342 /*
343 * This bit is shared between the initial nocache_trampoline call to
344 * enable CCI-400 and proper cluster cache disable before power down.
345 */
346 static void sunxi_cluster_cache_disable_without_axi(void)
347 {
348 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
349 /*
350 * On the Cortex-A15 we need to disable
351 * L2 prefetching before flushing the cache.
352 */
353 asm volatile(
354 "mcr p15, 1, %0, c15, c0, 3\n"
355 "isb\n"
356 "dsb"
357 : : "r" (0x400));
358 }
359
360 /* Flush all cache levels for this cluster. */
361 v7_exit_coherency_flush(all);
362
363 /*
364 * Disable cluster-level coherency by masking
365 * incoming snoops and DVM messages:
366 */
367 cci_disable_port_by_cpu(read_cpuid_mpidr());
368 }
369
370 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
371 int sunxi_mc_smp_first_comer;
372
373 static DEFINE_SPINLOCK(boot_lock);
374
375 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
376 {
377 int i;
378
379 for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++)
380 if (sunxi_mc_smp_cpu_table[cluster][i])
381 return false;
382 return true;
383 }
384
385 static void sunxi_mc_smp_secondary_init(unsigned int cpu)
386 {
387 /* Clear hotplug support magic flags for cpu0 */
388 if (cpu == 0)
389 sunxi_cpu0_hotplug_support_set(false);
390 }
391
392 static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
393 {
394 unsigned int mpidr, cpu, cluster;
395
396 mpidr = cpu_logical_map(l_cpu);
397 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
398 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
399
400 if (!cpucfg_base)
401 return -ENODEV;
402 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
403 return -EINVAL;
404
405 spin_lock_irq(&boot_lock);
406
407 if (sunxi_mc_smp_cpu_table[cluster][cpu])
408 goto out;
409
410 if (sunxi_mc_smp_cluster_is_down(cluster)) {
411 sunxi_mc_smp_first_comer = true;
412 sunxi_cluster_powerup(cluster);
413 } else {
414 sunxi_mc_smp_first_comer = false;
415 }
416
417 /* This is read by incoming CPUs with their cache and MMU disabled */
418 sync_cache_w(&sunxi_mc_smp_first_comer);
419 sunxi_cpu_powerup(cpu, cluster);
420
421 out:
422 sunxi_mc_smp_cpu_table[cluster][cpu]++;
423 spin_unlock_irq(&boot_lock);
424
425 return 0;
426 }
427
428 #ifdef CONFIG_HOTPLUG_CPU
429 static void sunxi_cluster_cache_disable(void)
430 {
431 unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
432 u32 reg;
433
434 pr_debug("%s: cluster %u\n", __func__, cluster);
435
436 sunxi_cluster_cache_disable_without_axi();
437
438 /* last man standing, assert ACINACTM */
439 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
440 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
441 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
442 }
443
444 static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
445 {
446 unsigned int mpidr, cpu, cluster;
447 bool last_man;
448
449 mpidr = cpu_logical_map(l_cpu);
450 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
451 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
452 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
453
454 spin_lock(&boot_lock);
455 sunxi_mc_smp_cpu_table[cluster][cpu]--;
456 if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
457 /* A power_up request went ahead of us. */
458 pr_debug("%s: aborting due to a power up request\n",
459 __func__);
460 spin_unlock(&boot_lock);
461 return;
462 } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
463 pr_err("Cluster %d CPU%d boots multiple times\n",
464 cluster, cpu);
465 BUG();
466 }
467
468 last_man = sunxi_mc_smp_cluster_is_down(cluster);
469 spin_unlock(&boot_lock);
470
471 gic_cpu_if_down(0);
472 if (last_man)
473 sunxi_cluster_cache_disable();
474 else
475 v7_exit_coherency_flush(louis);
476
477 for (;;)
478 wfi();
479 }
480
481 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
482 {
483 u32 reg;
484 int gating_bit = cpu;
485
486 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
487 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
488 return -EINVAL;
489
490 if (is_a83t && cpu == 0)
491 gating_bit = 4;
492
493 /* gate processor power */
494 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
495 reg |= PRCM_PWROFF_GATING_REG_CORE(gating_bit);
496 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
497 udelay(20);
498
499 /* close power switch */
500 sunxi_cpu_power_switch_set(cpu, cluster, false);
501
502 return 0;
503 }
504
505 static int sunxi_cluster_powerdown(unsigned int cluster)
506 {
507 u32 reg;
508
509 pr_debug("%s: cluster %u\n", __func__, cluster);
510 if (cluster >= SUNXI_NR_CLUSTERS)
511 return -EINVAL;
512
513 /* assert cluster resets or system will hang */
514 pr_debug("%s: assert cluster reset\n", __func__);
515 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
516 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
517 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
518 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
519 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
520
521 /* gate cluster power */
522 pr_debug("%s: gate cluster power\n", __func__);
523 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
524 if (is_a83t)
525 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
526 else
527 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
528 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
529 udelay(20);
530
531 return 0;
532 }
533
534 static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
535 {
536 unsigned int mpidr, cpu, cluster;
537 unsigned int tries, count;
538 int ret = 0;
539 u32 reg;
540
541 mpidr = cpu_logical_map(l_cpu);
542 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
543 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
544
545 /* This should never happen */
546 if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
547 cpu >= SUNXI_CPUS_PER_CLUSTER))
548 return 0;
549
550 /* wait for CPU core to die and enter WFI */
551 count = TIMEOUT_USEC / POLL_USEC;
552 spin_lock_irq(&boot_lock);
553 for (tries = 0; tries < count; tries++) {
554 spin_unlock_irq(&boot_lock);
555 usleep_range(POLL_USEC / 2, POLL_USEC);
556 spin_lock_irq(&boot_lock);
557
558 /*
559 * If the user turns off a bunch of cores at the same
560 * time, the kernel might call cpu_kill before some of
561 * them are ready. This is because boot_lock serializes
562 * both cpu_die and cpu_kill callbacks. Either one could
563 * run first. We should wait for cpu_die to complete.
564 */
565 if (sunxi_mc_smp_cpu_table[cluster][cpu])
566 continue;
567
568 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
569 if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu))
570 break;
571 }
572
573 if (tries >= count) {
574 ret = ETIMEDOUT;
575 goto out;
576 }
577
578 /* power down CPU core */
579 sunxi_cpu_powerdown(cpu, cluster);
580
581 if (!sunxi_mc_smp_cluster_is_down(cluster))
582 goto out;
583
584 /* wait for cluster L2 WFI */
585 ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
586 reg & CPUCFG_CX_STATUS_STANDBYWFIL2,
587 POLL_USEC, TIMEOUT_USEC);
588 if (ret) {
589 /*
590 * Ignore timeout on the cluster. Leaving the cluster on
591 * will not affect system execution, just use a bit more
592 * power. But returning an error here will only confuse
593 * the user as the CPU has already been shutdown.
594 */
595 ret = 0;
596 goto out;
597 }
598
599 /* Power down cluster */
600 sunxi_cluster_powerdown(cluster);
601
602 out:
603 spin_unlock_irq(&boot_lock);
604 pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
605 __func__, cluster, cpu, ret);
606 return !ret;
607 }
608
609 static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
610 {
611 /* CPU0 hotplug not handled for sun8i-a83t */
612 if (is_a83t)
613 if (cpu == 0)
614 return false;
615 return true;
616 }
617 #endif
618
619 static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = {
620 .smp_secondary_init = sunxi_mc_smp_secondary_init,
621 .smp_boot_secondary = sunxi_mc_smp_boot_secondary,
622 #ifdef CONFIG_HOTPLUG_CPU
623 .cpu_die = sunxi_mc_smp_cpu_die,
624 .cpu_kill = sunxi_mc_smp_cpu_kill,
625 .cpu_can_disable = sunxi_mc_smp_cpu_can_disable,
626 #endif
627 };
628
629 static bool __init sunxi_mc_smp_cpu_table_init(void)
630 {
631 unsigned int mpidr, cpu, cluster;
632
633 mpidr = read_cpuid_mpidr();
634 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
635 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
636
637 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
638 pr_err("%s: boot CPU is out of bounds!\n", __func__);
639 return false;
640 }
641 sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
642 return true;
643 }
644
645 /*
646 * Adapted from arch/arm/common/mc_smp_entry.c
647 *
648 * We need the trampoline code to enable CCI-400 on the first cluster
649 */
650 typedef typeof(cpu_reset) phys_reset_t;
651
652 static int __init nocache_trampoline(unsigned long __unused)
653 {
654 phys_reset_t phys_reset;
655
656 setup_mm_for_reboot();
657 sunxi_cluster_cache_disable_without_axi();
658
659 phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
660 phys_reset(__pa_symbol(sunxi_mc_smp_resume), false);
661 BUG();
662 }
663
664 static int __init sunxi_mc_smp_loopback(void)
665 {
666 int ret;
667
668 /*
669 * We're going to soft-restart the current CPU through the
670 * low-level MCPM code by leveraging the suspend/resume
671 * infrastructure. Let's play it safe by using cpu_pm_enter()
672 * in case the CPU init code path resets the VFP or similar.
673 */
674 sunxi_mc_smp_first_comer = true;
675 local_irq_disable();
676 local_fiq_disable();
677 ret = cpu_pm_enter();
678 if (!ret) {
679 ret = cpu_suspend(0, nocache_trampoline);
680 cpu_pm_exit();
681 }
682 local_fiq_enable();
683 local_irq_enable();
684 sunxi_mc_smp_first_comer = false;
685
686 return ret;
687 }
688
689 /*
690 * This holds any device nodes that we requested resources for,
691 * so that we may easily release resources in the error path.
692 */
693 struct sunxi_mc_smp_nodes {
694 struct device_node *prcm_node;
695 struct device_node *cpucfg_node;
696 struct device_node *sram_node;
697 struct device_node *r_cpucfg_node;
698 };
699
700 /* This structure holds SoC-specific bits tied to an enable-method string. */
701 struct sunxi_mc_smp_data {
702 const char *enable_method;
703 int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
704 bool is_a83t;
705 };
706
707 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
708 {
709 of_node_put(nodes->prcm_node);
710 of_node_put(nodes->cpucfg_node);
711 of_node_put(nodes->sram_node);
712 of_node_put(nodes->r_cpucfg_node);
713 memset(nodes, 0, sizeof(*nodes));
714 }
715
716 static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
717 {
718 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
719 "allwinner,sun9i-a80-prcm");
720 if (!nodes->prcm_node) {
721 pr_err("%s: PRCM not available\n", __func__);
722 return -ENODEV;
723 }
724
725 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
726 "allwinner,sun9i-a80-cpucfg");
727 if (!nodes->cpucfg_node) {
728 pr_err("%s: CPUCFG not available\n", __func__);
729 return -ENODEV;
730 }
731
732 nodes->sram_node = of_find_compatible_node(NULL, NULL,
733 "allwinner,sun9i-a80-smp-sram");
734 if (!nodes->sram_node) {
735 pr_err("%s: Secure SRAM not available\n", __func__);
736 return -ENODEV;
737 }
738
739 return 0;
740 }
741
742 static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
743 {
744 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
745 "allwinner,sun8i-a83t-r-ccu");
746 if (!nodes->prcm_node) {
747 pr_err("%s: PRCM not available\n", __func__);
748 return -ENODEV;
749 }
750
751 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
752 "allwinner,sun8i-a83t-cpucfg");
753 if (!nodes->cpucfg_node) {
754 pr_err("%s: CPUCFG not available\n", __func__);
755 return -ENODEV;
756 }
757
758 nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
759 "allwinner,sun8i-a83t-r-cpucfg");
760 if (!nodes->r_cpucfg_node) {
761 pr_err("%s: RCPUCFG not available\n", __func__);
762 return -ENODEV;
763 }
764
765 return 0;
766 }
767
768 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
769 {
770 .enable_method = "allwinner,sun9i-a80-smp",
771 .get_smp_nodes = sun9i_a80_get_smp_nodes,
772 },
773 {
774 .enable_method = "allwinner,sun8i-a83t-smp",
775 .get_smp_nodes = sun8i_a83t_get_smp_nodes,
776 .is_a83t = true,
777 },
778 };
779
780 static int __init sunxi_mc_smp_init(void)
781 {
782 struct sunxi_mc_smp_nodes nodes = { 0 };
783 struct device_node *node;
784 struct resource res;
785 void __iomem *addr;
786 int i, ret;
787
788 /*
789 * Don't bother checking the "cpus" node, as an enable-method
790 * property in that node is undocumented.
791 */
792 node = of_cpu_device_node_get(0);
793 if (!node)
794 return -ENODEV;
795
796 /*
797 * We can't actually use the enable-method magic in the kernel.
798 * Our loopback / trampoline code uses the CPU suspend framework,
799 * which requires the identity mapping be available. It would not
800 * yet be available if we used the .init_cpus or .prepare_cpus
801 * callbacks in smp_operations, which we would use if we were to
802 * use CPU_METHOD_OF_DECLARE
803 */
804 for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
805 ret = of_property_match_string(node, "enable-method",
806 sunxi_mc_smp_data[i].enable_method);
807 if (!ret)
808 break;
809 }
810
811 is_a83t = sunxi_mc_smp_data[i].is_a83t;
812
813 of_node_put(node);
814 if (ret)
815 return -ENODEV;
816
817 if (!sunxi_mc_smp_cpu_table_init())
818 return -EINVAL;
819
820 if (!cci_probed()) {
821 pr_err("%s: CCI-400 not available\n", __func__);
822 return -ENODEV;
823 }
824
825 /* Get needed device tree nodes */
826 ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes);
827 if (ret)
828 goto err_put_nodes;
829
830 /*
831 * Unfortunately we can not request the I/O region for the PRCM.
832 * It is shared with the PRCM clock.
833 */
834 prcm_base = of_iomap(nodes.prcm_node, 0);
835 if (!prcm_base) {
836 pr_err("%s: failed to map PRCM registers\n", __func__);
837 ret = -ENOMEM;
838 goto err_put_nodes;
839 }
840
841 cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0,
842 "sunxi-mc-smp");
843 if (IS_ERR(cpucfg_base)) {
844 ret = PTR_ERR(cpucfg_base);
845 pr_err("%s: failed to map CPUCFG registers: %d\n",
846 __func__, ret);
847 goto err_unmap_prcm;
848 }
849
850 if (is_a83t) {
851 r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
852 0, "sunxi-mc-smp");
853 if (IS_ERR(r_cpucfg_base)) {
854 ret = PTR_ERR(r_cpucfg_base);
855 pr_err("%s: failed to map R-CPUCFG registers\n",
856 __func__);
857 goto err_unmap_release_cpucfg;
858 }
859 } else {
860 sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
861 "sunxi-mc-smp");
862 if (IS_ERR(sram_b_smp_base)) {
863 ret = PTR_ERR(sram_b_smp_base);
864 pr_err("%s: failed to map secure SRAM\n", __func__);
865 goto err_unmap_release_cpucfg;
866 }
867 }
868
869 /* Configure CCI-400 for boot cluster */
870 ret = sunxi_mc_smp_loopback();
871 if (ret) {
872 pr_err("%s: failed to configure boot cluster: %d\n",
873 __func__, ret);
874 goto err_unmap_release_sram_rcpucfg;
875 }
876
877 /* We don't need the device nodes anymore */
878 sunxi_mc_smp_put_nodes(&nodes);
879
880 /* Set the hardware entry point address */
881 if (is_a83t)
882 addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
883 else
884 addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
885 writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
886
887 /* Actually enable multi cluster SMP */
888 smp_set_ops(&sunxi_mc_smp_smp_ops);
889
890 pr_info("sunxi multi cluster SMP support installed\n");
891
892 return 0;
893
894 err_unmap_release_sram_rcpucfg:
895 if (is_a83t) {
896 iounmap(r_cpucfg_base);
897 of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
898 } else {
899 iounmap(sram_b_smp_base);
900 of_address_to_resource(nodes.sram_node, 0, &res);
901 }
902 release_mem_region(res.start, resource_size(&res));
903 err_unmap_release_cpucfg:
904 iounmap(cpucfg_base);
905 of_address_to_resource(nodes.cpucfg_node, 0, &res);
906 release_mem_region(res.start, resource_size(&res));
907 err_unmap_prcm:
908 iounmap(prcm_base);
909 err_put_nodes:
910 sunxi_mc_smp_put_nodes(&nodes);
911 return ret;
912 }
913
914 early_initcall(sunxi_mc_smp_init);
Linux with added FPC-III support