arch/arm/mach-vexpress/dcscb.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
   4  *
   5  * Created by:  Nicolas Pitre, May 2012
   6  * Copyright:   (C) 2012-2013  Linaro Limited
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/io.h>
  12 #include <linux/errno.h>
  13 #include <linux/of_address.h>
  14 #include <linux/vexpress.h>
  15 #include <linux/arm-cci.h>
  16
  17 #include <asm/mcpm.h>
  18 #include <asm/proc-fns.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/cputype.h>
  21 #include <asm/cp15.h>
  22
  23
  24 #define RST_HOLD0       0x0
  25 #define RST_HOLD1       0x4
  26 #define SYS_SWRESET     0x8
  27 #define RST_STAT0       0xc
  28 #define RST_STAT1       0x10
  29 #define EAG_CFG_R       0x20
  30 #define EAG_CFG_W       0x24
  31 #define KFC_CFG_R       0x28
  32 #define KFC_CFG_W       0x2c
  33 #define DCS_CFG_R       0x30
  34
  35 static void __iomem *dcscb_base;
  36 static int dcscb_allcpus_mask[2];
  37
  38 static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster)
  39 {
  40         unsigned int rst_hold, cpumask = (1 << cpu);
  41
  42         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
  43         if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster]))
  44                 return -EINVAL;
  45
  46         rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
  47         rst_hold &= ~(cpumask | (cpumask << 4));
  48         writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
  49         return 0;
  50 }
  51
  52 static int dcscb_cluster_powerup(unsigned int cluster)
  53 {
  54         unsigned int rst_hold;
  55
  56         pr_debug("%s: cluster %u\n", __func__, cluster);
  57         if (cluster >= 2)
  58                 return -EINVAL;
  59
  60         /* remove cluster reset and add individual CPU's reset */
  61         rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
  62         rst_hold &= ~(1 << 8);
  63         rst_hold |= dcscb_allcpus_mask[cluster];
  64         writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
  65         return 0;
  66 }
  67
  68 static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
  69 {
  70         unsigned int rst_hold;
  71
  72         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
  73         BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster]));
  74
  75         rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
  76         rst_hold |= (1 << cpu);
  77         writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
  78 }
  79
  80 static void dcscb_cluster_powerdown_prepare(unsigned int cluster)
  81 {
  82         unsigned int rst_hold;
  83
  84         pr_debug("%s: cluster %u\n", __func__, cluster);
  85         BUG_ON(cluster >= 2);
  86
  87         rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
  88         rst_hold |= (1 << 8);
  89         writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
  90 }
  91
  92 static void dcscb_cpu_cache_disable(void)
  93 {
  94         /* Disable and flush the local CPU cache. */
  95         v7_exit_coherency_flush(louis);
  96 }
  97
  98 static void dcscb_cluster_cache_disable(void)
  99 {
 100         /* Flush all cache levels for this cluster. */
 101         v7_exit_coherency_flush(all);
 102
 103         /*
 104          * A full outer cache flush could be needed at this point
 105          * on platforms with such a cache, depending on where the
 106          * outer cache sits. In some cases the notion of a "last
 107          * cluster standing" would need to be implemented if the
 108          * outer cache is shared across clusters. In any case, when
 109          * the outer cache needs flushing, there is no concurrent
 110          * access to the cache controller to worry about and no
 111          * special locking besides what is already provided by the
 112          * MCPM state machinery is needed.
 113          */
 114
 115         /*
 116          * Disable cluster-level coherency by masking
 117          * incoming snoops and DVM messages:
 118          */
 119         cci_disable_port_by_cpu(read_cpuid_mpidr());
 120 }
 121
 122 static const struct mcpm_platform_ops dcscb_power_ops = {
 123         .cpu_powerup            = dcscb_cpu_powerup,
 124         .cluster_powerup        = dcscb_cluster_powerup,
 125         .cpu_powerdown_prepare  = dcscb_cpu_powerdown_prepare,
 126         .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare,
 127         .cpu_cache_disable      = dcscb_cpu_cache_disable,
 128         .cluster_cache_disable  = dcscb_cluster_cache_disable,
 129 };
 130
 131 extern void dcscb_power_up_setup(unsigned int affinity_level);
 132
 133 static int __init dcscb_init(void)
 134 {
 135         struct device_node *node;
 136         unsigned int cfg;
 137         int ret;
 138
 139         if (!cci_probed())
 140                 return -ENODEV;
 141
 142         node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
 143         if (!node)
 144                 return -ENODEV;
 145         dcscb_base = of_iomap(node, 0);
 146         if (!dcscb_base)
 147                 return -EADDRNOTAVAIL;
 148         cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
 149         dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
 150         dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
 151
 152         ret = mcpm_platform_register(&dcscb_power_ops);
 153         if (!ret)
 154                 ret = mcpm_sync_init(dcscb_power_up_setup);
 155         if (ret) {
 156                 iounmap(dcscb_base);
 157                 return ret;
 158         }
 159
 160         pr_info("VExpress DCSCB support installed\n");
 161
 162         /*
 163          * Future entries into the kernel can now go
 164          * through the cluster entry vectors.
 165          */
 166         vexpress_flags_set(__pa_symbol(mcpm_entry_point));
 167
 168         return 0;
 169 }
 170
 171 early_initcall(dcscb_init);