Linux 5.7.7
[linux/fpc-iii.git] / arch / sh / include / cpu-sh5 / cpu / registers.h
blob372c1e1978b3369837c50f0ec4c48a8ac0ea526e
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_CPU_SH5_REGISTERS_H
3 #define __ASM_SH_CPU_SH5_REGISTERS_H
5 /*
6 * include/asm-sh/cpu-sh5/registers.h
8 * Copyright (C) 2000, 2001 Paolo Alberelli
9 * Copyright (C) 2004 Richard Curnow
12 #ifdef __ASSEMBLY__
13 /* =====================================================================
15 ** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
16 ** Assigns symbolic names to control & target registers.
20 * Define some useful aliases for control registers.
22 #define SR cr0
23 #define SSR cr1
24 #define PSSR cr2
25 /* cr3 UNDEFINED */
26 #define INTEVT cr4
27 #define EXPEVT cr5
28 #define PEXPEVT cr6
29 #define TRA cr7
30 #define SPC cr8
31 #define PSPC cr9
32 #define RESVEC cr10
33 #define VBR cr11
34 /* cr12 UNDEFINED */
35 #define TEA cr13
36 /* cr14-cr15 UNDEFINED */
37 #define DCR cr16
38 #define KCR0 cr17
39 #define KCR1 cr18
40 /* cr19-cr31 UNDEFINED */
41 /* cr32-cr61 RESERVED */
42 #define CTC cr62
43 #define USR cr63
46 * ABI dependent registers (general purpose set)
48 #define RET r2
49 #define ARG1 r2
50 #define ARG2 r3
51 #define ARG3 r4
52 #define ARG4 r5
53 #define ARG5 r6
54 #define ARG6 r7
55 #define SP r15
56 #define LINK r18
57 #define ZERO r63
60 * Status register defines: used only by assembly sources (and
61 * syntax independednt)
63 #define SR_RESET_VAL 0x0000000050008000
64 #define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
65 #define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
67 #if defined (CONFIG_SH64_SR_WATCH)
68 #define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
69 #else
70 #define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
71 #endif
73 #define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
74 #define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
76 #else /* Not __ASSEMBLY__ syntax */
79 ** Stringify reg. name
81 #define __str(x) #x
83 /* Stringify control register names for use in inline assembly */
84 #define __SR __str(SR)
85 #define __SSR __str(SSR)
86 #define __PSSR __str(PSSR)
87 #define __INTEVT __str(INTEVT)
88 #define __EXPEVT __str(EXPEVT)
89 #define __PEXPEVT __str(PEXPEVT)
90 #define __TRA __str(TRA)
91 #define __SPC __str(SPC)
92 #define __PSPC __str(PSPC)
93 #define __RESVEC __str(RESVEC)
94 #define __VBR __str(VBR)
95 #define __TEA __str(TEA)
96 #define __DCR __str(DCR)
97 #define __KCR0 __str(KCR0)
98 #define __KCR1 __str(KCR1)
99 #define __CTC __str(CTC)
100 #define __USR __str(USR)
102 #endif /* __ASSEMBLY__ */
103 #endif /* __ASM_SH_CPU_SH5_REGISTERS_H */