2 * DRAM/SDRAM initialization - alter with care
3 * This file is intended to be included from other assembler files
5 * Note: This file may not modify r9 because r9 is used to carry
6 * information from the decompressor to the kernel
8 * Copyright (C) 2000-2012 Axis Communications AB
12 /* Just to be certain the config file is included, we include it here
13 * explicitly instead of depending on it being included in the file that
18 ;; WARNING! The registers r8 and r9 are used as parameters carrying
19 ;; information from the decompressor (if the kernel was compressed).
20 ;; They should not be used in the code below.
22 move.d CONFIG_ETRAX_DEF_R_WAITSTATES, $r0
23 move.d $r0, [R_WAITSTATES]
25 move.d CONFIG_ETRAX_DEF_R_BUS_CONFIG, $r0
26 move.d $r0, [R_BUS_CONFIG]
28 #ifndef CONFIG_ETRAX_SDRAM
29 move.d CONFIG_ETRAX_DEF_R_DRAM_CONFIG, $r0
30 move.d $r0, [R_DRAM_CONFIG]
32 move.d CONFIG_ETRAX_DEF_R_DRAM_TIMING, $r0
33 move.d $r0, [R_DRAM_TIMING]
35 ;; Samsung SDRAMs seem to require to be initialized twice to work properly.
39 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
42 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r0
43 move.d $r0, [R_SDRAM_CONFIG]
45 ; Calculate value of mrs_data
46 ; CAS latency = 2 && bus_width = 32 => 0x40
47 ; CAS latency = 3 && bus_width = 32 => 0x60
48 ; CAS latency = 2 && bus_width = 16 => 0x20
49 ; CAS latency = 3 && bus_width = 16 => 0x30
51 ; Check if value is already supplied in kernel config
52 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r2
57 move.d 0x40, $r2 ; Assume 32 bits and CAS latency = 2
58 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
60 and.d 0x03, $r1 ; Get CAS latency
61 and.d 0x1000, $r3 ; 50 or 100 MHz?
65 cmp.d 0x00, $r1 ; CAS latency = 2?
68 or.d 0x20, $r2 ; CAS latency = 3
72 cmp.d 0x01, $r1 ; CAS latency = 2?
75 or.d 0x20, $r2 ; CAS latency = 3
77 move.d CONFIG_ETRAX_DEF_R_SDRAM_CONFIG, $r1
78 and.d 0x800000, $r1 ; DRAM width is bit 23
81 lsrq 1, $r2 ; 16 bits. Shift down value.
83 ; Set timing parameters. Starts master clock
85 move.d CONFIG_ETRAX_DEF_R_SDRAM_TIMING, $r1
86 and.d 0x8000f9ff, $r1 ; Make sure mrs data and command is 0
87 or.d 0x80000000, $r1 ; Make sure sdram enable bit is set
89 or.d 0x0000c000, $r1 ; ref = disable
90 lslq 16, $r2 ; mrs data starts at bit 16
92 move.d $r1, [R_SDRAM_TIMING]
99 ; Issue initialization command sequence
100 move.d _sdram_commands_start, $r2
101 and.d 0x000fffff, $r2 ; Make sure commands are read from flash
102 move.d _sdram_commands_end, $r3
103 and.d 0x000fffff, $r3
106 lslq 9, $r4 ; Command starts at bit 9
108 move.d $r4, [R_SDRAM_TIMING]
109 nop ; Wait five nop cycles between each command
117 move.d $r5, [R_SDRAM_TIMING]
121 ba _sdram_commands_end
124 _sdram_commands_start: