drivers/rtc/rtc-vr41xx.c

   1 /*
   2  *  Driver for NEC VR4100 series Real Time Clock unit.
   3  *
   4  *  Copyright (C) 2003-2008  Yoichi Yuasa <yuasa@linux-mips.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/err.h>
  21 #include <linux/fs.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/rtc.h>
  29 #include <linux/spinlock.h>
  30 #include <linux/types.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/log2.h>
  33
  34 #include <asm/div64.h>
  35
  36 MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
  37 MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
  38 MODULE_LICENSE("GPL v2");
  39
  40 /* RTC 1 registers */
  41 #define ETIMELREG               0x00
  42 #define ETIMEMREG               0x02
  43 #define ETIMEHREG               0x04
  44 /* RFU */
  45 #define ECMPLREG                0x08
  46 #define ECMPMREG                0x0a
  47 #define ECMPHREG                0x0c
  48 /* RFU */
  49 #define RTCL1LREG               0x10
  50 #define RTCL1HREG               0x12
  51 #define RTCL1CNTLREG            0x14
  52 #define RTCL1CNTHREG            0x16
  53 #define RTCL2LREG               0x18
  54 #define RTCL2HREG               0x1a
  55 #define RTCL2CNTLREG            0x1c
  56 #define RTCL2CNTHREG            0x1e
  57
  58 /* RTC 2 registers */
  59 #define TCLKLREG                0x00
  60 #define TCLKHREG                0x02
  61 #define TCLKCNTLREG             0x04
  62 #define TCLKCNTHREG             0x06
  63 /* RFU */
  64 #define RTCINTREG               0x1e
  65  #define TCLOCK_INT             0x08
  66  #define RTCLONG2_INT           0x04
  67  #define RTCLONG1_INT           0x02
  68  #define ELAPSEDTIME_INT        0x01
  69
  70 #define RTC_FREQUENCY           32768
  71 #define MAX_PERIODIC_RATE       6553
  72
  73 static void __iomem *rtc1_base;
  74 static void __iomem *rtc2_base;
  75
  76 #define rtc1_read(offset)               readw(rtc1_base + (offset))
  77 #define rtc1_write(offset, value)       writew((value), rtc1_base + (offset))
  78
  79 #define rtc2_read(offset)               readw(rtc2_base + (offset))
  80 #define rtc2_write(offset, value)       writew((value), rtc2_base + (offset))
  81
  82 static unsigned long epoch = 1970;      /* Jan 1 1970 00:00:00 */
  83
  84 static DEFINE_SPINLOCK(rtc_lock);
  85 static char rtc_name[] = "RTC";
  86 static unsigned long periodic_count;
  87 static unsigned int alarm_enabled;
  88 static int aie_irq;
  89 static int pie_irq;
  90
  91 static inline time64_t read_elapsed_second(void)
  92 {
  93
  94         unsigned long first_low, first_mid, first_high;
  95
  96         unsigned long second_low, second_mid, second_high;
  97
  98         do {
  99                 first_low = rtc1_read(ETIMELREG);
 100                 first_mid = rtc1_read(ETIMEMREG);
 101                 first_high = rtc1_read(ETIMEHREG);
 102                 second_low = rtc1_read(ETIMELREG);
 103                 second_mid = rtc1_read(ETIMEMREG);
 104                 second_high = rtc1_read(ETIMEHREG);
 105         } while (first_low != second_low || first_mid != second_mid ||
 106                  first_high != second_high);
 107
 108         return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
 109 }
 110
 111 static inline void write_elapsed_second(time64_t sec)
 112 {
 113         spin_lock_irq(&rtc_lock);
 114
 115         rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
 116         rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
 117         rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
 118
 119         spin_unlock_irq(&rtc_lock);
 120 }
 121
 122 static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
 123 {
 124         time64_t epoch_sec, elapsed_sec;
 125
 126         epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
 127         elapsed_sec = read_elapsed_second();
 128
 129         rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
 130
 131         return 0;
 132 }
 133
 134 static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
 135 {
 136         time64_t epoch_sec, current_sec;
 137
 138         epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
 139         current_sec = rtc_tm_to_time64(time);
 140
 141         write_elapsed_second(current_sec - epoch_sec);
 142
 143         return 0;
 144 }
 145
 146 static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 147 {
 148         unsigned long low, mid, high;
 149         struct rtc_time *time = &wkalrm->time;
 150
 151         spin_lock_irq(&rtc_lock);
 152
 153         low = rtc1_read(ECMPLREG);
 154         mid = rtc1_read(ECMPMREG);
 155         high = rtc1_read(ECMPHREG);
 156         wkalrm->enabled = alarm_enabled;
 157
 158         spin_unlock_irq(&rtc_lock);
 159
 160         rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
 161
 162         return 0;
 163 }
 164
 165 static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
 166 {
 167         time64_t alarm_sec;
 168
 169         alarm_sec = rtc_tm_to_time64(&wkalrm->time);
 170
 171         spin_lock_irq(&rtc_lock);
 172
 173         if (alarm_enabled)
 174                 disable_irq(aie_irq);
 175
 176         rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
 177         rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
 178         rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
 179
 180         if (wkalrm->enabled)
 181                 enable_irq(aie_irq);
 182
 183         alarm_enabled = wkalrm->enabled;
 184
 185         spin_unlock_irq(&rtc_lock);
 186
 187         return 0;
 188 }
 189
 190 static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
 191 {
 192         switch (cmd) {
 193         case RTC_EPOCH_READ:
 194                 return put_user(epoch, (unsigned long __user *)arg);
 195         case RTC_EPOCH_SET:
 196                 /* Doesn't support before 1900 */
 197                 if (arg < 1900)
 198                         return -EINVAL;
 199                 epoch = arg;
 200                 break;
 201         default:
 202                 return -ENOIOCTLCMD;
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 209 {
 210         spin_lock_irq(&rtc_lock);
 211         if (enabled) {
 212                 if (!alarm_enabled) {
 213                         enable_irq(aie_irq);
 214                         alarm_enabled = 1;
 215                 }
 216         } else {
 217                 if (alarm_enabled) {
 218                         disable_irq(aie_irq);
 219                         alarm_enabled = 0;
 220                 }
 221         }
 222         spin_unlock_irq(&rtc_lock);
 223         return 0;
 224 }
 225
 226 static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
 227 {
 228         struct platform_device *pdev = (struct platform_device *)dev_id;
 229         struct rtc_device *rtc = platform_get_drvdata(pdev);
 230
 231         rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
 232
 233         rtc_update_irq(rtc, 1, RTC_AF);
 234
 235         return IRQ_HANDLED;
 236 }
 237
 238 static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
 239 {
 240         struct platform_device *pdev = (struct platform_device *)dev_id;
 241         struct rtc_device *rtc = platform_get_drvdata(pdev);
 242         unsigned long count = periodic_count;
 243
 244         rtc2_write(RTCINTREG, RTCLONG1_INT);
 245
 246         rtc1_write(RTCL1LREG, count);
 247         rtc1_write(RTCL1HREG, count >> 16);
 248
 249         rtc_update_irq(rtc, 1, RTC_PF);
 250
 251         return IRQ_HANDLED;
 252 }
 253
 254 static const struct rtc_class_ops vr41xx_rtc_ops = {
 255         .ioctl                  = vr41xx_rtc_ioctl,
 256         .read_time              = vr41xx_rtc_read_time,
 257         .set_time               = vr41xx_rtc_set_time,
 258         .read_alarm             = vr41xx_rtc_read_alarm,
 259         .set_alarm              = vr41xx_rtc_set_alarm,
 260         .alarm_irq_enable       = vr41xx_rtc_alarm_irq_enable,
 261 };
 262
 263 static int rtc_probe(struct platform_device *pdev)
 264 {
 265         struct resource *res;
 266         struct rtc_device *rtc;
 267         int retval;
 268
 269         if (pdev->num_resources != 4)
 270                 return -EBUSY;
 271
 272         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 273         if (!res)
 274                 return -EBUSY;
 275
 276         rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 277         if (!rtc1_base)
 278                 return -EBUSY;
 279
 280         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 281         if (!res) {
 282                 retval = -EBUSY;
 283                 goto err_rtc1_iounmap;
 284         }
 285
 286         rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 287         if (!rtc2_base) {
 288                 retval = -EBUSY;
 289                 goto err_rtc1_iounmap;
 290         }
 291
 292         rtc = devm_rtc_allocate_device(&pdev->dev);
 293         if (IS_ERR(rtc)) {
 294                 retval = PTR_ERR(rtc);
 295                 goto err_iounmap_all;
 296         }
 297
 298         rtc->ops = &vr41xx_rtc_ops;
 299
 300         /* 48-bit counter at 32.768 kHz */
 301         rtc->range_max = (1ULL << 33) - 1;
 302         rtc->max_user_freq = MAX_PERIODIC_RATE;
 303
 304         spin_lock_irq(&rtc_lock);
 305
 306         rtc1_write(ECMPLREG, 0);
 307         rtc1_write(ECMPMREG, 0);
 308         rtc1_write(ECMPHREG, 0);
 309         rtc1_write(RTCL1LREG, 0);
 310         rtc1_write(RTCL1HREG, 0);
 311
 312         spin_unlock_irq(&rtc_lock);
 313
 314         aie_irq = platform_get_irq(pdev, 0);
 315         if (aie_irq <= 0) {
 316                 retval = -EBUSY;
 317                 goto err_iounmap_all;
 318         }
 319
 320         retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
 321                                 "elapsed_time", pdev);
 322         if (retval < 0)
 323                 goto err_iounmap_all;
 324
 325         pie_irq = platform_get_irq(pdev, 1);
 326         if (pie_irq <= 0) {
 327                 retval = -EBUSY;
 328                 goto err_iounmap_all;
 329         }
 330
 331         retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
 332                                 "rtclong1", pdev);
 333         if (retval < 0)
 334                 goto err_iounmap_all;
 335
 336         platform_set_drvdata(pdev, rtc);
 337
 338         disable_irq(aie_irq);
 339         disable_irq(pie_irq);
 340
 341         dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
 342
 343         retval = rtc_register_device(rtc);
 344         if (retval)
 345                 goto err_iounmap_all;
 346
 347         return 0;
 348
 349 err_iounmap_all:
 350         rtc2_base = NULL;
 351
 352 err_rtc1_iounmap:
 353         rtc1_base = NULL;
 354
 355         return retval;
 356 }
 357
 358 /* work with hotplug and coldplug */
 359 MODULE_ALIAS("platform:RTC");
 360
 361 static struct platform_driver rtc_platform_driver = {
 362         .probe          = rtc_probe,
 363         .driver         = {
 364                 .name   = rtc_name,
 365         },
 366 };
 367
 368 module_platform_driver(rtc_platform_driver);