2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/memblock.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
58 #define DBG(fmt...) udbg_printf(fmt)
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
66 #define DBG_LOW(fmt...)
74 * Note: pte --> Linux PTE
75 * HPTE --> PowerPC Hashed Page Table Entry
78 * htab_initialize is called with the MMU off (of course), but
79 * the kernel has been copied down to zero so it can directly
80 * reference global data. At this point it is very difficult
81 * to print debug info.
86 extern unsigned long dart_tablebase
;
87 #endif /* CONFIG_U3_DART */
89 static unsigned long _SDR1
;
90 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
92 struct hash_pte
*htab_address
;
93 unsigned long htab_size_bytes
;
94 unsigned long htab_hash_mask
;
95 EXPORT_SYMBOL_GPL(htab_hash_mask
);
96 int mmu_linear_psize
= MMU_PAGE_4K
;
97 int mmu_virtual_psize
= MMU_PAGE_4K
;
98 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
99 #ifdef CONFIG_SPARSEMEM_VMEMMAP
100 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
102 int mmu_io_psize
= MMU_PAGE_4K
;
103 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
104 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
105 u16 mmu_slb_size
= 64;
106 EXPORT_SYMBOL_GPL(mmu_slb_size
);
107 #ifdef CONFIG_HUGETLB_PAGE
108 unsigned int HPAGE_SHIFT
;
110 #ifdef CONFIG_PPC_64K_PAGES
111 int mmu_ci_restrictions
;
113 #ifdef CONFIG_DEBUG_PAGEALLOC
114 static u8
*linear_map_hash_slots
;
115 static unsigned long linear_map_hash_count
;
116 static DEFINE_SPINLOCK(linear_map_hash_lock
);
117 #endif /* CONFIG_DEBUG_PAGEALLOC */
119 /* There are definitions of page sizes arrays to be used when none
120 * is provided by the firmware.
123 /* Pre-POWER4 CPUs (4k pages only)
125 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
135 /* POWER4, GPUL, POWER5
137 * Support for 16Mb large pages
139 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
156 static unsigned long htab_convert_pte_flags(unsigned long pteflags
)
158 unsigned long rflags
= pteflags
& 0x1fa;
160 /* _PAGE_EXEC -> NOEXEC */
161 if ((pteflags
& _PAGE_EXEC
) == 0)
164 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
165 * need to add in 0x1 if it's a read-only user page
167 if ((pteflags
& _PAGE_USER
) && !((pteflags
& _PAGE_RW
) &&
168 (pteflags
& _PAGE_DIRTY
)))
172 return rflags
| HPTE_R_C
;
175 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
176 unsigned long pstart
, unsigned long prot
,
177 int psize
, int ssize
)
179 unsigned long vaddr
, paddr
;
180 unsigned int step
, shift
;
183 shift
= mmu_psize_defs
[psize
].shift
;
186 prot
= htab_convert_pte_flags(prot
);
188 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
189 vstart
, vend
, pstart
, prot
, psize
, ssize
);
191 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
192 vaddr
+= step
, paddr
+= step
) {
193 unsigned long hash
, hpteg
;
194 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
195 unsigned long va
= hpt_va(vaddr
, vsid
, ssize
);
196 unsigned long tprot
= prot
;
198 /* Make kernel text executable */
199 if (overlaps_kernel_text(vaddr
, vaddr
+ step
))
202 hash
= hpt_hash(va
, shift
, ssize
);
203 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
205 BUG_ON(!ppc_md
.hpte_insert
);
206 ret
= ppc_md
.hpte_insert(hpteg
, va
, paddr
, tprot
,
207 HPTE_V_BOLTED
, psize
, ssize
);
211 #ifdef CONFIG_DEBUG_PAGEALLOC
212 if ((paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
213 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
214 #endif /* CONFIG_DEBUG_PAGEALLOC */
216 return ret
< 0 ? ret
: 0;
219 #ifdef CONFIG_MEMORY_HOTPLUG
220 static int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
221 int psize
, int ssize
)
224 unsigned int step
, shift
;
226 shift
= mmu_psize_defs
[psize
].shift
;
229 if (!ppc_md
.hpte_removebolted
) {
230 printk(KERN_WARNING
"Platform doesn't implement "
231 "hpte_removebolted\n");
235 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
)
236 ppc_md
.hpte_removebolted(vaddr
, psize
, ssize
);
240 #endif /* CONFIG_MEMORY_HOTPLUG */
242 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
243 const char *uname
, int depth
,
246 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
248 unsigned long size
= 0;
250 /* We are scanning "cpu" nodes only */
251 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
254 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes",
258 for (; size
>= 4; size
-= 4, ++prop
) {
260 DBG("1T segment support detected\n");
261 cur_cpu_spec
->cpu_features
|= CPU_FTR_1T_SEGMENT
;
265 cur_cpu_spec
->cpu_features
&= ~CPU_FTR_NO_SLBIE_B
;
269 static void __init
htab_init_seg_sizes(void)
271 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
274 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
275 const char *uname
, int depth
,
278 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
280 unsigned long size
= 0;
282 /* We are scanning "cpu" nodes only */
283 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
286 prop
= (u32
*)of_get_flat_dt_prop(node
,
287 "ibm,segment-page-sizes", &size
);
289 DBG("Page sizes from device-tree:\n");
291 cur_cpu_spec
->cpu_features
&= ~(CPU_FTR_16M_PAGE
);
293 unsigned int shift
= prop
[0];
294 unsigned int slbenc
= prop
[1];
295 unsigned int lpnum
= prop
[2];
296 unsigned int lpenc
= 0;
297 struct mmu_psize_def
*def
;
300 size
-= 3; prop
+= 3;
301 while(size
> 0 && lpnum
) {
302 if (prop
[0] == shift
)
304 prop
+= 2; size
-= 2;
319 cur_cpu_spec
->cpu_features
|= CPU_FTR_16M_PAGE
;
327 def
= &mmu_psize_defs
[idx
];
332 def
->avpnm
= (1 << (shift
- 23)) - 1;
335 /* We don't know for sure what's up with tlbiel, so
336 * for now we only set it for 4K and 64K pages
338 if (idx
== MMU_PAGE_4K
|| idx
== MMU_PAGE_64K
)
343 DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
344 "tlbiel=%d, penc=%d\n",
345 idx
, shift
, def
->sllp
, def
->avpnm
, def
->tlbiel
,
353 #ifdef CONFIG_HUGETLB_PAGE
354 /* Scan for 16G memory blocks that have been set aside for huge pages
355 * and reserve those blocks for 16G huge pages.
357 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
358 const char *uname
, int depth
,
360 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
361 unsigned long *addr_prop
;
362 u32
*page_count_prop
;
363 unsigned int expected_pages
;
364 long unsigned int phys_addr
;
365 long unsigned int block_size
;
367 /* We are scanning "memory" nodes only */
368 if (type
== NULL
|| strcmp(type
, "memory") != 0)
371 /* This property is the log base 2 of the number of virtual pages that
372 * will represent this memory block. */
373 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
374 if (page_count_prop
== NULL
)
376 expected_pages
= (1 << page_count_prop
[0]);
377 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
378 if (addr_prop
== NULL
)
380 phys_addr
= addr_prop
[0];
381 block_size
= addr_prop
[1];
382 if (block_size
!= (16 * GB
))
384 printk(KERN_INFO
"Huge page(16GB) memory: "
385 "addr = 0x%lX size = 0x%lX pages = %d\n",
386 phys_addr
, block_size
, expected_pages
);
387 if (phys_addr
+ (16 * GB
) <= memblock_end_of_DRAM()) {
388 memblock_reserve(phys_addr
, block_size
* expected_pages
);
389 add_gpage(phys_addr
, block_size
, expected_pages
);
393 #endif /* CONFIG_HUGETLB_PAGE */
395 static void __init
htab_init_page_sizes(void)
399 /* Default to 4K pages only */
400 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
401 sizeof(mmu_psize_defaults_old
));
404 * Try to find the available page sizes in the device-tree
406 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
407 if (rc
!= 0) /* Found */
411 * Not in the device-tree, let's fallback on known size
412 * list for 16M capable GP & GR
414 if (cpu_has_feature(CPU_FTR_16M_PAGE
))
415 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
416 sizeof(mmu_psize_defaults_gp
));
418 #ifndef CONFIG_DEBUG_PAGEALLOC
420 * Pick a size for the linear mapping. Currently, we only support
421 * 16M, 1M and 4K which is the default
423 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
424 mmu_linear_psize
= MMU_PAGE_16M
;
425 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
426 mmu_linear_psize
= MMU_PAGE_1M
;
427 #endif /* CONFIG_DEBUG_PAGEALLOC */
429 #ifdef CONFIG_PPC_64K_PAGES
431 * Pick a size for the ordinary pages. Default is 4K, we support
432 * 64K for user mappings and vmalloc if supported by the processor.
433 * We only use 64k for ioremap if the processor
434 * (and firmware) support cache-inhibited large pages.
435 * If not, we use 4k and set mmu_ci_restrictions so that
436 * hash_page knows to switch processes that use cache-inhibited
437 * mappings to 4k pages.
439 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
440 mmu_virtual_psize
= MMU_PAGE_64K
;
441 mmu_vmalloc_psize
= MMU_PAGE_64K
;
442 if (mmu_linear_psize
== MMU_PAGE_4K
)
443 mmu_linear_psize
= MMU_PAGE_64K
;
444 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE
)) {
446 * Don't use 64k pages for ioremap on pSeries, since
447 * that would stop us accessing the HEA ethernet.
449 if (!machine_is(pseries
))
450 mmu_io_psize
= MMU_PAGE_64K
;
452 mmu_ci_restrictions
= 1;
454 #endif /* CONFIG_PPC_64K_PAGES */
456 #ifdef CONFIG_SPARSEMEM_VMEMMAP
457 /* We try to use 16M pages for vmemmap if that is supported
458 * and we have at least 1G of RAM at boot
460 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
461 memblock_phys_mem_size() >= 0x40000000)
462 mmu_vmemmap_psize
= MMU_PAGE_16M
;
463 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
464 mmu_vmemmap_psize
= MMU_PAGE_64K
;
466 mmu_vmemmap_psize
= MMU_PAGE_4K
;
467 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
469 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
470 "virtual = %d, io = %d"
471 #ifdef CONFIG_SPARSEMEM_VMEMMAP
475 mmu_psize_defs
[mmu_linear_psize
].shift
,
476 mmu_psize_defs
[mmu_virtual_psize
].shift
,
477 mmu_psize_defs
[mmu_io_psize
].shift
478 #ifdef CONFIG_SPARSEMEM_VMEMMAP
479 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
483 #ifdef CONFIG_HUGETLB_PAGE
484 /* Reserve 16G huge page memory sections for huge pages */
485 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
486 #endif /* CONFIG_HUGETLB_PAGE */
489 static int __init
htab_dt_scan_pftsize(unsigned long node
,
490 const char *uname
, int depth
,
493 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
496 /* We are scanning "cpu" nodes only */
497 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
500 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
502 /* pft_size[0] is the NUMA CEC cookie */
503 ppc64_pft_size
= prop
[1];
509 static unsigned long __init
htab_get_table_size(void)
511 unsigned long mem_size
, rnd_mem_size
, pteg_count
, psize
;
513 /* If hash size isn't already provided by the platform, we try to
514 * retrieve it from the device-tree. If it's not there neither, we
515 * calculate it now based on the total RAM size
517 if (ppc64_pft_size
== 0)
518 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
520 return 1UL << ppc64_pft_size
;
522 /* round mem_size up to next power of 2 */
523 mem_size
= memblock_phys_mem_size();
524 rnd_mem_size
= 1UL << __ilog2(mem_size
);
525 if (rnd_mem_size
< mem_size
)
529 psize
= mmu_psize_defs
[mmu_virtual_psize
].shift
;
530 pteg_count
= max(rnd_mem_size
>> (psize
+ 1), 1UL << 11);
532 return pteg_count
<< 7;
535 #ifdef CONFIG_MEMORY_HOTPLUG
536 void create_section_mapping(unsigned long start
, unsigned long end
)
538 BUG_ON(htab_bolt_mapping(start
, end
, __pa(start
),
539 pgprot_val(PAGE_KERNEL
), mmu_linear_psize
,
543 int remove_section_mapping(unsigned long start
, unsigned long end
)
545 return htab_remove_mapping(start
, end
, mmu_linear_psize
,
548 #endif /* CONFIG_MEMORY_HOTPLUG */
550 static inline void make_bl(unsigned int *insn_addr
, void *func
)
552 unsigned long funcp
= *((unsigned long *)func
);
553 int offset
= funcp
- (unsigned long)insn_addr
;
555 *insn_addr
= (unsigned int)(0x48000001 | (offset
& 0x03fffffc));
556 flush_icache_range((unsigned long)insn_addr
, 4+
557 (unsigned long)insn_addr
);
560 static void __init
htab_finish_init(void)
562 extern unsigned int *htab_call_hpte_insert1
;
563 extern unsigned int *htab_call_hpte_insert2
;
564 extern unsigned int *htab_call_hpte_remove
;
565 extern unsigned int *htab_call_hpte_updatepp
;
567 #ifdef CONFIG_PPC_HAS_HASH_64K
568 extern unsigned int *ht64_call_hpte_insert1
;
569 extern unsigned int *ht64_call_hpte_insert2
;
570 extern unsigned int *ht64_call_hpte_remove
;
571 extern unsigned int *ht64_call_hpte_updatepp
;
573 make_bl(ht64_call_hpte_insert1
, ppc_md
.hpte_insert
);
574 make_bl(ht64_call_hpte_insert2
, ppc_md
.hpte_insert
);
575 make_bl(ht64_call_hpte_remove
, ppc_md
.hpte_remove
);
576 make_bl(ht64_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
577 #endif /* CONFIG_PPC_HAS_HASH_64K */
579 make_bl(htab_call_hpte_insert1
, ppc_md
.hpte_insert
);
580 make_bl(htab_call_hpte_insert2
, ppc_md
.hpte_insert
);
581 make_bl(htab_call_hpte_remove
, ppc_md
.hpte_remove
);
582 make_bl(htab_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
585 static void __init
htab_initialize(void)
588 unsigned long pteg_count
;
590 unsigned long base
= 0, size
= 0, limit
;
591 struct memblock_region
*reg
;
593 DBG(" -> htab_initialize()\n");
595 /* Initialize segment sizes */
596 htab_init_seg_sizes();
598 /* Initialize page sizes */
599 htab_init_page_sizes();
601 if (cpu_has_feature(CPU_FTR_1T_SEGMENT
)) {
602 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
603 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
604 printk(KERN_INFO
"Using 1TB segments\n");
608 * Calculate the required size of the htab. We want the number of
609 * PTEGs to equal one half the number of real pages.
611 htab_size_bytes
= htab_get_table_size();
612 pteg_count
= htab_size_bytes
>> 7;
614 htab_hash_mask
= pteg_count
- 1;
616 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
617 /* Using a hypervisor which owns the htab */
621 /* Find storage for the HPT. Must be contiguous in
622 * the absolute address space. On cell we want it to be
623 * in the first 2 Gig so we can use it for IOMMU hacks.
625 if (machine_is(cell
))
628 limit
= MEMBLOCK_ALLOC_ANYWHERE
;
630 table
= memblock_alloc_base(htab_size_bytes
, htab_size_bytes
, limit
);
632 DBG("Hash table allocated at %lx, size: %lx\n", table
,
635 htab_address
= abs_to_virt(table
);
637 /* htab absolute addr + encoded htabsize */
638 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
640 /* Initialize the HPT with no entries */
641 memset((void *)table
, 0, htab_size_bytes
);
644 mtspr(SPRN_SDR1
, _SDR1
);
647 prot
= pgprot_val(PAGE_KERNEL
);
649 #ifdef CONFIG_DEBUG_PAGEALLOC
650 linear_map_hash_count
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
651 linear_map_hash_slots
= __va(memblock_alloc_base(linear_map_hash_count
,
653 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
654 #endif /* CONFIG_DEBUG_PAGEALLOC */
656 /* On U3 based machines, we need to reserve the DART area and
657 * _NOT_ map it to avoid cache paradoxes as it's remapped non
661 /* create bolted the linear mapping in the hash table */
662 for_each_memblock(memory
, reg
) {
663 base
= (unsigned long)__va(reg
->base
);
666 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
669 #ifdef CONFIG_U3_DART
670 /* Do not map the DART space. Fortunately, it will be aligned
671 * in such a way that it will not cross two memblock regions and
672 * will fit within a single 16Mb page.
673 * The DART space is assumed to be a full 16Mb region even if
674 * we only use 2Mb of that space. We will use more of it later
675 * for AGP GART. We have to use a full 16Mb large page.
677 DBG("DART base: %lx\n", dart_tablebase
);
679 if (dart_tablebase
!= 0 && dart_tablebase
>= base
680 && dart_tablebase
< (base
+ size
)) {
681 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
682 if (base
!= dart_tablebase
)
683 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
687 if ((base
+ size
) > dart_table_end
)
688 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
690 __pa(dart_table_end
),
696 #endif /* CONFIG_U3_DART */
697 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
698 prot
, mmu_linear_psize
, mmu_kernel_ssize
));
700 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE
);
703 * If we have a memory_limit and we've allocated TCEs then we need to
704 * explicitly map the TCE area at the top of RAM. We also cope with the
705 * case that the TCEs start below memory_limit.
706 * tce_alloc_start/end are 16MB aligned so the mapping should work
707 * for either 4K or 16MB pages.
709 if (tce_alloc_start
) {
710 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
711 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
713 if (base
+ size
>= tce_alloc_start
)
714 tce_alloc_start
= base
+ size
+ 1;
716 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
717 __pa(tce_alloc_start
), prot
,
718 mmu_linear_psize
, mmu_kernel_ssize
));
723 DBG(" <- htab_initialize()\n");
728 void __init
early_init_mmu(void)
730 /* Setup initial STAB address in the PACA */
731 get_paca()->stab_real
= __pa((u64
)&initial_stab
);
732 get_paca()->stab_addr
= (u64
)&initial_stab
;
734 /* Initialize the MMU Hash table and create the linear mapping
735 * of memory. Has to be done before stab/slb initialization as
736 * this is currently where the page size encoding is obtained
740 /* Initialize stab / SLB management except on iSeries
742 if (cpu_has_feature(CPU_FTR_SLB
))
744 else if (!firmware_has_feature(FW_FEATURE_ISERIES
))
745 stab_initialize(get_paca()->stab_real
);
749 void __cpuinit
early_init_mmu_secondary(void)
751 /* Initialize hash table for that CPU */
752 if (!firmware_has_feature(FW_FEATURE_LPAR
))
753 mtspr(SPRN_SDR1
, _SDR1
);
755 /* Initialize STAB/SLB. We use a virtual address as it works
756 * in real mode on pSeries and we want a virutal address on
759 if (cpu_has_feature(CPU_FTR_SLB
))
762 stab_initialize(get_paca()->stab_addr
);
764 #endif /* CONFIG_SMP */
767 * Called by asm hashtable.S for doing lazy icache flush
769 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
773 if (!pfn_valid(pte_pfn(pte
)))
776 page
= pte_page(pte
);
779 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
781 flush_dcache_icache_page(page
);
782 set_bit(PG_arch_1
, &page
->flags
);
789 #ifdef CONFIG_PPC_MM_SLICES
790 unsigned int get_paca_psize(unsigned long addr
)
792 unsigned long index
, slices
;
794 if (addr
< SLICE_LOW_TOP
) {
795 slices
= get_paca()->context
.low_slices_psize
;
796 index
= GET_LOW_SLICE_INDEX(addr
);
798 slices
= get_paca()->context
.high_slices_psize
;
799 index
= GET_HIGH_SLICE_INDEX(addr
);
801 return (slices
>> (index
* 4)) & 0xF;
805 unsigned int get_paca_psize(unsigned long addr
)
807 return get_paca()->context
.user_psize
;
812 * Demote a segment to using 4k pages.
813 * For now this makes the whole process use 4k pages.
815 #ifdef CONFIG_PPC_64K_PAGES
816 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
818 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
820 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
821 #ifdef CONFIG_SPU_BASE
822 spu_flush_all_slbs(mm
);
824 if (get_paca_psize(addr
) != MMU_PAGE_4K
) {
825 get_paca()->context
= mm
->context
;
826 slb_flush_and_rebolt();
829 #endif /* CONFIG_PPC_64K_PAGES */
831 #ifdef CONFIG_PPC_SUBPAGE_PROT
833 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
834 * Userspace sets the subpage permissions using the subpage_prot system call.
836 * Result is 0: full permissions, _PAGE_RW: read-only,
837 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
839 static int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
841 struct subpage_prot_table
*spt
= &mm
->context
.spt
;
845 if (ea
>= spt
->maxaddr
)
847 if (ea
< 0x100000000) {
848 /* addresses below 4GB use spt->low_prot */
849 sbpm
= spt
->low_prot
;
851 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
855 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
858 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
860 /* extract 2-bit bitfield for this 4k subpage */
861 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
863 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
864 spp
= ((spp
& 2) ? _PAGE_USER
: 0) | ((spp
& 1) ? _PAGE_RW
: 0);
868 #else /* CONFIG_PPC_SUBPAGE_PROT */
869 static inline int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
875 void hash_failure_debug(unsigned long ea
, unsigned long access
,
876 unsigned long vsid
, unsigned long trap
,
877 int ssize
, int psize
, unsigned long pte
)
879 if (!printk_ratelimit())
881 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
882 ea
, access
, current
->comm
);
883 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d psize=%d pte=0x%lx\n",
884 trap
, vsid
, ssize
, psize
, pte
);
889 * 1 - normal page fault
890 * -1 - critical hash insertion error
891 * -2 - access not permitted by subpage protection mechanism
893 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
)
897 struct mm_struct
*mm
;
900 const struct cpumask
*tmp
;
901 int rc
, user_region
= 0, local
= 0;
904 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
907 if ((ea
& ~REGION_MASK
) >= PGTABLE_RANGE
) {
908 DBG_LOW(" out of pgtable range !\n");
912 /* Get region & vsid */
913 switch (REGION_ID(ea
)) {
918 DBG_LOW(" user region with no mm !\n");
921 psize
= get_slice_psize(mm
, ea
);
922 ssize
= user_segment_size(ea
);
923 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
925 case VMALLOC_REGION_ID
:
927 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
928 if (ea
< VMALLOC_END
)
929 psize
= mmu_vmalloc_psize
;
931 psize
= mmu_io_psize
;
932 ssize
= mmu_kernel_ssize
;
936 * Send the problem up to do_page_fault
940 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
947 /* Check CPU locality */
948 tmp
= cpumask_of(smp_processor_id());
949 if (user_region
&& cpumask_equal(mm_cpumask(mm
), tmp
))
952 #ifndef CONFIG_PPC_64K_PAGES
953 /* If we use 4K pages and our psize is not 4K, then we might
954 * be hitting a special driver mapping, and need to align the
955 * address before we fetch the PTE.
957 * It could also be a hugepage mapping, in which case this is
958 * not necessary, but it's not harmful, either.
960 if (psize
!= MMU_PAGE_4K
)
961 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
962 #endif /* CONFIG_PPC_64K_PAGES */
964 /* Get PTE and page size from page tables */
965 ptep
= find_linux_pte_or_hugepte(pgdir
, ea
, &hugeshift
);
966 if (ptep
== NULL
|| !pte_present(*ptep
)) {
967 DBG_LOW(" no PTE !\n");
971 /* Add _PAGE_PRESENT to the required access perm */
972 access
|= _PAGE_PRESENT
;
974 /* Pre-check access permissions (will be re-checked atomically
975 * in __hash_page_XX but this pre-check is a fast path
977 if (access
& ~pte_val(*ptep
)) {
978 DBG_LOW(" no access !\n");
982 #ifdef CONFIG_HUGETLB_PAGE
984 return __hash_page_huge(ea
, access
, vsid
, ptep
, trap
, local
,
985 ssize
, hugeshift
, psize
);
986 #endif /* CONFIG_HUGETLB_PAGE */
988 #ifndef CONFIG_PPC_64K_PAGES
989 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
991 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
992 pte_val(*(ptep
+ PTRS_PER_PTE
)));
994 /* Do actual hashing */
995 #ifdef CONFIG_PPC_64K_PAGES
996 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
997 if ((pte_val(*ptep
) & _PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
998 demote_segment_4k(mm
, ea
);
1002 /* If this PTE is non-cacheable and we have restrictions on
1003 * using non cacheable large pages, then we switch to 4k
1005 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&&
1006 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
1008 demote_segment_4k(mm
, ea
);
1009 psize
= MMU_PAGE_4K
;
1010 } else if (ea
< VMALLOC_END
) {
1012 * some driver did a non-cacheable mapping
1013 * in vmalloc space, so switch vmalloc
1016 printk(KERN_ALERT
"Reducing vmalloc segment "
1017 "to 4kB pages because of "
1018 "non-cacheable mapping\n");
1019 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
1020 #ifdef CONFIG_SPU_BASE
1021 spu_flush_all_slbs(mm
);
1026 if (psize
!= get_paca_psize(ea
)) {
1027 get_paca()->context
= mm
->context
;
1028 slb_flush_and_rebolt();
1030 } else if (get_paca()->vmalloc_sllp
!=
1031 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
1032 get_paca()->vmalloc_sllp
=
1033 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
1034 slb_vmalloc_update();
1036 #endif /* CONFIG_PPC_64K_PAGES */
1038 #ifdef CONFIG_PPC_HAS_HASH_64K
1039 if (psize
== MMU_PAGE_64K
)
1040 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
1042 #endif /* CONFIG_PPC_HAS_HASH_64K */
1044 int spp
= subpage_protection(mm
, ea
);
1048 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1052 /* Dump some info in case of hash insertion failure, they should
1053 * never happen so it is really useful to know if/when they do
1056 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
, psize
,
1058 #ifndef CONFIG_PPC_64K_PAGES
1059 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1061 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1062 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1064 DBG_LOW(" -> rc=%d\n", rc
);
1067 EXPORT_SYMBOL_GPL(hash_page
);
1069 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1070 unsigned long access
, unsigned long trap
)
1075 unsigned long flags
;
1076 int rc
, ssize
, local
= 0;
1078 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1080 #ifdef CONFIG_PPC_MM_SLICES
1081 /* We only prefault standard pages for now */
1082 if (unlikely(get_slice_psize(mm
, ea
) != mm
->context
.user_psize
))
1086 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1087 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1089 /* Get Linux PTE if available */
1093 ptep
= find_linux_pte(pgdir
, ea
);
1097 #ifdef CONFIG_PPC_64K_PAGES
1098 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1099 * a 64K kernel), then we don't preload, hash_page() will take
1100 * care of it once we actually try to access the page.
1101 * That way we don't have to duplicate all of the logic for segment
1102 * page size demotion here
1104 if (pte_val(*ptep
) & (_PAGE_4K_PFN
| _PAGE_NO_CACHE
))
1106 #endif /* CONFIG_PPC_64K_PAGES */
1109 ssize
= user_segment_size(ea
);
1110 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1112 /* Hash doesn't like irqs */
1113 local_irq_save(flags
);
1115 /* Is that local to this CPU ? */
1116 if (cpumask_equal(mm_cpumask(mm
), cpumask_of(smp_processor_id())))
1120 #ifdef CONFIG_PPC_HAS_HASH_64K
1121 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1122 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
1124 #endif /* CONFIG_PPC_HAS_HASH_64K */
1125 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
,
1126 subpage_protection(mm
, ea
));
1128 /* Dump some info in case of hash insertion failure, they should
1129 * never happen so it is really useful to know if/when they do
1132 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
,
1133 mm
->context
.user_psize
, pte_val(*ptep
));
1135 local_irq_restore(flags
);
1138 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1139 * do not forget to update the assembly call site !
1141 void flush_hash_page(unsigned long va
, real_pte_t pte
, int psize
, int ssize
,
1144 unsigned long hash
, index
, shift
, hidx
, slot
;
1146 DBG_LOW("flush_hash_page(va=%016lx)\n", va
);
1147 pte_iterate_hashed_subpages(pte
, psize
, va
, index
, shift
) {
1148 hash
= hpt_hash(va
, shift
, ssize
);
1149 hidx
= __rpte_to_hidx(pte
, index
);
1150 if (hidx
& _PTEIDX_SECONDARY
)
1152 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1153 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1154 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index
, slot
, hidx
);
1155 ppc_md
.hpte_invalidate(slot
, va
, psize
, ssize
, local
);
1156 } pte_iterate_hashed_end();
1159 void flush_hash_range(unsigned long number
, int local
)
1161 if (ppc_md
.flush_hash_range
)
1162 ppc_md
.flush_hash_range(number
, local
);
1165 struct ppc64_tlb_batch
*batch
=
1166 &__get_cpu_var(ppc64_tlb_batch
);
1168 for (i
= 0; i
< number
; i
++)
1169 flush_hash_page(batch
->vaddr
[i
], batch
->pte
[i
],
1170 batch
->psize
, batch
->ssize
, local
);
1175 * low_hash_fault is called when we the low level hash code failed
1176 * to instert a PTE due to an hypervisor error
1178 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1180 if (user_mode(regs
)) {
1181 #ifdef CONFIG_PPC_SUBPAGE_PROT
1183 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1186 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1188 bad_page_fault(regs
, address
, SIGBUS
);
1191 #ifdef CONFIG_DEBUG_PAGEALLOC
1192 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1194 unsigned long hash
, hpteg
;
1195 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1196 unsigned long va
= hpt_va(vaddr
, vsid
, mmu_kernel_ssize
);
1197 unsigned long mode
= htab_convert_pte_flags(PAGE_KERNEL
);
1200 hash
= hpt_hash(va
, PAGE_SHIFT
, mmu_kernel_ssize
);
1201 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
1203 ret
= ppc_md
.hpte_insert(hpteg
, va
, __pa(vaddr
),
1204 mode
, HPTE_V_BOLTED
,
1205 mmu_linear_psize
, mmu_kernel_ssize
);
1207 spin_lock(&linear_map_hash_lock
);
1208 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1209 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1210 spin_unlock(&linear_map_hash_lock
);
1213 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1215 unsigned long hash
, hidx
, slot
;
1216 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1217 unsigned long va
= hpt_va(vaddr
, vsid
, mmu_kernel_ssize
);
1219 hash
= hpt_hash(va
, PAGE_SHIFT
, mmu_kernel_ssize
);
1220 spin_lock(&linear_map_hash_lock
);
1221 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1222 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1223 linear_map_hash_slots
[lmi
] = 0;
1224 spin_unlock(&linear_map_hash_lock
);
1225 if (hidx
& _PTEIDX_SECONDARY
)
1227 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1228 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1229 ppc_md
.hpte_invalidate(slot
, va
, mmu_linear_psize
, mmu_kernel_ssize
, 0);
1232 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1234 unsigned long flags
, vaddr
, lmi
;
1237 local_irq_save(flags
);
1238 for (i
= 0; i
< numpages
; i
++, page
++) {
1239 vaddr
= (unsigned long)page_address(page
);
1240 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1241 if (lmi
>= linear_map_hash_count
)
1244 kernel_map_linear_page(vaddr
, lmi
);
1246 kernel_unmap_linear_page(vaddr
, lmi
);
1248 local_irq_restore(flags
);
1250 #endif /* CONFIG_DEBUG_PAGEALLOC */
1252 void setup_initial_memory_limit(phys_addr_t first_memblock_base
,
1253 phys_addr_t first_memblock_size
)
1255 /* We don't currently support the first MEMBLOCK not mapping 0
1256 * physical on those processors
1258 BUG_ON(first_memblock_base
!= 0);
1260 /* On LPAR systems, the first entry is our RMA region,
1261 * non-LPAR 64-bit hash MMU systems don't have a limitation
1262 * on real mode access, but using the first entry works well
1263 * enough. We also clamp it to 1G to avoid some funky things
1264 * such as RTAS bugs etc...
1266 ppc64_rma_size
= min_t(u64
, first_memblock_size
, 0x40000000);
1268 /* Finally limit subsequent allocations */
1269 memblock_set_current_limit(ppc64_rma_size
);