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powerpc/fadump: Do not allow hot-remove memory from fadump reserved area.
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-mpc.c
blobd94f05c8b8b7934f1b43dc2af13dd9496ecabe29
1 /*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched/signal.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/slab.h>
23
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/fsl_devices.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30
31 #include <asm/mpc52xx.h>
32 #include <asm/mpc85xx.h>
33 #include <sysdev/fsl_soc.h>
34
35 #define DRV_NAME "mpc-i2c"
36
37 #define MPC_I2C_CLOCK_LEGACY 0
38 #define MPC_I2C_CLOCK_PRESERVE (~0U)
39
40 #define MPC_I2C_FDR 0x04
41 #define MPC_I2C_CR 0x08
42 #define MPC_I2C_SR 0x0c
43 #define MPC_I2C_DR 0x10
44 #define MPC_I2C_DFSRR 0x14
45
46 #define CCR_MEN 0x80
47 #define CCR_MIEN 0x40
48 #define CCR_MSTA 0x20
49 #define CCR_MTX 0x10
50 #define CCR_TXAK 0x08
51 #define CCR_RSTA 0x04
52
53 #define CSR_MCF 0x80
54 #define CSR_MAAS 0x40
55 #define CSR_MBB 0x20
56 #define CSR_MAL 0x10
57 #define CSR_SRW 0x04
58 #define CSR_MIF 0x02
59 #define CSR_RXAK 0x01
60
61 struct mpc_i2c {
62 struct device *dev;
63 void __iomem *base;
64 u32 interrupt;
65 wait_queue_head_t queue;
66 struct i2c_adapter adap;
67 int irq;
68 u32 real_clk;
69 #ifdef CONFIG_PM_SLEEP
70 u8 fdr, dfsrr;
71 #endif
72 struct clk *clk_per;
73 };
74
75 struct mpc_i2c_divider {
76 u16 divider;
77 u16 fdr; /* including dfsrr */
78 };
79
80 struct mpc_i2c_data {
81 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
82 };
83
84 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
85 {
86 writeb(x, i2c->base + MPC_I2C_CR);
87 }
88
89 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
90 {
91 struct mpc_i2c *i2c = dev_id;
92 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
93 /* Read again to allow register to stabilise */
94 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
95 writeb(0, i2c->base + MPC_I2C_SR);
96 wake_up(&i2c->queue);
97 return IRQ_HANDLED;
98 }
99 return IRQ_NONE;
100 }
101
102 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
103 * the bus, because it wants to send ACK.
104 * Following sequence of enabling/disabling and sending start/stop generates
105 * the 9 pulses, so it's all OK.
106 */
107 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
108 {
109 int k;
110 u32 delay_val = 1000000 / i2c->real_clk + 1;
111
112 if (delay_val < 2)
113 delay_val = 2;
114
115 for (k = 9; k; k--) {
116 writeccr(i2c, 0);
117 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
118 readb(i2c->base + MPC_I2C_DR);
119 writeccr(i2c, CCR_MEN);
120 udelay(delay_val << 1);
121 }
122 }
123
124 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
125 {
126 unsigned long orig_jiffies = jiffies;
127 u32 cmd_err;
128 int result = 0;
129
130 if (!i2c->irq) {
131 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
132 schedule();
133 if (time_after(jiffies, orig_jiffies + timeout)) {
134 dev_dbg(i2c->dev, "timeout\n");
135 writeccr(i2c, 0);
136 result = -ETIMEDOUT;
137 break;
138 }
139 }
140 cmd_err = readb(i2c->base + MPC_I2C_SR);
141 writeb(0, i2c->base + MPC_I2C_SR);
142 } else {
143 /* Interrupt mode */
144 result = wait_event_timeout(i2c->queue,
145 (i2c->interrupt & CSR_MIF), timeout);
146
147 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
148 dev_dbg(i2c->dev, "wait timeout\n");
149 writeccr(i2c, 0);
150 result = -ETIMEDOUT;
151 }
152
153 cmd_err = i2c->interrupt;
154 i2c->interrupt = 0;
155 }
156
157 if (result < 0)
158 return result;
159
160 if (!(cmd_err & CSR_MCF)) {
161 dev_dbg(i2c->dev, "unfinished\n");
162 return -EIO;
163 }
164
165 if (cmd_err & CSR_MAL) {
166 dev_dbg(i2c->dev, "MAL\n");
167 return -EAGAIN;
168 }
169
170 if (writing && (cmd_err & CSR_RXAK)) {
171 dev_dbg(i2c->dev, "No RXAK\n");
172 /* generate stop */
173 writeccr(i2c, CCR_MEN);
174 return -ENXIO;
175 }
176 return 0;
177 }
178
179 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
180 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
181 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
182 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
183 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
184 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
185 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
186 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
187 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
188 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
189 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
190 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
191 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
192 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
193 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
194 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
195 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
196 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
197 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
198 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
199 };
200
201 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
202 u32 *real_clk)
203 {
204 const struct mpc_i2c_divider *div = NULL;
205 unsigned int pvr = mfspr(SPRN_PVR);
206 u32 divider;
207 int i;
208
209 if (clock == MPC_I2C_CLOCK_LEGACY) {
210 /* see below - default fdr = 0x3f -> div = 2048 */
211 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
212 return -EINVAL;
213 }
214
215 /* Determine divider value */
216 divider = mpc5xxx_get_bus_frequency(node) / clock;
217
218 /*
219 * We want to choose an FDR/DFSR that generates an I2C bus speed that
220 * is equal to or lower than the requested speed.
221 */
222 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
223 div = &mpc_i2c_dividers_52xx[i];
224 /* Old MPC5200 rev A CPUs do not support the high bits */
225 if (div->fdr & 0xc0 && pvr == 0x80822011)
226 continue;
227 if (div->divider >= divider)
228 break;
229 }
230
231 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
232 return (int)div->fdr;
233 }
234
235 static void mpc_i2c_setup_52xx(struct device_node *node,
236 struct mpc_i2c *i2c,
237 u32 clock)
238 {
239 int ret, fdr;
240
241 if (clock == MPC_I2C_CLOCK_PRESERVE) {
242 dev_dbg(i2c->dev, "using fdr %d\n",
243 readb(i2c->base + MPC_I2C_FDR));
244 return;
245 }
246
247 ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
248 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
249
250 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
251
252 if (ret >= 0)
253 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
254 fdr);
255 }
256 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
257 static void mpc_i2c_setup_52xx(struct device_node *node,
258 struct mpc_i2c *i2c,
259 u32 clock)
260 {
261 }
262 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
263
264 #ifdef CONFIG_PPC_MPC512x
265 static void mpc_i2c_setup_512x(struct device_node *node,
266 struct mpc_i2c *i2c,
267 u32 clock)
268 {
269 struct device_node *node_ctrl;
270 void __iomem *ctrl;
271 const u32 *pval;
272 u32 idx;
273
274 /* Enable I2C interrupts for mpc5121 */
275 node_ctrl = of_find_compatible_node(NULL, NULL,
276 "fsl,mpc5121-i2c-ctrl");
277 if (node_ctrl) {
278 ctrl = of_iomap(node_ctrl, 0);
279 if (ctrl) {
280 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
281 pval = of_get_property(node, "reg", NULL);
282 idx = (*pval & 0xff) / 0x20;
283 setbits32(ctrl, 1 << (24 + idx * 2));
284 iounmap(ctrl);
285 }
286 of_node_put(node_ctrl);
287 }
288
289 /* The clock setup for the 52xx works also fine for the 512x */
290 mpc_i2c_setup_52xx(node, i2c, clock);
291 }
292 #else /* CONFIG_PPC_MPC512x */
293 static void mpc_i2c_setup_512x(struct device_node *node,
294 struct mpc_i2c *i2c,
295 u32 clock)
296 {
297 }
298 #endif /* CONFIG_PPC_MPC512x */
299
300 #ifdef CONFIG_FSL_SOC
301 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
302 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
303 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
304 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
305 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
306 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
307 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
308 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
309 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
310 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
311 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
312 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
313 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
314 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
315 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
316 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
317 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
318 {49152, 0x011e}, {61440, 0x011f}
319 };
320
321 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
322 {
323 struct device_node *node;
324 u32 __iomem *reg;
325 u32 val = 0;
326
327 node = of_find_node_by_name(NULL, "global-utilities");
328 if (node) {
329 const u32 *prop = of_get_property(node, "reg", NULL);
330 if (prop) {
331 /*
332 * Map and check POR Device Status Register 2
333 * (PORDEVSR2) at 0xE0014. Note than while MPC8533
334 * and MPC8544 indicate SEC frequency ratio
335 * configuration as bit 26 in PORDEVSR2, other MPC8xxx
336 * parts may store it differently or may not have it
337 * at all.
338 */
339 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
340 if (!reg)
341 printk(KERN_ERR
342 "Error: couldn't map PORDEVSR2\n");
343 else
344 val = in_be32(reg) & 0x00000020; /* sec-cfg */
345 iounmap(reg);
346 }
347 }
348 of_node_put(node);
349
350 return val;
351 }
352
353 static u32 mpc_i2c_get_prescaler_8xxx(void)
354 {
355 /*
356 * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
357 * may have prescaler 1, 2, or 3, depending on the power-on
358 * configuration.
359 */
360 u32 prescaler = 1;
361
362 /* mpc85xx */
363 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
364 || pvr_version_is(PVR_VER_E500MC)
365 || pvr_version_is(PVR_VER_E5500)
366 || pvr_version_is(PVR_VER_E6500)) {
367 unsigned int svr = mfspr(SPRN_SVR);
368
369 if ((SVR_SOC_VER(svr) == SVR_8540)
370 || (SVR_SOC_VER(svr) == SVR_8541)
371 || (SVR_SOC_VER(svr) == SVR_8560)
372 || (SVR_SOC_VER(svr) == SVR_8555)
373 || (SVR_SOC_VER(svr) == SVR_8610))
374 /* the above 85xx SoCs have prescaler 1 */
375 prescaler = 1;
376 else if ((SVR_SOC_VER(svr) == SVR_8533)
377 || (SVR_SOC_VER(svr) == SVR_8544))
378 /* the above 85xx SoCs have prescaler 3 or 2 */
379 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
380 else
381 /* all the other 85xx have prescaler 2 */
382 prescaler = 2;
383 }
384
385 return prescaler;
386 }
387
388 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
389 u32 *real_clk)
390 {
391 const struct mpc_i2c_divider *div = NULL;
392 u32 prescaler = mpc_i2c_get_prescaler_8xxx();
393 u32 divider;
394 int i;
395
396 if (clock == MPC_I2C_CLOCK_LEGACY) {
397 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
398 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
399 return -EINVAL;
400 }
401
402 divider = fsl_get_sys_freq() / clock / prescaler;
403
404 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
405 fsl_get_sys_freq(), clock, divider);
406
407 /*
408 * We want to choose an FDR/DFSR that generates an I2C bus speed that
409 * is equal to or lower than the requested speed.
410 */
411 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
412 div = &mpc_i2c_dividers_8xxx[i];
413 if (div->divider >= divider)
414 break;
415 }
416
417 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
418 return div ? (int)div->fdr : -EINVAL;
419 }
420
421 static void mpc_i2c_setup_8xxx(struct device_node *node,
422 struct mpc_i2c *i2c,
423 u32 clock)
424 {
425 int ret, fdr;
426
427 if (clock == MPC_I2C_CLOCK_PRESERVE) {
428 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
429 readb(i2c->base + MPC_I2C_DFSRR),
430 readb(i2c->base + MPC_I2C_FDR));
431 return;
432 }
433
434 ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
435 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
436
437 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
438 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
439
440 if (ret >= 0)
441 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
442 i2c->real_clk, fdr >> 8, fdr & 0xff);
443 }
444
445 #else /* !CONFIG_FSL_SOC */
446 static void mpc_i2c_setup_8xxx(struct device_node *node,
447 struct mpc_i2c *i2c,
448 u32 clock)
449 {
450 }
451 #endif /* CONFIG_FSL_SOC */
452
453 static void mpc_i2c_start(struct mpc_i2c *i2c)
454 {
455 /* Clear arbitration */
456 writeb(0, i2c->base + MPC_I2C_SR);
457 /* Start with MEN */
458 writeccr(i2c, CCR_MEN);
459 }
460
461 static void mpc_i2c_stop(struct mpc_i2c *i2c)
462 {
463 writeccr(i2c, CCR_MEN);
464 }
465
466 static int mpc_write(struct mpc_i2c *i2c, int target,
467 const u8 *data, int length, int restart)
468 {
469 int i, result;
470 unsigned timeout = i2c->adap.timeout;
471 u32 flags = restart ? CCR_RSTA : 0;
472
473 /* Start as master */
474 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
475 /* Write target byte */
476 writeb((target << 1), i2c->base + MPC_I2C_DR);
477
478 result = i2c_wait(i2c, timeout, 1);
479 if (result < 0)
480 return result;
481
482 for (i = 0; i < length; i++) {
483 /* Write data byte */
484 writeb(data[i], i2c->base + MPC_I2C_DR);
485
486 result = i2c_wait(i2c, timeout, 1);
487 if (result < 0)
488 return result;
489 }
490
491 return 0;
492 }
493
494 static int mpc_read(struct mpc_i2c *i2c, int target,
495 u8 *data, int length, int restart, bool recv_len)
496 {
497 unsigned timeout = i2c->adap.timeout;
498 int i, result;
499 u32 flags = restart ? CCR_RSTA : 0;
500
501 /* Switch to read - restart */
502 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
503 /* Write target address byte - this time with the read flag set */
504 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
505
506 result = i2c_wait(i2c, timeout, 1);
507 if (result < 0)
508 return result;
509
510 if (length) {
511 if (length == 1 && !recv_len)
512 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
513 else
514 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
515 /* Dummy read */
516 readb(i2c->base + MPC_I2C_DR);
517 }
518
519 for (i = 0; i < length; i++) {
520 u8 byte;
521
522 result = i2c_wait(i2c, timeout, 0);
523 if (result < 0)
524 return result;
525
526 /*
527 * For block reads, we have to know the total length (1st byte)
528 * before we can determine if we are done.
529 */
530 if (i || !recv_len) {
531 /* Generate txack on next to last byte */
532 if (i == length - 2)
533 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
534 | CCR_TXAK);
535 /* Do not generate stop on last byte */
536 if (i == length - 1)
537 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
538 | CCR_MTX);
539 }
540
541 byte = readb(i2c->base + MPC_I2C_DR);
542
543 /*
544 * Adjust length if first received byte is length.
545 * The length is 1 length byte plus actually data length
546 */
547 if (i == 0 && recv_len) {
548 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
549 return -EPROTO;
550 length += byte;
551 /*
552 * For block reads, generate txack here if data length
553 * is 1 byte (total length is 2 bytes).
554 */
555 if (length == 2)
556 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
557 | CCR_TXAK);
558 }
559 data[i] = byte;
560 }
561
562 return length;
563 }
564
565 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
566 {
567 struct i2c_msg *pmsg;
568 int i;
569 int ret = 0;
570 unsigned long orig_jiffies = jiffies;
571 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
572
573 mpc_i2c_start(i2c);
574
575 /* Allow bus up to 1s to become not busy */
576 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
577 if (signal_pending(current)) {
578 dev_dbg(i2c->dev, "Interrupted\n");
579 writeccr(i2c, 0);
580 return -EINTR;
581 }
582 if (time_after(jiffies, orig_jiffies + HZ)) {
583 u8 status = readb(i2c->base + MPC_I2C_SR);
584
585 dev_dbg(i2c->dev, "timeout\n");
586 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
587 writeb(status & ~CSR_MAL,
588 i2c->base + MPC_I2C_SR);
589 mpc_i2c_fixup(i2c);
590 }
591 return -EIO;
592 }
593 schedule();
594 }
595
596 for (i = 0; ret >= 0 && i < num; i++) {
597 pmsg = &msgs[i];
598 dev_dbg(i2c->dev,
599 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
600 pmsg->flags & I2C_M_RD ? "read" : "write",
601 pmsg->len, pmsg->addr, i + 1, num);
602 if (pmsg->flags & I2C_M_RD) {
603 bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
604
605 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
606 recv_len);
607 if (recv_len && ret > 0)
608 pmsg->len = ret;
609 } else {
610 ret =
611 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
612 }
613 }
614 mpc_i2c_stop(i2c); /* Initiate STOP */
615 orig_jiffies = jiffies;
616 /* Wait until STOP is seen, allow up to 1 s */
617 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
618 if (time_after(jiffies, orig_jiffies + HZ)) {
619 u8 status = readb(i2c->base + MPC_I2C_SR);
620
621 dev_dbg(i2c->dev, "timeout\n");
622 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
623 writeb(status & ~CSR_MAL,
624 i2c->base + MPC_I2C_SR);
625 mpc_i2c_fixup(i2c);
626 }
627 return -EIO;
628 }
629 cond_resched();
630 }
631 return (ret < 0) ? ret : num;
632 }
633
634 static u32 mpc_functionality(struct i2c_adapter *adap)
635 {
636 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
637 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
638 }
639
640 static const struct i2c_algorithm mpc_algo = {
641 .master_xfer = mpc_xfer,
642 .functionality = mpc_functionality,
643 };
644
645 static struct i2c_adapter mpc_ops = {
646 .owner = THIS_MODULE,
647 .algo = &mpc_algo,
648 .timeout = HZ,
649 };
650
651 static const struct of_device_id mpc_i2c_of_match[];
652 static int fsl_i2c_probe(struct platform_device *op)
653 {
654 const struct of_device_id *match;
655 struct mpc_i2c *i2c;
656 const u32 *prop;
657 u32 clock = MPC_I2C_CLOCK_LEGACY;
658 int result = 0;
659 int plen;
660 struct resource res;
661 struct clk *clk;
662 int err;
663
664 match = of_match_device(mpc_i2c_of_match, &op->dev);
665 if (!match)
666 return -EINVAL;
667
668 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
669 if (!i2c)
670 return -ENOMEM;
671
672 i2c->dev = &op->dev; /* for debug and error output */
673
674 init_waitqueue_head(&i2c->queue);
675
676 i2c->base = of_iomap(op->dev.of_node, 0);
677 if (!i2c->base) {
678 dev_err(i2c->dev, "failed to map controller\n");
679 result = -ENOMEM;
680 goto fail_map;
681 }
682
683 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
684 if (i2c->irq) { /* no i2c->irq implies polling */
685 result = request_irq(i2c->irq, mpc_i2c_isr,
686 IRQF_SHARED, "i2c-mpc", i2c);
687 if (result < 0) {
688 dev_err(i2c->dev, "failed to attach interrupt\n");
689 goto fail_request;
690 }
691 }
692
693 /*
694 * enable clock for the I2C peripheral (non fatal),
695 * keep a reference upon successful allocation
696 */
697 clk = devm_clk_get(&op->dev, NULL);
698 if (!IS_ERR(clk)) {
699 err = clk_prepare_enable(clk);
700 if (err) {
701 dev_err(&op->dev, "failed to enable clock\n");
702 goto fail_request;
703 } else {
704 i2c->clk_per = clk;
705 }
706 }
707
708 if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
709 clock = MPC_I2C_CLOCK_PRESERVE;
710 } else {
711 prop = of_get_property(op->dev.of_node, "clock-frequency",
712 &plen);
713 if (prop && plen == sizeof(u32))
714 clock = *prop;
715 }
716
717 if (match->data) {
718 const struct mpc_i2c_data *data = match->data;
719 data->setup(op->dev.of_node, i2c, clock);
720 } else {
721 /* Backwards compatibility */
722 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
723 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
724 }
725
726 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
727 if (prop && plen == sizeof(u32)) {
728 mpc_ops.timeout = *prop * HZ / 1000000;
729 if (mpc_ops.timeout < 5)
730 mpc_ops.timeout = 5;
731 }
732 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
733
734 platform_set_drvdata(op, i2c);
735
736 i2c->adap = mpc_ops;
737 of_address_to_resource(op->dev.of_node, 0, &res);
738 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
739 "MPC adapter at 0x%llx", (unsigned long long)res.start);
740 i2c_set_adapdata(&i2c->adap, i2c);
741 i2c->adap.dev.parent = &op->dev;
742 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
743
744 result = i2c_add_adapter(&i2c->adap);
745 if (result < 0)
746 goto fail_add;
747
748 return result;
749
750 fail_add:
751 if (i2c->clk_per)
752 clk_disable_unprepare(i2c->clk_per);
753 free_irq(i2c->irq, i2c);
754 fail_request:
755 irq_dispose_mapping(i2c->irq);
756 iounmap(i2c->base);
757 fail_map:
758 kfree(i2c);
759 return result;
760 };
761
762 static int fsl_i2c_remove(struct platform_device *op)
763 {
764 struct mpc_i2c *i2c = platform_get_drvdata(op);
765
766 i2c_del_adapter(&i2c->adap);
767
768 if (i2c->clk_per)
769 clk_disable_unprepare(i2c->clk_per);
770
771 if (i2c->irq)
772 free_irq(i2c->irq, i2c);
773
774 irq_dispose_mapping(i2c->irq);
775 iounmap(i2c->base);
776 kfree(i2c);
777 return 0;
778 };
779
780 #ifdef CONFIG_PM_SLEEP
781 static int mpc_i2c_suspend(struct device *dev)
782 {
783 struct mpc_i2c *i2c = dev_get_drvdata(dev);
784
785 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
786 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
787
788 return 0;
789 }
790
791 static int mpc_i2c_resume(struct device *dev)
792 {
793 struct mpc_i2c *i2c = dev_get_drvdata(dev);
794
795 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
796 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
797
798 return 0;
799 }
800
801 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
802 #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
803 #else
804 #define MPC_I2C_PM_OPS NULL
805 #endif
806
807 static const struct mpc_i2c_data mpc_i2c_data_512x = {
808 .setup = mpc_i2c_setup_512x,
809 };
810
811 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
812 .setup = mpc_i2c_setup_52xx,
813 };
814
815 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
816 .setup = mpc_i2c_setup_8xxx,
817 };
818
819 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
820 .setup = mpc_i2c_setup_8xxx,
821 };
822
823 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
824 .setup = mpc_i2c_setup_8xxx,
825 };
826
827 static const struct of_device_id mpc_i2c_of_match[] = {
828 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
829 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
830 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
831 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
832 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
833 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
834 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
835 /* Backward compatibility */
836 {.compatible = "fsl-i2c", },
837 {},
838 };
839 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
840
841 /* Structure for a device driver */
842 static struct platform_driver mpc_i2c_driver = {
843 .probe = fsl_i2c_probe,
844 .remove = fsl_i2c_remove,
845 .driver = {
846 .name = DRV_NAME,
847 .of_match_table = mpc_i2c_of_match,
848 .pm = MPC_I2C_PM_OPS,
849 },
850 };
851
852 module_platform_driver(mpc_i2c_driver);
853
854 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
855 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
856 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
857 MODULE_LICENSE("GPL");
Linux with added FPC-III support